3c726f8dee
Adds a new CONFIG_PPC_64K_PAGES which, when enabled, changes the kernel base page size to 64K. The resulting kernel still boots on any hardware. On current machines with 4K pages support only, the kernel will maintain 16 "subpages" for each 64K page transparently. Note that while real 64K capable HW has been tested, the current patch will not enable it yet as such hardware is not released yet, and I'm still verifying with the firmware architects the proper to get the information from the newer hypervisors. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
235 lines
6.1 KiB
ArmAsm
235 lines
6.1 KiB
ArmAsm
/*
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* arch/ppc64/mm/slb_low.S
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*
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* Low-level SLB routines
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*
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* Copyright (C) 2004 David Gibson <dwg@au.ibm.com>, IBM
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*
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* Based on earlier C version:
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* Dave Engebretsen and Mike Corrigan {engebret|mikejc}@us.ibm.com
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* Copyright (c) 2001 Dave Engebretsen
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* Copyright (C) 2002 Anton Blanchard <anton@au.ibm.com>, IBM
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/config.h>
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#include <asm/processor.h>
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#include <asm/ppc_asm.h>
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#include <asm/asm-offsets.h>
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#include <asm/cputable.h>
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#include <asm/page.h>
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#include <asm/mmu.h>
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#include <asm/pgtable.h>
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/* void slb_allocate_realmode(unsigned long ea);
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*
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* Create an SLB entry for the given EA (user or kernel).
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* r3 = faulting address, r13 = PACA
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* r9, r10, r11 are clobbered by this function
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* No other registers are examined or changed.
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*/
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_GLOBAL(slb_allocate_realmode)
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/* r3 = faulting address */
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srdi r9,r3,60 /* get region */
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srdi r10,r3,28 /* get esid */
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cmpldi cr7,r9,0xc /* cmp KERNELBASE for later use */
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/* r3 = address, r10 = esid, cr7 = <>KERNELBASE */
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blt cr7,0f /* user or kernel? */
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/* kernel address: proto-VSID = ESID */
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/* WARNING - MAGIC: we don't use the VSID 0xfffffffff, but
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* this code will generate the protoVSID 0xfffffffff for the
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* top segment. That's ok, the scramble below will translate
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* it to VSID 0, which is reserved as a bad VSID - one which
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* will never have any pages in it. */
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/* Check if hitting the linear mapping of the vmalloc/ioremap
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* kernel space
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*/
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bne cr7,1f
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/* Linear mapping encoding bits, the "li" instruction below will
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* be patched by the kernel at boot
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*/
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_GLOBAL(slb_miss_kernel_load_linear)
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li r11,0
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b slb_finish_load
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1: /* vmalloc/ioremap mapping encoding bits, the "li" instruction below
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* will be patched by the kernel at boot
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*/
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_GLOBAL(slb_miss_kernel_load_virtual)
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li r11,0
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b slb_finish_load
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0: /* user address: proto-VSID = context << 15 | ESID. First check
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* if the address is within the boundaries of the user region
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*/
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srdi. r9,r10,USER_ESID_BITS
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bne- 8f /* invalid ea bits set */
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/* Figure out if the segment contains huge pages */
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#ifdef CONFIG_HUGETLB_PAGE
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BEGIN_FTR_SECTION
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b 1f
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END_FTR_SECTION_IFCLR(CPU_FTR_16M_PAGE)
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lhz r9,PACAHIGHHTLBAREAS(r13)
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srdi r11,r10,(HTLB_AREA_SHIFT-SID_SHIFT)
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srd r9,r9,r11
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lhz r11,PACALOWHTLBAREAS(r13)
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srd r11,r11,r10
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or. r9,r9,r11
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beq 1f
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_GLOBAL(slb_miss_user_load_huge)
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li r11,0
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b 2f
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1:
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#endif /* CONFIG_HUGETLB_PAGE */
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_GLOBAL(slb_miss_user_load_normal)
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li r11,0
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2:
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ld r9,PACACONTEXTID(r13)
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rldimi r10,r9,USER_ESID_BITS,0
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b slb_finish_load
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8: /* invalid EA */
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li r10,0 /* BAD_VSID */
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li r11,SLB_VSID_USER /* flags don't much matter */
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b slb_finish_load
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#ifdef __DISABLED__
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/* void slb_allocate_user(unsigned long ea);
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*
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* Create an SLB entry for the given EA (user or kernel).
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* r3 = faulting address, r13 = PACA
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* r9, r10, r11 are clobbered by this function
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* No other registers are examined or changed.
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*
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* It is called with translation enabled in order to be able to walk the
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* page tables. This is not currently used.
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*/
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_GLOBAL(slb_allocate_user)
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/* r3 = faulting address */
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srdi r10,r3,28 /* get esid */
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crset 4*cr7+lt /* set "user" flag for later */
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/* check if we fit in the range covered by the pagetables*/
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srdi. r9,r3,PGTABLE_EADDR_SIZE
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crnot 4*cr0+eq,4*cr0+eq
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beqlr
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/* now we need to get to the page tables in order to get the page
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* size encoding from the PMD. In the future, we'll be able to deal
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* with 1T segments too by getting the encoding from the PGD instead
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*/
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ld r9,PACAPGDIR(r13)
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cmpldi cr0,r9,0
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beqlr
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rlwinm r11,r10,8,25,28
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ldx r9,r9,r11 /* get pgd_t */
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cmpldi cr0,r9,0
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beqlr
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rlwinm r11,r10,3,17,28
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ldx r9,r9,r11 /* get pmd_t */
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cmpldi cr0,r9,0
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beqlr
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/* build vsid flags */
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andi. r11,r9,SLB_VSID_LLP
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ori r11,r11,SLB_VSID_USER
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/* get context to calculate proto-VSID */
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ld r9,PACACONTEXTID(r13)
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rldimi r10,r9,USER_ESID_BITS,0
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/* fall through slb_finish_load */
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#endif /* __DISABLED__ */
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/*
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* Finish loading of an SLB entry and return
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*
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* r3 = EA, r10 = proto-VSID, r11 = flags, clobbers r9, cr7 = <>KERNELBASE
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*/
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slb_finish_load:
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ASM_VSID_SCRAMBLE(r10,r9)
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rldimi r11,r10,SLB_VSID_SHIFT,16 /* combine VSID and flags */
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/* r3 = EA, r11 = VSID data */
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/*
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* Find a slot, round robin. Previously we tried to find a
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* free slot first but that took too long. Unfortunately we
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* dont have any LRU information to help us choose a slot.
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*/
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#ifdef CONFIG_PPC_ISERIES
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/*
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* On iSeries, the "bolted" stack segment can be cast out on
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* shared processor switch so we need to check for a miss on
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* it and restore it to the right slot.
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*/
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ld r9,PACAKSAVE(r13)
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clrrdi r9,r9,28
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clrrdi r3,r3,28
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li r10,SLB_NUM_BOLTED-1 /* Stack goes in last bolted slot */
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cmpld r9,r3
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beq 3f
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#endif /* CONFIG_PPC_ISERIES */
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ld r10,PACASTABRR(r13)
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addi r10,r10,1
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/* use a cpu feature mask if we ever change our slb size */
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cmpldi r10,SLB_NUM_ENTRIES
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blt+ 4f
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li r10,SLB_NUM_BOLTED
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4:
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std r10,PACASTABRR(r13)
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3:
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rldimi r3,r10,0,36 /* r3= EA[0:35] | entry */
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oris r10,r3,SLB_ESID_V@h /* r3 |= SLB_ESID_V */
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/* r3 = ESID data, r11 = VSID data */
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/*
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* No need for an isync before or after this slbmte. The exception
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* we enter with and the rfid we exit with are context synchronizing.
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*/
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slbmte r11,r10
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/* we're done for kernel addresses */
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crclr 4*cr0+eq /* set result to "success" */
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bgelr cr7
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/* Update the slb cache */
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lhz r3,PACASLBCACHEPTR(r13) /* offset = paca->slb_cache_ptr */
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cmpldi r3,SLB_CACHE_ENTRIES
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bge 1f
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/* still room in the slb cache */
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sldi r11,r3,1 /* r11 = offset * sizeof(u16) */
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rldicl r10,r10,36,28 /* get low 16 bits of the ESID */
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add r11,r11,r13 /* r11 = (u16 *)paca + offset */
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sth r10,PACASLBCACHE(r11) /* paca->slb_cache[offset] = esid */
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addi r3,r3,1 /* offset++ */
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b 2f
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1: /* offset >= SLB_CACHE_ENTRIES */
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li r3,SLB_CACHE_ENTRIES+1
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2:
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sth r3,PACASLBCACHEPTR(r13) /* paca->slb_cache_ptr = offset */
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crclr 4*cr0+eq /* set result to "success" */
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blr
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