b4cd605ca9
Because the common underlying code for ARM kprobes and uprobes needs to share a common architecrure-specific context structure, and because the generic kprobes include file insists on defining this to a dummy structure when kprobes is not configured, a new common structure is required which can exist when uprobes is configured without kprobes. In this case kprobes will define a dummy structure, but without the define aliasing the two structure tags it will not affect uprobes and the shared probes code. Signed-off-by: David A. Long <dave.long@linaro.org> Acked-by: Jon Medhurst <tixy@linaro.org>
343 lines
11 KiB
C
343 lines
11 KiB
C
/*
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* arch/arm/kernel/kprobes-decode.c
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*
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* Copyright (C) 2006, 2007 Motorola Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*/
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/*
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* We do not have hardware single-stepping on ARM, This
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* effort is further complicated by the ARM not having a
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* "next PC" register. Instructions that change the PC
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* can't be safely single-stepped in a MP environment, so
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* we have a lot of work to do:
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*
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* In the prepare phase:
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* *) If it is an instruction that does anything
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* with the CPU mode, we reject it for a kprobe.
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* (This is out of laziness rather than need. The
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* instructions could be simulated.)
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*
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* *) Otherwise, decode the instruction rewriting its
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* registers to take fixed, ordered registers and
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* setting a handler for it to run the instruction.
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*
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* In the execution phase by an instruction's handler:
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*
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* *) If the PC is written to by the instruction, the
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* instruction must be fully simulated in software.
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*
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* *) Otherwise, a modified form of the instruction is
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* directly executed. Its handler calls the
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* instruction in insn[0]. In insn[1] is a
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* "mov pc, lr" to return.
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*
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* Before calling, load up the reordered registers
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* from the original instruction's registers. If one
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* of the original input registers is the PC, compute
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* and adjust the appropriate input register.
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*
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* After call completes, copy the output registers to
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* the original instruction's original registers.
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*
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* We don't use a real breakpoint instruction since that
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* would have us in the kernel go from SVC mode to SVC
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* mode losing the link register. Instead we use an
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* undefined instruction. To simplify processing, the
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* undefined instruction used for kprobes must be reserved
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* exclusively for kprobes use.
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*
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* TODO: ifdef out some instruction decoding based on architecture.
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*/
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#include <linux/kernel.h>
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#include <linux/kprobes.h>
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#include <linux/ptrace.h>
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#include "kprobes.h"
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#include "probes-arm.h"
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#if __LINUX_ARM_ARCH__ >= 6
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#define BLX(reg) "blx "reg" \n\t"
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#else
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#define BLX(reg) "mov lr, pc \n\t" \
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"mov pc, "reg" \n\t"
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#endif
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static void __kprobes
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emulate_ldrdstrd(probes_opcode_t insn,
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struct arch_probes_insn *asi, struct pt_regs *regs)
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{
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unsigned long pc = regs->ARM_pc + 4;
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int rt = (insn >> 12) & 0xf;
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int rn = (insn >> 16) & 0xf;
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int rm = insn & 0xf;
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register unsigned long rtv asm("r0") = regs->uregs[rt];
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register unsigned long rt2v asm("r1") = regs->uregs[rt+1];
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register unsigned long rnv asm("r2") = (rn == 15) ? pc
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: regs->uregs[rn];
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register unsigned long rmv asm("r3") = regs->uregs[rm];
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__asm__ __volatile__ (
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BLX("%[fn]")
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: "=r" (rtv), "=r" (rt2v), "=r" (rnv)
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: "0" (rtv), "1" (rt2v), "2" (rnv), "r" (rmv),
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[fn] "r" (asi->insn_fn)
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: "lr", "memory", "cc"
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);
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regs->uregs[rt] = rtv;
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regs->uregs[rt+1] = rt2v;
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if (is_writeback(insn))
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regs->uregs[rn] = rnv;
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}
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static void __kprobes
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emulate_ldr(probes_opcode_t insn,
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struct arch_probes_insn *asi, struct pt_regs *regs)
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{
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unsigned long pc = regs->ARM_pc + 4;
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int rt = (insn >> 12) & 0xf;
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int rn = (insn >> 16) & 0xf;
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int rm = insn & 0xf;
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register unsigned long rtv asm("r0");
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register unsigned long rnv asm("r2") = (rn == 15) ? pc
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: regs->uregs[rn];
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register unsigned long rmv asm("r3") = regs->uregs[rm];
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__asm__ __volatile__ (
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BLX("%[fn]")
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: "=r" (rtv), "=r" (rnv)
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: "1" (rnv), "r" (rmv), [fn] "r" (asi->insn_fn)
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: "lr", "memory", "cc"
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);
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if (rt == 15)
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load_write_pc(rtv, regs);
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else
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regs->uregs[rt] = rtv;
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if (is_writeback(insn))
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regs->uregs[rn] = rnv;
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}
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static void __kprobes
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emulate_str(probes_opcode_t insn,
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struct arch_probes_insn *asi, struct pt_regs *regs)
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{
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unsigned long rtpc = regs->ARM_pc - 4 + str_pc_offset;
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unsigned long rnpc = regs->ARM_pc + 4;
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int rt = (insn >> 12) & 0xf;
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int rn = (insn >> 16) & 0xf;
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int rm = insn & 0xf;
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register unsigned long rtv asm("r0") = (rt == 15) ? rtpc
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: regs->uregs[rt];
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register unsigned long rnv asm("r2") = (rn == 15) ? rnpc
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: regs->uregs[rn];
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register unsigned long rmv asm("r3") = regs->uregs[rm];
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__asm__ __volatile__ (
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BLX("%[fn]")
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: "=r" (rnv)
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: "r" (rtv), "0" (rnv), "r" (rmv), [fn] "r" (asi->insn_fn)
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: "lr", "memory", "cc"
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);
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if (is_writeback(insn))
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regs->uregs[rn] = rnv;
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}
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static void __kprobes
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emulate_rd12rn16rm0rs8_rwflags(probes_opcode_t insn,
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struct arch_probes_insn *asi, struct pt_regs *regs)
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{
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unsigned long pc = regs->ARM_pc + 4;
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int rd = (insn >> 12) & 0xf;
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int rn = (insn >> 16) & 0xf;
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int rm = insn & 0xf;
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int rs = (insn >> 8) & 0xf;
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register unsigned long rdv asm("r0") = regs->uregs[rd];
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register unsigned long rnv asm("r2") = (rn == 15) ? pc
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: regs->uregs[rn];
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register unsigned long rmv asm("r3") = (rm == 15) ? pc
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: regs->uregs[rm];
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register unsigned long rsv asm("r1") = regs->uregs[rs];
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unsigned long cpsr = regs->ARM_cpsr;
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__asm__ __volatile__ (
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"msr cpsr_fs, %[cpsr] \n\t"
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BLX("%[fn]")
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"mrs %[cpsr], cpsr \n\t"
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: "=r" (rdv), [cpsr] "=r" (cpsr)
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: "0" (rdv), "r" (rnv), "r" (rmv), "r" (rsv),
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"1" (cpsr), [fn] "r" (asi->insn_fn)
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: "lr", "memory", "cc"
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);
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if (rd == 15)
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alu_write_pc(rdv, regs);
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else
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regs->uregs[rd] = rdv;
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regs->ARM_cpsr = (regs->ARM_cpsr & ~APSR_MASK) | (cpsr & APSR_MASK);
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}
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static void __kprobes
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emulate_rd12rn16rm0_rwflags_nopc(probes_opcode_t insn,
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struct arch_probes_insn *asi, struct pt_regs *regs)
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{
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int rd = (insn >> 12) & 0xf;
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int rn = (insn >> 16) & 0xf;
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int rm = insn & 0xf;
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register unsigned long rdv asm("r0") = regs->uregs[rd];
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register unsigned long rnv asm("r2") = regs->uregs[rn];
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register unsigned long rmv asm("r3") = regs->uregs[rm];
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unsigned long cpsr = regs->ARM_cpsr;
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__asm__ __volatile__ (
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"msr cpsr_fs, %[cpsr] \n\t"
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BLX("%[fn]")
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"mrs %[cpsr], cpsr \n\t"
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: "=r" (rdv), [cpsr] "=r" (cpsr)
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: "0" (rdv), "r" (rnv), "r" (rmv),
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"1" (cpsr), [fn] "r" (asi->insn_fn)
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: "lr", "memory", "cc"
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);
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regs->uregs[rd] = rdv;
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regs->ARM_cpsr = (regs->ARM_cpsr & ~APSR_MASK) | (cpsr & APSR_MASK);
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}
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static void __kprobes
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emulate_rd16rn12rm0rs8_rwflags_nopc(probes_opcode_t insn,
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struct arch_probes_insn *asi,
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struct pt_regs *regs)
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{
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int rd = (insn >> 16) & 0xf;
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int rn = (insn >> 12) & 0xf;
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int rm = insn & 0xf;
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int rs = (insn >> 8) & 0xf;
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register unsigned long rdv asm("r2") = regs->uregs[rd];
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register unsigned long rnv asm("r0") = regs->uregs[rn];
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register unsigned long rmv asm("r3") = regs->uregs[rm];
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register unsigned long rsv asm("r1") = regs->uregs[rs];
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unsigned long cpsr = regs->ARM_cpsr;
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__asm__ __volatile__ (
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"msr cpsr_fs, %[cpsr] \n\t"
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BLX("%[fn]")
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"mrs %[cpsr], cpsr \n\t"
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: "=r" (rdv), [cpsr] "=r" (cpsr)
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: "0" (rdv), "r" (rnv), "r" (rmv), "r" (rsv),
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"1" (cpsr), [fn] "r" (asi->insn_fn)
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: "lr", "memory", "cc"
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);
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regs->uregs[rd] = rdv;
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regs->ARM_cpsr = (regs->ARM_cpsr & ~APSR_MASK) | (cpsr & APSR_MASK);
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}
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static void __kprobes
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emulate_rd12rm0_noflags_nopc(probes_opcode_t insn,
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struct arch_probes_insn *asi, struct pt_regs *regs)
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{
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int rd = (insn >> 12) & 0xf;
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int rm = insn & 0xf;
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register unsigned long rdv asm("r0") = regs->uregs[rd];
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register unsigned long rmv asm("r3") = regs->uregs[rm];
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__asm__ __volatile__ (
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BLX("%[fn]")
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: "=r" (rdv)
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: "0" (rdv), "r" (rmv), [fn] "r" (asi->insn_fn)
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: "lr", "memory", "cc"
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);
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regs->uregs[rd] = rdv;
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}
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static void __kprobes
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emulate_rdlo12rdhi16rn0rm8_rwflags_nopc(probes_opcode_t insn,
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struct arch_probes_insn *asi,
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struct pt_regs *regs)
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{
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int rdlo = (insn >> 12) & 0xf;
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int rdhi = (insn >> 16) & 0xf;
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int rn = insn & 0xf;
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int rm = (insn >> 8) & 0xf;
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register unsigned long rdlov asm("r0") = regs->uregs[rdlo];
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register unsigned long rdhiv asm("r2") = regs->uregs[rdhi];
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register unsigned long rnv asm("r3") = regs->uregs[rn];
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register unsigned long rmv asm("r1") = regs->uregs[rm];
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unsigned long cpsr = regs->ARM_cpsr;
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__asm__ __volatile__ (
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"msr cpsr_fs, %[cpsr] \n\t"
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BLX("%[fn]")
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"mrs %[cpsr], cpsr \n\t"
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: "=r" (rdlov), "=r" (rdhiv), [cpsr] "=r" (cpsr)
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: "0" (rdlov), "1" (rdhiv), "r" (rnv), "r" (rmv),
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"2" (cpsr), [fn] "r" (asi->insn_fn)
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: "lr", "memory", "cc"
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);
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regs->uregs[rdlo] = rdlov;
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regs->uregs[rdhi] = rdhiv;
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regs->ARM_cpsr = (regs->ARM_cpsr & ~APSR_MASK) | (cpsr & APSR_MASK);
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}
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const union decode_action kprobes_arm_actions[NUM_PROBES_ARM_ACTIONS] = {
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[PROBES_EMULATE_NONE] = {.handler = probes_emulate_none},
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[PROBES_SIMULATE_NOP] = {.handler = probes_simulate_nop},
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[PROBES_PRELOAD_IMM] = {.handler = probes_simulate_nop},
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[PROBES_PRELOAD_REG] = {.handler = probes_simulate_nop},
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[PROBES_BRANCH_IMM] = {.handler = simulate_blx1},
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[PROBES_MRS] = {.handler = simulate_mrs},
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[PROBES_BRANCH_REG] = {.handler = simulate_blx2bx},
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[PROBES_CLZ] = {.handler = emulate_rd12rm0_noflags_nopc},
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[PROBES_SATURATING_ARITHMETIC] = {
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.handler = emulate_rd12rn16rm0_rwflags_nopc},
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[PROBES_MUL1] = {.handler = emulate_rdlo12rdhi16rn0rm8_rwflags_nopc},
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[PROBES_MUL2] = {.handler = emulate_rd16rn12rm0rs8_rwflags_nopc},
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[PROBES_SWP] = {.handler = emulate_rd12rn16rm0_rwflags_nopc},
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[PROBES_LDRSTRD] = {.handler = emulate_ldrdstrd},
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[PROBES_LOAD_EXTRA] = {.handler = emulate_ldr},
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[PROBES_LOAD] = {.handler = emulate_ldr},
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[PROBES_STORE_EXTRA] = {.handler = emulate_str},
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[PROBES_STORE] = {.handler = emulate_str},
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[PROBES_MOV_IP_SP] = {.handler = simulate_mov_ipsp},
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[PROBES_DATA_PROCESSING_REG] = {
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.handler = emulate_rd12rn16rm0rs8_rwflags},
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[PROBES_DATA_PROCESSING_IMM] = {
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.handler = emulate_rd12rn16rm0rs8_rwflags},
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[PROBES_MOV_HALFWORD] = {.handler = emulate_rd12rm0_noflags_nopc},
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[PROBES_SEV] = {.handler = probes_emulate_none},
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[PROBES_WFE] = {.handler = probes_simulate_nop},
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[PROBES_SATURATE] = {.handler = emulate_rd12rn16rm0_rwflags_nopc},
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[PROBES_REV] = {.handler = emulate_rd12rm0_noflags_nopc},
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[PROBES_MMI] = {.handler = emulate_rd12rn16rm0_rwflags_nopc},
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[PROBES_PACK] = {.handler = emulate_rd12rn16rm0_rwflags_nopc},
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[PROBES_EXTEND] = {.handler = emulate_rd12rm0_noflags_nopc},
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[PROBES_EXTEND_ADD] = {.handler = emulate_rd12rn16rm0_rwflags_nopc},
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[PROBES_MUL_ADD_LONG] = {
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.handler = emulate_rdlo12rdhi16rn0rm8_rwflags_nopc},
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[PROBES_MUL_ADD] = {.handler = emulate_rd16rn12rm0rs8_rwflags_nopc},
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[PROBES_BITFIELD] = {.handler = emulate_rd12rm0_noflags_nopc},
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[PROBES_BRANCH] = {.handler = simulate_bbl},
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[PROBES_LDMSTM] = {.decoder = kprobe_decode_ldmstm}
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};
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