89127ed381
The problem has its root in the calculation of the set-port offsets (macro MCFGPIO_SETR() in arch/m68k/include/asm/gpio.h), this assumes that all ports have the same offset from the base port address (MCFGPIO_SETR) which is defined in mcf520xsim.h as an alias of MCFGIO_PSETR_BUSCTL. Because the BUSCTL and BE port do not have a set-register (see MCF5208 Reference Manual Page 13-10, Table 13-3) the offset calculations went wrong. Because the BE and BUSCTL port do not seem useful in these parts, as they lack a set register, I removed them and adapted the gpio chip bases which are also used for the offset-calculations. Now both setting and resetting the chip selects works as expected from userland and from the kernelspace. Signed-off-by: Peter Turczak <peter@turczak.de> Signed-off-by: Greg Ungerer <gerg@uclinux.org>
66 lines
2.4 KiB
C
66 lines
2.4 KiB
C
/*
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* Definitions for Freescale Coldfire QSPI module
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*
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* Copyright 2010 Steven King <sfking@fdwdc.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2
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* as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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*/
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#ifndef mcfqspi_h
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#define mcfqspi_h
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#if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x)
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#define MCFQSPI_IOBASE (MCF_IPSBAR + 0x340)
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#elif defined(CONFIG_M5249)
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#define MCFQSPI_IOBASE (MCF_MBAR + 0x300)
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#elif defined(CONFIG_M520x)
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#define MCFQSPI_IOBASE 0xFC05C000
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#elif defined(CONFIG_M532x)
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#define MCFQSPI_IOBASE 0xFC058000
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#endif
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#define MCFQSPI_IOSIZE 0x40
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/**
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* struct mcfqspi_cs_control - chip select control for the coldfire qspi driver
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* @setup: setup the control; allocate gpio's, etc. May be NULL.
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* @teardown: finish with the control; free gpio's, etc. May be NULL.
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* @select: output the signals to select the device. Can not be NULL.
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* @deselect: output the signals to deselect the device. Can not be NULL.
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*
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* The QSPI module has 4 hardware chip selects. We don't use them. Instead
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* platforms are required to supply a mcfqspi_cs_control as a part of the
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* platform data for each QSPI master controller. Only the select and
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* deselect functions are required.
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*/
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struct mcfqspi_cs_control {
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int (*setup)(struct mcfqspi_cs_control *);
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void (*teardown)(struct mcfqspi_cs_control *);
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void (*select)(struct mcfqspi_cs_control *, u8, bool);
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void (*deselect)(struct mcfqspi_cs_control *, u8, bool);
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};
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/**
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* struct mcfqspi_platform_data - platform data for the coldfire qspi driver
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* @bus_num: board specific identifier for this qspi driver.
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* @num_chipselects: number of chip selects supported by this qspi driver.
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* @cs_control: platform dependent chip select control.
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*/
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struct mcfqspi_platform_data {
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s16 bus_num;
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u16 num_chipselect;
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struct mcfqspi_cs_control *cs_control;
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};
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#endif /* mcfqspi_h */
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