5a31057fc0
Update the 64-bit hibernation code to support Book E CPUs. Some registers and instructions are not defined for Book3e (SDR reg, tlbia instruction). SDR: Storage Description Register. Book3S and Book3E have different address translation mode, we do not need HTABORG & HTABSIZE to translate virtual address to real address. More registers are saved in BookE-64bit.(TCR, SPRG1) Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
269 lines
5 KiB
ArmAsm
269 lines
5 KiB
ArmAsm
/*
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* PowerPC 64-bit swsusp implementation
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*
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* Copyright 2006 Johannes Berg <johannes@sipsolutions.net>
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*
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* GPLv2
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*/
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#include <linux/threads.h>
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#include <asm/processor.h>
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#include <asm/page.h>
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#include <asm/cputable.h>
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#include <asm/thread_info.h>
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#include <asm/ppc_asm.h>
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#include <asm/asm-offsets.h>
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/*
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* Structure for storing CPU registers on the save area.
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*/
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#define SL_r1 0x00 /* stack pointer */
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#define SL_PC 0x08
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#define SL_MSR 0x10
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#define SL_SDR1 0x18
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#define SL_XER 0x20
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#define SL_TB 0x40
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#define SL_r2 0x48
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#define SL_CR 0x50
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#define SL_LR 0x58
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#define SL_r12 0x60
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#define SL_r13 0x68
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#define SL_r14 0x70
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#define SL_r15 0x78
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#define SL_r16 0x80
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#define SL_r17 0x88
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#define SL_r18 0x90
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#define SL_r19 0x98
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#define SL_r20 0xa0
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#define SL_r21 0xa8
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#define SL_r22 0xb0
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#define SL_r23 0xb8
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#define SL_r24 0xc0
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#define SL_r25 0xc8
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#define SL_r26 0xd0
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#define SL_r27 0xd8
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#define SL_r28 0xe0
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#define SL_r29 0xe8
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#define SL_r30 0xf0
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#define SL_r31 0xf8
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#define SL_SPRG1 0x100
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#define SL_TCR 0x108
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#define SL_SIZE SL_TCR+8
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/* these macros rely on the save area being
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* pointed to by r11 */
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#define SAVE_SPR(register) \
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mfspr r0, SPRN_##register ;\
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std r0, SL_##register(r11)
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#define RESTORE_SPR(register) \
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ld r0, SL_##register(r11) ;\
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mtspr SPRN_##register, r0
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#define SAVE_SPECIAL(special) \
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mf##special r0 ;\
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std r0, SL_##special(r11)
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#define RESTORE_SPECIAL(special) \
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ld r0, SL_##special(r11) ;\
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mt##special r0
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#define SAVE_REGISTER(reg) \
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std reg, SL_##reg(r11)
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#define RESTORE_REGISTER(reg) \
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ld reg, SL_##reg(r11)
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/* space for storing cpu state */
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.section .data
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.align 5
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swsusp_save_area:
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.space SL_SIZE
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.section ".toc","aw"
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swsusp_save_area_ptr:
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.tc swsusp_save_area[TC],swsusp_save_area
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restore_pblist_ptr:
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.tc restore_pblist[TC],restore_pblist
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.section .text
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.align 5
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_GLOBAL(swsusp_arch_suspend)
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ld r11,swsusp_save_area_ptr@toc(r2)
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SAVE_SPECIAL(LR)
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SAVE_REGISTER(r1)
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SAVE_SPECIAL(CR)
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SAVE_SPECIAL(TB)
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SAVE_REGISTER(r2)
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SAVE_REGISTER(r12)
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SAVE_REGISTER(r13)
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SAVE_REGISTER(r14)
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SAVE_REGISTER(r15)
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SAVE_REGISTER(r16)
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SAVE_REGISTER(r17)
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SAVE_REGISTER(r18)
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SAVE_REGISTER(r19)
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SAVE_REGISTER(r20)
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SAVE_REGISTER(r21)
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SAVE_REGISTER(r22)
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SAVE_REGISTER(r23)
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SAVE_REGISTER(r24)
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SAVE_REGISTER(r25)
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SAVE_REGISTER(r26)
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SAVE_REGISTER(r27)
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SAVE_REGISTER(r28)
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SAVE_REGISTER(r29)
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SAVE_REGISTER(r30)
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SAVE_REGISTER(r31)
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SAVE_SPECIAL(MSR)
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SAVE_SPECIAL(XER)
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#ifdef CONFIG_PPC_BOOK3S_64
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SAVE_SPECIAL(SDR1)
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#else
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SAVE_SPR(TCR)
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/* Save SPRG1, SPRG1 be used save paca */
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SAVE_SPR(SPRG1)
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#endif
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/* we push the stack up 128 bytes but don't store the
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* stack pointer on the stack like a real stackframe */
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addi r1,r1,-128
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bl _iommu_save
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bl swsusp_save
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/* restore LR */
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ld r11,swsusp_save_area_ptr@toc(r2)
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RESTORE_SPECIAL(LR)
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addi r1,r1,128
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blr
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/* Resume code */
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_GLOBAL(swsusp_arch_resume)
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/* Stop pending alitvec streams and memory accesses */
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BEGIN_FTR_SECTION
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DSSALL
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END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
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sync
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ld r12,restore_pblist_ptr@toc(r2)
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ld r12,0(r12)
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cmpdi r12,0
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beq- nothing_to_copy
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li r15,PAGE_SIZE>>3
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copyloop:
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ld r13,pbe_address(r12)
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ld r14,pbe_orig_address(r12)
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mtctr r15
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li r10,0
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copy_page_loop:
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ldx r0,r10,r13
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stdx r0,r10,r14
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addi r10,r10,8
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bdnz copy_page_loop
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ld r12,pbe_next(r12)
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cmpdi r12,0
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bne+ copyloop
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nothing_to_copy:
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#ifdef CONFIG_PPC_BOOK3S_64
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/* flush caches */
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lis r3, 0x10
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mtctr r3
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li r3, 0
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ori r3, r3, CONFIG_KERNEL_START>>48
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li r0, 48
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sld r3, r3, r0
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li r0, 0
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1:
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dcbf r0,r3
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addi r3,r3,0x20
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bdnz 1b
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sync
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tlbia
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#endif
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ld r11,swsusp_save_area_ptr@toc(r2)
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RESTORE_SPECIAL(CR)
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/* restore timebase */
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/* load saved tb */
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ld r1, SL_TB(r11)
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/* get upper 32 bits of it */
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srdi r2, r1, 32
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/* clear tb lower to avoid wrap */
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li r0, 0
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mttbl r0
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/* set tb upper */
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mttbu r2
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/* set tb lower */
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mttbl r1
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/* restore registers */
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RESTORE_REGISTER(r1)
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RESTORE_REGISTER(r2)
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RESTORE_REGISTER(r12)
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RESTORE_REGISTER(r13)
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RESTORE_REGISTER(r14)
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RESTORE_REGISTER(r15)
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RESTORE_REGISTER(r16)
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RESTORE_REGISTER(r17)
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RESTORE_REGISTER(r18)
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RESTORE_REGISTER(r19)
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RESTORE_REGISTER(r20)
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RESTORE_REGISTER(r21)
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RESTORE_REGISTER(r22)
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RESTORE_REGISTER(r23)
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RESTORE_REGISTER(r24)
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RESTORE_REGISTER(r25)
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RESTORE_REGISTER(r26)
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RESTORE_REGISTER(r27)
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RESTORE_REGISTER(r28)
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RESTORE_REGISTER(r29)
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RESTORE_REGISTER(r30)
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RESTORE_REGISTER(r31)
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#ifdef CONFIG_PPC_BOOK3S_64
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/* can't use RESTORE_SPECIAL(MSR) */
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ld r0, SL_MSR(r11)
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mtmsrd r0, 0
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RESTORE_SPECIAL(SDR1)
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#else
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/* Restore SPRG1, be used to save paca */
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ld r0, SL_SPRG1(r11)
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mtsprg 1, r0
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RESTORE_SPECIAL(MSR)
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/* Restore TCR and clear any pending bits in TSR. */
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RESTORE_SPR(TCR)
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lis r0, (TSR_ENW | TSR_WIS | TSR_DIS | TSR_FIS)@h
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mtspr SPRN_TSR, r0
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/* Kick decrementer */
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li r0, 1
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mtdec r0
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/* Invalidate all tlbs */
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bl _tlbil_all
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#endif
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RESTORE_SPECIAL(XER)
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sync
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addi r1,r1,-128
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#ifdef CONFIG_PPC_BOOK3S_64
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bl slb_flush_and_rebolt
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#endif
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bl do_after_copyback
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addi r1,r1,128
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ld r11,swsusp_save_area_ptr@toc(r2)
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RESTORE_SPECIAL(LR)
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li r3, 0
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blr
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