18aecc2b64
This support was partially present in the existing code (look for "__tilegx__" ifdefs) but with this change you can build a working kernel using the TILE-Gx toolchain and ARCH=tilegx. Most of these files are new, generally adding a foo_64.c file where previously there was just a foo_32.c file. The ARCH=tilegx directive redirects to arch/tile, not arch/tilegx, using the existing SRCARCH mechanism in the top-level Makefile. Changes to existing files: - <asm/bitops.h> and <asm/bitops_32.h> changed to factor the include of <asm-generic/bitops/non-atomic.h> in the common header. - <asm/compat.h> and arch/tile/kernel/compat.c changed to remove the "const" markers I had put on compat_sys_execve() when trying to match some recent similar changes to the non-compat execve. It turns out the compat version wasn't "upgraded" to use const. - <asm/opcode-tile_64.h> and <asm/opcode_constants_64.h> were previously included accidentally, with the 32-bit contents. Now they have the proper 64-bit contents. Finally, I had to hack the existing hacky drivers/input/input-compat.h to add yet another "#ifdef" for INPUT_COMPAT_TEST (same as x86_64). Signed-off-by: Chris Metcalf <cmetcalf@tilera.com> Acked-by: Dmitry Torokhov <dmitry.torokhov@gmail.com> [drivers/input]
145 lines
4 KiB
ArmAsm
145 lines
4 KiB
ArmAsm
/*
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* Copyright 2011 Tilera Corporation. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation, version 2.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
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* NON INFRINGEMENT. See the GNU General Public License for
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* more details.
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*/
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#include <linux/linkage.h>
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#include <asm/system.h>
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#include <asm/ptrace.h>
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#include <asm/asm-offsets.h>
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#include <arch/spr_def.h>
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#include <asm/processor.h>
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/*
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* See <asm/system.h>; called with prev and next task_struct pointers.
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* "prev" is returned in r0 for _switch_to and also for ret_from_fork.
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*
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* We want to save pc/sp in "prev", and get the new pc/sp from "next".
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* We also need to save all the callee-saved registers on the stack.
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*
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* Intel enables/disables access to the hardware cycle counter in
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* seccomp (secure computing) environments if necessary, based on
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* has_secure_computing(). We might want to do this at some point,
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* though it would require virtualizing the other SPRs under WORLD_ACCESS.
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*
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* Since we're saving to the stack, we omit sp from this list.
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* And for parallels with other architectures, we save lr separately,
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* in the thread_struct itself (as the "pc" field).
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*
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* This code also needs to be aligned with process.c copy_thread()
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*/
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#if CALLEE_SAVED_REGS_COUNT != 24
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# error Mismatch between <asm/system.h> and kernel/entry.S
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#endif
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#define FRAME_SIZE ((2 + CALLEE_SAVED_REGS_COUNT) * 8)
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#define SAVE_REG(r) { st r12, r; addi r12, r12, 8 }
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#define LOAD_REG(r) { ld r, r12; addi r12, r12, 8 }
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#define FOR_EACH_CALLEE_SAVED_REG(f) \
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f(r30); f(r31); \
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f(r32); f(r33); f(r34); f(r35); f(r36); f(r37); f(r38); f(r39); \
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f(r40); f(r41); f(r42); f(r43); f(r44); f(r45); f(r46); f(r47); \
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f(r48); f(r49); f(r50); f(r51); f(r52);
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STD_ENTRY_SECTION(__switch_to, .sched.text)
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{
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move r10, sp
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st sp, lr
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}
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{
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addli r11, sp, -FRAME_SIZE + 8
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addli sp, sp, -FRAME_SIZE
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}
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{
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st r11, r10
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addli r4, r1, TASK_STRUCT_THREAD_KSP_OFFSET
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}
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{
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ld r13, r4 /* Load new sp to a temp register early. */
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addi r12, sp, 16
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}
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FOR_EACH_CALLEE_SAVED_REG(SAVE_REG)
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addli r3, r0, TASK_STRUCT_THREAD_KSP_OFFSET
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{
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st r3, sp
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addli r3, r0, TASK_STRUCT_THREAD_PC_OFFSET
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}
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{
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st r3, lr
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addli r4, r1, TASK_STRUCT_THREAD_PC_OFFSET
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}
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{
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ld lr, r4
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addi r12, r13, 16
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}
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{
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/* Update sp and ksp0 simultaneously to avoid backtracer warnings. */
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move sp, r13
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mtspr SPR_SYSTEM_SAVE_K_0, r2
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}
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FOR_EACH_CALLEE_SAVED_REG(LOAD_REG)
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.L__switch_to_pc:
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{
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addli sp, sp, FRAME_SIZE
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jrp lr /* r0 is still valid here, so return it */
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}
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STD_ENDPROC(__switch_to)
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/* Return a suitable address for the backtracer for suspended threads */
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STD_ENTRY_SECTION(get_switch_to_pc, .sched.text)
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lnk r0
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{
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addli r0, r0, .L__switch_to_pc - .
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jrp lr
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}
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STD_ENDPROC(get_switch_to_pc)
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STD_ENTRY(get_pt_regs)
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.irp reg, r0, r1, r2, r3, r4, r5, r6, r7, \
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r8, r9, r10, r11, r12, r13, r14, r15, \
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r16, r17, r18, r19, r20, r21, r22, r23, \
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r24, r25, r26, r27, r28, r29, r30, r31, \
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r32, r33, r34, r35, r36, r37, r38, r39, \
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r40, r41, r42, r43, r44, r45, r46, r47, \
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r48, r49, r50, r51, r52, tp, sp
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{
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st r0, \reg
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addi r0, r0, 8
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}
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.endr
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{
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st r0, lr
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addi r0, r0, PTREGS_OFFSET_PC - PTREGS_OFFSET_LR
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}
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lnk r1
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{
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st r0, r1
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addi r0, r0, PTREGS_OFFSET_EX1 - PTREGS_OFFSET_PC
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}
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mfspr r1, INTERRUPT_CRITICAL_SECTION
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shli r1, r1, SPR_EX_CONTEXT_1_1__ICS_SHIFT
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ori r1, r1, KERNEL_PL
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{
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st r0, r1
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addi r0, r0, PTREGS_OFFSET_FAULTNUM - PTREGS_OFFSET_EX1
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}
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{
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st r0, zero /* clear faultnum */
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addi r0, r0, PTREGS_OFFSET_ORIG_R0 - PTREGS_OFFSET_FAULTNUM
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}
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{
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st r0, zero /* clear orig_r0 */
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addli r0, r0, -PTREGS_OFFSET_ORIG_R0 /* restore r0 to base */
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}
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jrp lr
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STD_ENDPROC(get_pt_regs)
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