06be2efaf4
This splits out a per-SoC IRQ range handling, so that the DB8500 and DB5500 SoC:s can reuse aproximately the same IRQ range with the largest span setting the roof. The same change is done for the boards, mutatis mutandis, with a new file for the U5500 board. Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
113 lines
4.6 KiB
C
113 lines
4.6 KiB
C
/*
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* Copyright (C) ST-Ericsson SA 2010
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*
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* Author: Rabin Vincent <rabin.vincent@stericsson.com>
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* License terms: GNU General Public License (GPL) version 2
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*/
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#ifndef __MACH_IRQS_DB5500_H
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#define __MACH_IRQS_DB5500_H
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#define IRQ_DB5500_MTU0 (IRQ_SHPI_START + 4)
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#define IRQ_DB5500_SPI2 (IRQ_SHPI_START + 6)
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#define IRQ_DB5500_PMU0 (IRQ_SHPI_START + 7)
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#define IRQ_DB5500_SPI0 (IRQ_SHPI_START + 8)
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#define IRQ_DB5500_RTT (IRQ_SHPI_START + 9)
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#define IRQ_DB5500_PKA (IRQ_SHPI_START + 10)
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#define IRQ_DB5500_UART0 (IRQ_SHPI_START + 11)
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#define IRQ_DB5500_I2C3 (IRQ_SHPI_START + 12)
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#define IRQ_DB5500_L2CC (IRQ_SHPI_START + 13)
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#define IRQ_DB5500_MSP0 (IRQ_SHPI_START + 14)
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#define IRQ_DB5500_CRYP1 (IRQ_SHPI_START + 15)
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#define IRQ_DB5500_PMU1 (IRQ_SHPI_START + 16)
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#define IRQ_DB5500_MTU1 (IRQ_SHPI_START + 17)
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#define IRQ_DB5500_RTC (IRQ_SHPI_START + 18)
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#define IRQ_DB5500_UART1 (IRQ_SHPI_START + 19)
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#define IRQ_DB5500_USB_WAKEUP (IRQ_SHPI_START + 20)
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#define IRQ_DB5500_I2C0 (IRQ_SHPI_START + 21)
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#define IRQ_DB5500_I2C1 (IRQ_SHPI_START + 22)
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#define IRQ_DB5500_USBOTG (IRQ_SHPI_START + 23)
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#define IRQ_DB5500_DMA_SECURE (IRQ_SHPI_START + 24)
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#define IRQ_DB5500_DMA (IRQ_SHPI_START + 25)
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#define IRQ_DB5500_UART2 (IRQ_SHPI_START + 26)
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#define IRQ_DB5500_ICN_PMU1 (IRQ_SHPI_START + 27)
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#define IRQ_DB5500_ICN_PMU2 (IRQ_SHPI_START + 28)
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#define IRQ_DB5500_UART3 (IRQ_SHPI_START + 29)
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#define IRQ_DB5500_SPI3 (IRQ_SHPI_START + 30)
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#define IRQ_DB5500_SDMMC4 (IRQ_SHPI_START + 31)
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#define IRQ_DB5500_IRRC (IRQ_SHPI_START + 33)
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#define IRQ_DB5500_IRDA_FT (IRQ_SHPI_START + 34)
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#define IRQ_DB5500_IRDA_SD (IRQ_SHPI_START + 35)
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#define IRQ_DB5500_IRDA_FI (IRQ_SHPI_START + 36)
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#define IRQ_DB5500_IRDA_FD (IRQ_SHPI_START + 37)
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#define IRQ_DB5500_FSMC_CODEREADY (IRQ_SHPI_START + 38)
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#define IRQ_DB5500_FSMC_NANDWAIT (IRQ_SHPI_START + 39)
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#define IRQ_DB5500_AB5500 (IRQ_SHPI_START + 40)
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#define IRQ_DB5500_SDMMC2 (IRQ_SHPI_START + 41)
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#define IRQ_DB5500_SIA (IRQ_SHPI_START + 42)
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#define IRQ_DB5500_SIA2 (IRQ_SHPI_START + 43)
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#define IRQ_DB5500_HVA (IRQ_SHPI_START + 44)
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#define IRQ_DB5500_HVA2 (IRQ_SHPI_START + 45)
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#define IRQ_DB5500_PRCMU0 (IRQ_SHPI_START + 46)
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#define IRQ_DB5500_PRCMU1 (IRQ_SHPI_START + 47)
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#define IRQ_DB5500_DISP (IRQ_SHPI_START + 48)
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#define IRQ_DB5500_SDMMC1 (IRQ_SHPI_START + 50)
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#define IRQ_DB5500_MSP1 (IRQ_SHPI_START + 52)
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#define IRQ_DB5500_KBD (IRQ_SHPI_START + 53)
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#define IRQ_DB5500_I2C2 (IRQ_SHPI_START + 55)
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#define IRQ_DB5500_B2R2 (IRQ_SHPI_START + 56)
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#define IRQ_DB5500_CRYP0 (IRQ_SHPI_START + 57)
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#define IRQ_DB5500_SDMMC3 (IRQ_SHPI_START + 59)
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#define IRQ_DB5500_SDMMC0 (IRQ_SHPI_START + 60)
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#define IRQ_DB5500_HSEM (IRQ_SHPI_START + 61)
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#define IRQ_DB5500_SBAG (IRQ_SHPI_START + 63)
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#define IRQ_DB5500_MODEM (IRQ_SHPI_START + 65)
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#define IRQ_DB5500_SPI1 (IRQ_SHPI_START + 96)
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#define IRQ_DB5500_MSP2 (IRQ_SHPI_START + 98)
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#define IRQ_DB5500_SRPTIMER (IRQ_SHPI_START + 101)
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#define IRQ_DB5500_CTI0 (IRQ_SHPI_START + 108)
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#define IRQ_DB5500_CTI1 (IRQ_SHPI_START + 109)
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#define IRQ_DB5500_ICN_ERR (IRQ_SHPI_START + 110)
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#define IRQ_DB5500_MALI_PPMMU (IRQ_SHPI_START + 112)
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#define IRQ_DB5500_MALI_PP (IRQ_SHPI_START + 113)
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#define IRQ_DB5500_MALI_GPMMU (IRQ_SHPI_START + 114)
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#define IRQ_DB5500_MALI_GP (IRQ_SHPI_START + 115)
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#define IRQ_DB5500_MALI (IRQ_SHPI_START + 116)
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#define IRQ_DB5500_PRCMU_SEM (IRQ_SHPI_START + 118)
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#define IRQ_DB5500_GPIO0 (IRQ_SHPI_START + 119)
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#define IRQ_DB5500_GPIO1 (IRQ_SHPI_START + 120)
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#define IRQ_DB5500_GPIO2 (IRQ_SHPI_START + 121)
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#define IRQ_DB5500_GPIO3 (IRQ_SHPI_START + 122)
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#define IRQ_DB5500_GPIO4 (IRQ_SHPI_START + 123)
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#define IRQ_DB5500_GPIO5 (IRQ_SHPI_START + 124)
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#define IRQ_DB5500_GPIO6 (IRQ_SHPI_START + 125)
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#define IRQ_DB5500_GPIO7 (IRQ_SHPI_START + 126)
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#ifdef CONFIG_UX500_SOC_DB5500
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/*
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* After the GPIO ones we reserve a range of IRQ:s in which virtual
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* IRQ:s representing modem IRQ:s can be allocated
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*/
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#define IRQ_MODEM_EVENTS_BASE IRQ_SOC_START
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#define IRQ_MODEM_EVENTS_NBR 72
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#define IRQ_MODEM_EVENTS_END (IRQ_MODEM_EVENTS_BASE + IRQ_MODEM_EVENTS_NBR)
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/* List of virtual IRQ:s that are allocated from the range above */
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#define MBOX_PAIR0_VIRT_IRQ (IRQ_MODEM_EVENTS_BASE + 43)
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#define MBOX_PAIR1_VIRT_IRQ (IRQ_MODEM_EVENTS_BASE + 45)
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#define MBOX_PAIR2_VIRT_IRQ (IRQ_MODEM_EVENTS_BASE + 41)
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/*
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* We may have several SoCs, but only one will run at a
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* time, so the one with most IRQs will bump this ahead,
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* but the IRQ_SOC_START remains the same for either SoC.
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*/
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#if IRQ_SOC_END < IRQ_MODEM_EVENTS_END
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#undef IRQ_SOC_END
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#define IRQ_SOC_END IRQ_MODEM_EVENTS_END
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#endif
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#endif /* CONFIG_UX500_SOC_DB5500 */
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#endif
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