a7726350e0
Here is a collection of cleanup patches. Among the pieces that stand out are:
- The deletion of h720x platforms
- Split of at91 non-dt platforms to their own Kconfig file to keep them separate
- General cleanups and refactoring of i.MX and MXS platforms
- Some restructuring of clock tables for OMAP
- Convertion of PMC driver for Tegra to dt-only
- Some renames of sunxi -> sun4i (Allwinner A10)
- ... plus a bunch of other stuff that I haven't mentioned
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQIcBAABAgAGBQJRggUqAAoJEIwa5zzehBx3HjEQAJwp7heRs/HwTDzmzcyHkRMV
usbaa9dHBuAZ0DzsWjLK99xEn8VWD9TvbeP6hN5gNhxko06UVza3o8PI2iV1ztMB
9K3u2+LS5on/5cOxnsU1va16h5hBZ0ZIgNx5NY+PZ5mBY6v1U3qTjljPP62iXp63
w+sdXeZDe/c5JvuoDRbY0OBR++3Jp8cQg7KbU78jWz3r5D2rC1zwhkf2audcRY6b
jIWTj9M8CHynh/D6OzKqDcOYorBHNSRj0YbiWS2nnMfm+0V8nya00EPRpCPRiBUb
sobSy1CI9Qxiih3bOf6QCfzCRzJ5hbtE0zlI8g3bqtEZ1yOsE949HrKapWHJJdIU
JNTXrxXORAnaRhbzvSPNpp/iJBSDQRsfEETgv5BuHg/4lzTQfzElySbcgb4EeoHr
7Zt8ZR2/Du+u76qIPqs19ES3Wx+nOEOfSDAgZmlfPvlwmlGDYvqAXoeJ006VXnhG
JacLuD/cFnJ1w00Bcl48ZXMIsVkoRqjvsCG5q688HGXMM1lU8DfgUpQY6OCWAbdu
kFnBinJZk+HbE8FGS8O0BoQ+oiC0YIr2XhATL66PGHq7bLHb5ycwvZ7mrfC0AN9j
M9hqTFednwfo9wF8vSj5nMsxXwP8/mky4ECGoFvLsMYDosunrNVnAHtTgDSE+ZgO
6kQJ1P8jBBXn2LyjF88W
=xCAx
-----END PGP SIGNATURE-----
Merge tag 'cleanup-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC cleanup from Olof Johansson:
"Here is a collection of cleanup patches. Among the pieces that stand
out are:
- The deletion of h720x platforms
- Split of at91 non-dt platforms to their own Kconfig file to keep
them separate
- General cleanups and refactoring of i.MX and MXS platforms
- Some restructuring of clock tables for OMAP
- Convertion of PMC driver for Tegra to dt-only
- Some renames of sunxi -> sun4i (Allwinner A10)
- ... plus a bunch of other stuff that I haven't mentioned"
* tag 'cleanup-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (119 commits)
ARM: i.MX: remove unused ARCH_* configs
ARM i.MX53: remove platform ahci support
ARM: sunxi: Rework the restart code
irqchip: sunxi: Rename sunxi to sun4i
irqchip: sunxi: Make use of the IRQCHIP_DECLARE macro
clocksource: sunxi: Rename sunxi to sun4i
clocksource: sunxi: make use of CLKSRC_OF
clocksource: sunxi: Cleanup the timer code
ARM: at91: remove trailing semicolon from macros
ARM: at91/setup: fix trivial typos
ARM: EXYNOS: remove "config EXYNOS_DEV_DRM"
ARM: EXYNOS: change the name of USB ohci header
ARM: SAMSUNG: Remove unnecessary code for dma
ARM: S3C24XX: Remove unused GPIO drive strength register definitions
ARM: OMAP4+: PM: Restore CPU power state to ON with clockdomain force wakeup method
ARM: S3C24XX: Removed unneeded dependency on CPU_S3C2412
ARM: S3C24XX: Removed unneeded dependency on CPU_S3C2410
ARM: S3C24XX: Removed unneeded dependency on ARCH_S3C24XX for boards
ARM: SAMSUNG: Fix typo "CONFIG_SAMSUNG_DEV_RTC"
ARM: S5P64X0: Fix typo "CONFIG_S5P64X0_SETUP_SDHCI"
...
149 lines
4.2 KiB
C
149 lines
4.2 KiB
C
/*
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* Copyright (c) 2010-2013, NVIDIA Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __MACH_TEGRA_SLEEP_H
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#define __MACH_TEGRA_SLEEP_H
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#include "iomap.h"
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#define TEGRA_ARM_PERIF_VIRT (TEGRA_ARM_PERIF_BASE - IO_CPU_PHYS \
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+ IO_CPU_VIRT)
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#define TEGRA_FLOW_CTRL_VIRT (TEGRA_FLOW_CTRL_BASE - IO_PPSB_PHYS \
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+ IO_PPSB_VIRT)
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#define TEGRA_CLK_RESET_VIRT (TEGRA_CLK_RESET_BASE - IO_PPSB_PHYS \
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+ IO_PPSB_VIRT)
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#define TEGRA_PMC_VIRT (TEGRA_PMC_BASE - IO_APB_PHYS + IO_APB_VIRT)
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/* PMC_SCRATCH37-39 and 41 are used for tegra_pen_lock and idle */
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#define PMC_SCRATCH37 0x130
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#define PMC_SCRATCH38 0x134
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#define PMC_SCRATCH39 0x138
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#define PMC_SCRATCH41 0x140
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#ifdef CONFIG_ARCH_TEGRA_2x_SOC
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#define CPU_RESETTABLE 2
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#define CPU_RESETTABLE_SOON 1
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#define CPU_NOT_RESETTABLE 0
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#endif
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#ifdef __ASSEMBLY__
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/* returns the offset of the flow controller halt register for a cpu */
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.macro cpu_to_halt_reg rd, rcpu
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cmp \rcpu, #0
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subne \rd, \rcpu, #1
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movne \rd, \rd, lsl #3
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addne \rd, \rd, #0x14
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moveq \rd, #0
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.endm
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/* returns the offset of the flow controller csr register for a cpu */
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.macro cpu_to_csr_reg rd, rcpu
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cmp \rcpu, #0
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subne \rd, \rcpu, #1
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movne \rd, \rd, lsl #3
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addne \rd, \rd, #0x18
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moveq \rd, #8
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.endm
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/* returns the ID of the current processor */
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.macro cpu_id, rd
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mrc p15, 0, \rd, c0, c0, 5
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and \rd, \rd, #0xF
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.endm
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/* loads a 32-bit value into a register without a data access */
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.macro mov32, reg, val
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movw \reg, #:lower16:\val
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movt \reg, #:upper16:\val
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.endm
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/* Macro to exit SMP coherency. */
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.macro exit_smp, tmp1, tmp2
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mrc p15, 0, \tmp1, c1, c0, 1 @ ACTLR
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bic \tmp1, \tmp1, #(1<<6) | (1<<0) @ clear ACTLR.SMP | ACTLR.FW
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mcr p15, 0, \tmp1, c1, c0, 1 @ ACTLR
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isb
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cpu_id \tmp1
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mov \tmp1, \tmp1, lsl #2
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mov \tmp2, #0xf
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mov \tmp2, \tmp2, lsl \tmp1
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mov32 \tmp1, TEGRA_ARM_PERIF_VIRT + 0xC
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str \tmp2, [\tmp1] @ invalidate SCU tags for CPU
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dsb
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.endm
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/* Macro to resume & re-enable L2 cache */
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#ifndef L2X0_CTRL_EN
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#define L2X0_CTRL_EN 1
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#endif
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#ifdef CONFIG_CACHE_L2X0
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.macro l2_cache_resume, tmp1, tmp2, tmp3, phys_l2x0_saved_regs
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W(adr) \tmp1, \phys_l2x0_saved_regs
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ldr \tmp1, [\tmp1]
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ldr \tmp2, [\tmp1, #L2X0_R_PHY_BASE]
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ldr \tmp3, [\tmp2, #L2X0_CTRL]
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tst \tmp3, #L2X0_CTRL_EN
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bne exit_l2_resume
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ldr \tmp3, [\tmp1, #L2X0_R_TAG_LATENCY]
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str \tmp3, [\tmp2, #L2X0_TAG_LATENCY_CTRL]
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ldr \tmp3, [\tmp1, #L2X0_R_DATA_LATENCY]
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str \tmp3, [\tmp2, #L2X0_DATA_LATENCY_CTRL]
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ldr \tmp3, [\tmp1, #L2X0_R_PREFETCH_CTRL]
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str \tmp3, [\tmp2, #L2X0_PREFETCH_CTRL]
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ldr \tmp3, [\tmp1, #L2X0_R_PWR_CTRL]
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str \tmp3, [\tmp2, #L2X0_POWER_CTRL]
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ldr \tmp3, [\tmp1, #L2X0_R_AUX_CTRL]
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str \tmp3, [\tmp2, #L2X0_AUX_CTRL]
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mov \tmp3, #L2X0_CTRL_EN
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str \tmp3, [\tmp2, #L2X0_CTRL]
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exit_l2_resume:
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.endm
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#else /* CONFIG_CACHE_L2X0 */
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.macro l2_cache_resume, tmp1, tmp2, tmp3, phys_l2x0_saved_regs
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.endm
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#endif /* CONFIG_CACHE_L2X0 */
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#else
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void tegra_pen_lock(void);
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void tegra_pen_unlock(void);
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void tegra_resume(void);
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int tegra_sleep_cpu_finish(unsigned long);
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void tegra_disable_clean_inv_dcache(void);
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#ifdef CONFIG_HOTPLUG_CPU
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void tegra20_hotplug_shutdown(void);
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void tegra30_hotplug_shutdown(void);
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void tegra_hotplug_init(void);
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#else
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static inline void tegra_hotplug_init(void) {}
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#endif
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void tegra20_cpu_shutdown(int cpu);
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int tegra20_cpu_is_resettable_soon(void);
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void tegra20_cpu_clear_resettable(void);
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#ifdef CONFIG_ARCH_TEGRA_2x_SOC
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void tegra20_cpu_set_resettable_soon(void);
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#else
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static inline void tegra20_cpu_set_resettable_soon(void) {}
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#endif
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int tegra20_sleep_cpu_secondary_finish(unsigned long);
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void tegra20_tear_down_cpu(void);
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int tegra30_sleep_cpu_secondary_finish(unsigned long);
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void tegra30_tear_down_cpu(void);
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#endif
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#endif
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