f5d7a13b18
This makes it more assembler friendly and allows it to be used in situation that need an unsigned long and not a pointer. Also the naming is clearer. IOMEM is introduced without IMX_ prefix as it is used this way in more than one ARM subarch and it might become globally available soon. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
96 lines
3.3 KiB
C
96 lines
3.3 KiB
C
#ifndef __MACH_MX25_H__
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#define __MACH_MX25_H__
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#define MX25_AIPS1_BASE_ADDR 0x43f00000
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#define MX25_AIPS1_BASE_ADDR_VIRT 0xfc000000
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#define MX25_AIPS1_SIZE SZ_1M
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#define MX25_AIPS2_BASE_ADDR 0x53f00000
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#define MX25_AIPS2_BASE_ADDR_VIRT 0xfc200000
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#define MX25_AIPS2_SIZE SZ_1M
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#define MX25_AVIC_BASE_ADDR 0x68000000
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#define MX25_AVIC_BASE_ADDR_VIRT 0xfc400000
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#define MX25_AVIC_SIZE SZ_1M
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#define MX25_I2C1_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x80000)
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#define MX25_I2C3_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x84000)
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#define MX25_CAN1_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x88000)
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#define MX25_CAN2_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x8c000)
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#define MX25_I2C2_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x98000)
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#define MX25_CSPI1_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0xa4000)
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#define MX25_IOMUXC_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0xac000)
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#define MX25_CRM_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x80000)
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#define MX25_GPT1_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x90000)
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#define MX25_WDOG_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xdc000)
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#define MX25_GPIO1_BASE_ADDR_VIRT (MX25_AIPS2_BASE_ADDR_VIRT + 0xcc000)
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#define MX25_GPIO2_BASE_ADDR_VIRT (MX25_AIPS2_BASE_ADDR_VIRT + 0xd0000)
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#define MX25_GPIO3_BASE_ADDR_VIRT (MX25_AIPS2_BASE_ADDR_VIRT + 0xa4000)
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#define MX25_GPIO4_BASE_ADDR_VIRT (MX25_AIPS2_BASE_ADDR_VIRT + 0x9c000)
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#define MX25_IO_P2V(x) ( \
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IMX_IO_P2V_MODULE(x, MX25_AIPS1) ?: \
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IMX_IO_P2V_MODULE(x, MX25_AIPS2) ?: \
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IMX_IO_P2V_MODULE(x, MX25_AVIC))
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#define MX25_IO_ADDRESS(x) IOMEM(MX25_IO_P2V(x))
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#define MX25_AIPS1_IO_ADDRESS(x) \
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(((x) - MX25_AIPS1_BASE_ADDR) + MX25_AIPS1_BASE_ADDR_VIRT)
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#define MX25_UART1_BASE_ADDR 0x43f90000
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#define MX25_UART2_BASE_ADDR 0x43f94000
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#define MX25_AUDMUX_BASE_ADDR 0x43fb0000
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#define MX25_UART3_BASE_ADDR 0x5000c000
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#define MX25_UART4_BASE_ADDR 0x50008000
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#define MX25_UART5_BASE_ADDR 0x5002c000
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#define MX25_CSPI3_BASE_ADDR 0x50004000
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#define MX25_CSPI2_BASE_ADDR 0x50010000
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#define MX25_FEC_BASE_ADDR 0x50038000
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#define MX25_SSI2_BASE_ADDR 0x50014000
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#define MX25_SSI1_BASE_ADDR 0x50034000
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#define MX25_NFC_BASE_ADDR 0xbb000000
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#define MX25_DRYICE_BASE_ADDR 0x53ffc000
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#define MX25_ESDHC1_BASE_ADDR 0x53fb4000
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#define MX25_ESDHC2_BASE_ADDR 0x53fb8000
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#define MX25_LCDC_BASE_ADDR 0x53fbc000
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#define MX25_KPP_BASE_ADDR 0x43fa8000
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#define MX25_SDMA_BASE_ADDR 0x53fd4000
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#define MX25_OTG_BASE_ADDR 0x53ff4000
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#define MX25_CSI_BASE_ADDR 0x53ff8000
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#define MX25_INT_CSPI3 0
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#define MX25_INT_I2C1 3
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#define MX25_INT_I2C2 4
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#define MX25_INT_UART4 5
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#define MX25_INT_ESDHC2 8
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#define MX25_INT_ESDHC1 9
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#define MX25_INT_I2C3 10
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#define MX25_INT_SSI2 11
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#define MX25_INT_SSI1 12
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#define MX25_INT_CSPI2 13
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#define MX25_INT_CSPI1 14
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#define MX25_INT_CSI 17
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#define MX25_INT_UART3 18
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#define MX25_INT_KPP 24
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#define MX25_INT_DRYICE 25
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#define MX25_INT_UART2 32
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#define MX25_INT_NFC 33
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#define MX25_INT_SDMA 34
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#define MX25_INT_LCDC 39
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#define MX25_INT_UART5 40
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#define MX25_INT_CAN1 43
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#define MX25_INT_CAN2 44
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#define MX25_INT_UART1 45
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#define MX25_INT_FEC 57
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#define MX25_DMA_REQ_SSI2_RX1 22
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#define MX25_DMA_REQ_SSI2_TX1 23
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#define MX25_DMA_REQ_SSI2_RX0 24
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#define MX25_DMA_REQ_SSI2_TX0 25
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#define MX25_DMA_REQ_SSI1_RX1 26
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#define MX25_DMA_REQ_SSI1_TX1 27
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#define MX25_DMA_REQ_SSI1_RX0 28
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#define MX25_DMA_REQ_SSI1_TX0 29
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#endif /* ifndef __MACH_MX25_H__ */
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