1bc2d3e38e
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7216/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
528 lines
16 KiB
C
528 lines
16 KiB
C
/*
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* Define the pci_ops for the PCIC on Toshiba TX4927, TX4938, etc.
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*
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* Based on linux/arch/mips/pci/ops-tx4938.c,
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* linux/arch/mips/pci/fixup-rbtx4938.c,
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* linux/arch/mips/txx9/rbtx4938/setup.c,
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* and RBTX49xx patch from CELF patch archive.
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*
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* 2003-2005 (c) MontaVista Software, Inc.
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* Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
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* (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/kernel.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <asm/txx9/pci.h>
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#include <asm/txx9/tx4927pcic.h>
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static struct {
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struct pci_controller *channel;
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struct tx4927_pcic_reg __iomem *pcicptr;
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} pcicptrs[2]; /* TX4938 has 2 pcic */
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static void __init set_tx4927_pcicptr(struct pci_controller *channel,
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struct tx4927_pcic_reg __iomem *pcicptr)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(pcicptrs); i++) {
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if (pcicptrs[i].channel == channel) {
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pcicptrs[i].pcicptr = pcicptr;
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return;
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}
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}
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for (i = 0; i < ARRAY_SIZE(pcicptrs); i++) {
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if (!pcicptrs[i].channel) {
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pcicptrs[i].channel = channel;
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pcicptrs[i].pcicptr = pcicptr;
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return;
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}
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}
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BUG();
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}
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struct tx4927_pcic_reg __iomem *get_tx4927_pcicptr(
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struct pci_controller *channel)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(pcicptrs); i++) {
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if (pcicptrs[i].channel == channel)
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return pcicptrs[i].pcicptr;
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}
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return NULL;
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}
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static int mkaddr(struct pci_bus *bus, unsigned int devfn, int where,
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struct tx4927_pcic_reg __iomem *pcicptr)
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{
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if (bus->parent == NULL &&
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devfn >= PCI_DEVFN(TX4927_PCIC_MAX_DEVNU, 0))
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return -1;
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__raw_writel(((bus->number & 0xff) << 0x10)
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| ((devfn & 0xff) << 0x08) | (where & 0xfc)
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| (bus->parent ? 1 : 0),
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&pcicptr->g2pcfgadrs);
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/* clear M_ABORT and Disable M_ABORT Int. */
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__raw_writel((__raw_readl(&pcicptr->pcistatus) & 0x0000ffff)
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| (PCI_STATUS_REC_MASTER_ABORT << 16),
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&pcicptr->pcistatus);
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return 0;
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}
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static int check_abort(struct tx4927_pcic_reg __iomem *pcicptr)
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{
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int code = PCIBIOS_SUCCESSFUL;
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/* wait write cycle completion before checking error status */
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while (__raw_readl(&pcicptr->pcicstatus) & TX4927_PCIC_PCICSTATUS_IWB)
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;
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if (__raw_readl(&pcicptr->pcistatus)
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& (PCI_STATUS_REC_MASTER_ABORT << 16)) {
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__raw_writel((__raw_readl(&pcicptr->pcistatus) & 0x0000ffff)
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| (PCI_STATUS_REC_MASTER_ABORT << 16),
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&pcicptr->pcistatus);
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/* flush write buffer */
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iob();
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code = PCIBIOS_DEVICE_NOT_FOUND;
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}
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return code;
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}
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static u8 icd_readb(int offset, struct tx4927_pcic_reg __iomem *pcicptr)
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{
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#ifdef __BIG_ENDIAN
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offset ^= 3;
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#endif
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return __raw_readb((void __iomem *)&pcicptr->g2pcfgdata + offset);
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}
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static u16 icd_readw(int offset, struct tx4927_pcic_reg __iomem *pcicptr)
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{
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#ifdef __BIG_ENDIAN
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offset ^= 2;
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#endif
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return __raw_readw((void __iomem *)&pcicptr->g2pcfgdata + offset);
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}
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static u32 icd_readl(struct tx4927_pcic_reg __iomem *pcicptr)
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{
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return __raw_readl(&pcicptr->g2pcfgdata);
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}
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static void icd_writeb(u8 val, int offset,
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struct tx4927_pcic_reg __iomem *pcicptr)
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{
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#ifdef __BIG_ENDIAN
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offset ^= 3;
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#endif
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__raw_writeb(val, (void __iomem *)&pcicptr->g2pcfgdata + offset);
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}
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static void icd_writew(u16 val, int offset,
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struct tx4927_pcic_reg __iomem *pcicptr)
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{
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#ifdef __BIG_ENDIAN
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offset ^= 2;
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#endif
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__raw_writew(val, (void __iomem *)&pcicptr->g2pcfgdata + offset);
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}
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static void icd_writel(u32 val, struct tx4927_pcic_reg __iomem *pcicptr)
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{
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__raw_writel(val, &pcicptr->g2pcfgdata);
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}
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static struct tx4927_pcic_reg __iomem *pci_bus_to_pcicptr(struct pci_bus *bus)
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{
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struct pci_controller *channel = bus->sysdata;
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return get_tx4927_pcicptr(channel);
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}
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static int tx4927_pci_config_read(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 *val)
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{
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struct tx4927_pcic_reg __iomem *pcicptr = pci_bus_to_pcicptr(bus);
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if (mkaddr(bus, devfn, where, pcicptr)) {
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*val = 0xffffffff;
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return -1;
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}
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switch (size) {
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case 1:
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*val = icd_readb(where & 3, pcicptr);
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break;
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case 2:
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*val = icd_readw(where & 3, pcicptr);
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break;
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default:
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*val = icd_readl(pcicptr);
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}
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return check_abort(pcicptr);
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}
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static int tx4927_pci_config_write(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 val)
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{
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struct tx4927_pcic_reg __iomem *pcicptr = pci_bus_to_pcicptr(bus);
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if (mkaddr(bus, devfn, where, pcicptr))
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return -1;
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switch (size) {
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case 1:
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icd_writeb(val, where & 3, pcicptr);
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break;
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case 2:
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icd_writew(val, where & 3, pcicptr);
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break;
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default:
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icd_writel(val, pcicptr);
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}
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return check_abort(pcicptr);
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}
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static struct pci_ops tx4927_pci_ops = {
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.read = tx4927_pci_config_read,
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.write = tx4927_pci_config_write,
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};
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static struct {
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u8 trdyto;
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u8 retryto;
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u16 gbwc;
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} tx4927_pci_opts = {
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.trdyto = 0,
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.retryto = 0,
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.gbwc = 0xfe0, /* 4064 GBUSCLK for CCFG.GTOT=0b11 */
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};
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char *tx4927_pcibios_setup(char *str)
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{
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if (!strncmp(str, "trdyto=", 7)) {
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u8 val = 0;
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if (kstrtou8(str + 7, 0, &val) == 0)
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tx4927_pci_opts.trdyto = val;
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return NULL;
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}
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if (!strncmp(str, "retryto=", 8)) {
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u8 val = 0;
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if (kstrtou8(str + 8, 0, &val) == 0)
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tx4927_pci_opts.retryto = val;
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return NULL;
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}
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if (!strncmp(str, "gbwc=", 5)) {
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u16 val;
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if (kstrtou16(str + 5, 0, &val) == 0)
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tx4927_pci_opts.gbwc = val;
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return NULL;
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}
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return str;
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}
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void __init tx4927_pcic_setup(struct tx4927_pcic_reg __iomem *pcicptr,
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struct pci_controller *channel, int extarb)
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{
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int i;
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unsigned long flags;
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set_tx4927_pcicptr(channel, pcicptr);
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if (!channel->pci_ops)
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printk(KERN_INFO
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"PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:%s\n",
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__raw_readl(&pcicptr->pciid) >> 16,
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__raw_readl(&pcicptr->pciid) & 0xffff,
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__raw_readl(&pcicptr->pciccrev) & 0xff,
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extarb ? "External" : "Internal");
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channel->pci_ops = &tx4927_pci_ops;
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local_irq_save(flags);
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/* Disable All Initiator Space */
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__raw_writel(__raw_readl(&pcicptr->pciccfg)
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& ~(TX4927_PCIC_PCICCFG_G2PMEN(0)
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| TX4927_PCIC_PCICCFG_G2PMEN(1)
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| TX4927_PCIC_PCICCFG_G2PMEN(2)
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| TX4927_PCIC_PCICCFG_G2PIOEN),
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&pcicptr->pciccfg);
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/* GB->PCI mappings */
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__raw_writel((channel->io_resource->end - channel->io_resource->start)
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>> 4,
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&pcicptr->g2piomask);
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____raw_writeq((channel->io_resource->start +
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channel->io_map_base - IO_BASE) |
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#ifdef __BIG_ENDIAN
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TX4927_PCIC_G2PIOGBASE_ECHG
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#else
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TX4927_PCIC_G2PIOGBASE_BSDIS
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#endif
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, &pcicptr->g2piogbase);
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____raw_writeq(channel->io_resource->start - channel->io_offset,
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&pcicptr->g2piopbase);
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for (i = 0; i < 3; i++) {
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__raw_writel(0, &pcicptr->g2pmmask[i]);
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____raw_writeq(0, &pcicptr->g2pmgbase[i]);
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____raw_writeq(0, &pcicptr->g2pmpbase[i]);
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}
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if (channel->mem_resource->end) {
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__raw_writel((channel->mem_resource->end
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- channel->mem_resource->start) >> 4,
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&pcicptr->g2pmmask[0]);
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____raw_writeq(channel->mem_resource->start |
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#ifdef __BIG_ENDIAN
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TX4927_PCIC_G2PMnGBASE_ECHG
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#else
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TX4927_PCIC_G2PMnGBASE_BSDIS
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#endif
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, &pcicptr->g2pmgbase[0]);
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____raw_writeq(channel->mem_resource->start -
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channel->mem_offset,
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&pcicptr->g2pmpbase[0]);
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}
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/* PCI->GB mappings (I/O 256B) */
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__raw_writel(0, &pcicptr->p2giopbase); /* 256B */
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____raw_writeq(0, &pcicptr->p2giogbase);
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/* PCI->GB mappings (MEM 512MB (64MB on R1.x)) */
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__raw_writel(0, &pcicptr->p2gm0plbase);
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__raw_writel(0, &pcicptr->p2gm0pubase);
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____raw_writeq(TX4927_PCIC_P2GMnGBASE_TMEMEN |
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#ifdef __BIG_ENDIAN
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TX4927_PCIC_P2GMnGBASE_TECHG
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#else
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TX4927_PCIC_P2GMnGBASE_TBSDIS
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#endif
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, &pcicptr->p2gmgbase[0]);
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/* PCI->GB mappings (MEM 16MB) */
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__raw_writel(0xffffffff, &pcicptr->p2gm1plbase);
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__raw_writel(0xffffffff, &pcicptr->p2gm1pubase);
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____raw_writeq(0, &pcicptr->p2gmgbase[1]);
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/* PCI->GB mappings (MEM 1MB) */
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__raw_writel(0xffffffff, &pcicptr->p2gm2pbase); /* 1MB */
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____raw_writeq(0, &pcicptr->p2gmgbase[2]);
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/* Clear all (including IRBER) except for GBWC */
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__raw_writel((tx4927_pci_opts.gbwc << 16)
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& TX4927_PCIC_PCICCFG_GBWC_MASK,
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&pcicptr->pciccfg);
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/* Enable Initiator Memory Space */
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if (channel->mem_resource->end)
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__raw_writel(__raw_readl(&pcicptr->pciccfg)
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| TX4927_PCIC_PCICCFG_G2PMEN(0),
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&pcicptr->pciccfg);
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/* Enable Initiator I/O Space */
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if (channel->io_resource->end)
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__raw_writel(__raw_readl(&pcicptr->pciccfg)
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| TX4927_PCIC_PCICCFG_G2PIOEN,
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&pcicptr->pciccfg);
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/* Enable Initiator Config */
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__raw_writel(__raw_readl(&pcicptr->pciccfg)
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| TX4927_PCIC_PCICCFG_ICAEN | TX4927_PCIC_PCICCFG_TCAR,
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&pcicptr->pciccfg);
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/* Do not use MEMMUL, MEMINF: YMFPCI card causes M_ABORT. */
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__raw_writel(0, &pcicptr->pcicfg1);
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__raw_writel((__raw_readl(&pcicptr->g2ptocnt) & ~0xffff)
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| (tx4927_pci_opts.trdyto & 0xff)
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| ((tx4927_pci_opts.retryto & 0xff) << 8),
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&pcicptr->g2ptocnt);
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/* Clear All Local Bus Status */
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__raw_writel(TX4927_PCIC_PCICSTATUS_ALL, &pcicptr->pcicstatus);
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/* Enable All Local Bus Interrupts */
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__raw_writel(TX4927_PCIC_PCICSTATUS_ALL, &pcicptr->pcicmask);
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/* Clear All Initiator Status */
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__raw_writel(TX4927_PCIC_G2PSTATUS_ALL, &pcicptr->g2pstatus);
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/* Enable All Initiator Interrupts */
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__raw_writel(TX4927_PCIC_G2PSTATUS_ALL, &pcicptr->g2pmask);
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/* Clear All PCI Status Error */
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__raw_writel((__raw_readl(&pcicptr->pcistatus) & 0x0000ffff)
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| (TX4927_PCIC_PCISTATUS_ALL << 16),
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&pcicptr->pcistatus);
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/* Enable All PCI Status Error Interrupts */
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__raw_writel(TX4927_PCIC_PCISTATUS_ALL, &pcicptr->pcimask);
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if (!extarb) {
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/* Reset Bus Arbiter */
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__raw_writel(TX4927_PCIC_PBACFG_RPBA, &pcicptr->pbacfg);
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__raw_writel(0, &pcicptr->pbabm);
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/* Enable Bus Arbiter */
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__raw_writel(TX4927_PCIC_PBACFG_PBAEN, &pcicptr->pbacfg);
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}
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__raw_writel(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY
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| PCI_COMMAND_PARITY | PCI_COMMAND_SERR,
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&pcicptr->pcistatus);
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local_irq_restore(flags);
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printk(KERN_DEBUG
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"PCI: COMMAND=%04x,PCIMASK=%04x,"
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"TRDYTO=%02x,RETRYTO=%02x,GBWC=%03x\n",
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__raw_readl(&pcicptr->pcistatus) & 0xffff,
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__raw_readl(&pcicptr->pcimask) & 0xffff,
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__raw_readl(&pcicptr->g2ptocnt) & 0xff,
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(__raw_readl(&pcicptr->g2ptocnt) & 0xff00) >> 8,
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(__raw_readl(&pcicptr->pciccfg) >> 16) & 0xfff);
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}
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static void tx4927_report_pcic_status1(struct tx4927_pcic_reg __iomem *pcicptr)
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{
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__u16 pcistatus = (__u16)(__raw_readl(&pcicptr->pcistatus) >> 16);
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__u32 g2pstatus = __raw_readl(&pcicptr->g2pstatus);
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__u32 pcicstatus = __raw_readl(&pcicptr->pcicstatus);
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static struct {
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__u32 flag;
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const char *str;
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} pcistat_tbl[] = {
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{ PCI_STATUS_DETECTED_PARITY, "DetectedParityError" },
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{ PCI_STATUS_SIG_SYSTEM_ERROR, "SignaledSystemError" },
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{ PCI_STATUS_REC_MASTER_ABORT, "ReceivedMasterAbort" },
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{ PCI_STATUS_REC_TARGET_ABORT, "ReceivedTargetAbort" },
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{ PCI_STATUS_SIG_TARGET_ABORT, "SignaledTargetAbort" },
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{ PCI_STATUS_PARITY, "MasterParityError" },
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}, g2pstat_tbl[] = {
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{ TX4927_PCIC_G2PSTATUS_TTOE, "TIOE" },
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{ TX4927_PCIC_G2PSTATUS_RTOE, "RTOE" },
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}, pcicstat_tbl[] = {
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{ TX4927_PCIC_PCICSTATUS_PME, "PME" },
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{ TX4927_PCIC_PCICSTATUS_TLB, "TLB" },
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{ TX4927_PCIC_PCICSTATUS_NIB, "NIB" },
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{ TX4927_PCIC_PCICSTATUS_ZIB, "ZIB" },
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{ TX4927_PCIC_PCICSTATUS_PERR, "PERR" },
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{ TX4927_PCIC_PCICSTATUS_SERR, "SERR" },
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{ TX4927_PCIC_PCICSTATUS_GBE, "GBE" },
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{ TX4927_PCIC_PCICSTATUS_IWB, "IWB" },
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};
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int i, cont;
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printk(KERN_ERR "");
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if (pcistatus & TX4927_PCIC_PCISTATUS_ALL) {
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printk(KERN_CONT "pcistat:%04x(", pcistatus);
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for (i = 0, cont = 0; i < ARRAY_SIZE(pcistat_tbl); i++)
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if (pcistatus & pcistat_tbl[i].flag)
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printk(KERN_CONT "%s%s",
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cont++ ? " " : "", pcistat_tbl[i].str);
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printk(KERN_CONT ") ");
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}
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if (g2pstatus & TX4927_PCIC_G2PSTATUS_ALL) {
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printk(KERN_CONT "g2pstatus:%08x(", g2pstatus);
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for (i = 0, cont = 0; i < ARRAY_SIZE(g2pstat_tbl); i++)
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if (g2pstatus & g2pstat_tbl[i].flag)
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printk(KERN_CONT "%s%s",
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cont++ ? " " : "", g2pstat_tbl[i].str);
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printk(KERN_CONT ") ");
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}
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if (pcicstatus & TX4927_PCIC_PCICSTATUS_ALL) {
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printk(KERN_CONT "pcicstatus:%08x(", pcicstatus);
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for (i = 0, cont = 0; i < ARRAY_SIZE(pcicstat_tbl); i++)
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if (pcicstatus & pcicstat_tbl[i].flag)
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printk(KERN_CONT "%s%s",
|
|
cont++ ? " " : "", pcicstat_tbl[i].str);
|
|
printk(KERN_CONT ")");
|
|
}
|
|
printk(KERN_CONT "\n");
|
|
}
|
|
|
|
void tx4927_report_pcic_status(void)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < ARRAY_SIZE(pcicptrs); i++) {
|
|
if (pcicptrs[i].pcicptr)
|
|
tx4927_report_pcic_status1(pcicptrs[i].pcicptr);
|
|
}
|
|
}
|
|
|
|
static void tx4927_dump_pcic_settings1(struct tx4927_pcic_reg __iomem *pcicptr)
|
|
{
|
|
int i;
|
|
__u32 __iomem *preg = (__u32 __iomem *)pcicptr;
|
|
|
|
printk(KERN_INFO "tx4927 pcic (0x%p) settings:", pcicptr);
|
|
for (i = 0; i < sizeof(struct tx4927_pcic_reg); i += 4, preg++) {
|
|
if (i % 32 == 0) {
|
|
printk(KERN_CONT "\n");
|
|
printk(KERN_INFO "%04x:", i);
|
|
}
|
|
/* skip registers with side-effects */
|
|
if (i == offsetof(struct tx4927_pcic_reg, g2pintack)
|
|
|| i == offsetof(struct tx4927_pcic_reg, g2pspc)
|
|
|| i == offsetof(struct tx4927_pcic_reg, g2pcfgadrs)
|
|
|| i == offsetof(struct tx4927_pcic_reg, g2pcfgdata)) {
|
|
printk(KERN_CONT " XXXXXXXX");
|
|
continue;
|
|
}
|
|
printk(KERN_CONT " %08x", __raw_readl(preg));
|
|
}
|
|
printk(KERN_CONT "\n");
|
|
}
|
|
|
|
void tx4927_dump_pcic_settings(void)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < ARRAY_SIZE(pcicptrs); i++) {
|
|
if (pcicptrs[i].pcicptr)
|
|
tx4927_dump_pcic_settings1(pcicptrs[i].pcicptr);
|
|
}
|
|
}
|
|
|
|
irqreturn_t tx4927_pcierr_interrupt(int irq, void *dev_id)
|
|
{
|
|
struct pt_regs *regs = get_irq_regs();
|
|
struct tx4927_pcic_reg __iomem *pcicptr =
|
|
(struct tx4927_pcic_reg __iomem *)(unsigned long)dev_id;
|
|
|
|
if (txx9_pci_err_action != TXX9_PCI_ERR_IGNORE) {
|
|
printk(KERN_WARNING "PCIERR interrupt at 0x%0*lx\n",
|
|
(int)(2 * sizeof(unsigned long)), regs->cp0_epc);
|
|
tx4927_report_pcic_status1(pcicptr);
|
|
}
|
|
if (txx9_pci_err_action != TXX9_PCI_ERR_PANIC) {
|
|
/* clear all pci errors */
|
|
__raw_writel((__raw_readl(&pcicptr->pcistatus) & 0x0000ffff)
|
|
| (TX4927_PCIC_PCISTATUS_ALL << 16),
|
|
&pcicptr->pcistatus);
|
|
__raw_writel(TX4927_PCIC_G2PSTATUS_ALL, &pcicptr->g2pstatus);
|
|
__raw_writel(TX4927_PCIC_PBASTATUS_ALL, &pcicptr->pbastatus);
|
|
__raw_writel(TX4927_PCIC_PCICSTATUS_ALL, &pcicptr->pcicstatus);
|
|
return IRQ_HANDLED;
|
|
}
|
|
console_verbose();
|
|
tx4927_dump_pcic_settings1(pcicptr);
|
|
panic("PCI error.");
|
|
}
|
|
|
|
#ifdef CONFIG_TOSHIBA_FPCIB0
|
|
static void tx4927_quirk_slc90e66_bridge(struct pci_dev *dev)
|
|
{
|
|
struct tx4927_pcic_reg __iomem *pcicptr = pci_bus_to_pcicptr(dev->bus);
|
|
|
|
if (!pcicptr)
|
|
return;
|
|
if (__raw_readl(&pcicptr->pbacfg) & TX4927_PCIC_PBACFG_PBAEN) {
|
|
/* Reset Bus Arbiter */
|
|
__raw_writel(TX4927_PCIC_PBACFG_RPBA, &pcicptr->pbacfg);
|
|
/*
|
|
* swap reqBP and reqXP (raise priority of SLC90E66).
|
|
* SLC90E66(PCI-ISA bridge) is connected to REQ2 on
|
|
* PCI Backplane board.
|
|
*/
|
|
__raw_writel(0x72543610, &pcicptr->pbareqport);
|
|
__raw_writel(0, &pcicptr->pbabm);
|
|
/* Use Fixed ParkMaster (required by SLC90E66) */
|
|
__raw_writel(TX4927_PCIC_PBACFG_FIXPA, &pcicptr->pbacfg);
|
|
/* Enable Bus Arbiter */
|
|
__raw_writel(TX4927_PCIC_PBACFG_FIXPA |
|
|
TX4927_PCIC_PBACFG_PBAEN,
|
|
&pcicptr->pbacfg);
|
|
printk(KERN_INFO "PCI: Use Fixed Park Master (REQPORT %08x)\n",
|
|
__raw_readl(&pcicptr->pbareqport));
|
|
}
|
|
}
|
|
#define PCI_DEVICE_ID_EFAR_SLC90E66_0 0x9460
|
|
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_0,
|
|
tx4927_quirk_slc90e66_bridge);
|
|
#endif
|