3297c2e6d7
This patch fixes on enable and ctrlbit of uclk1 and sclk_pwm. Signed-off-by: Jongpill Lee <boyko.lee@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
588 lines
14 KiB
C
588 lines
14 KiB
C
/* linux/arch/arm/mach-s5pv310/clock.c
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*
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* Copyright (c) 2010 Samsung Electronics Co., Ltd.
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* http://www.samsung.com/
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*
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* S5PV310 - Clock support
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <plat/cpu-freq.h>
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#include <plat/clock.h>
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#include <plat/cpu.h>
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#include <plat/pll.h>
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#include <plat/s5p-clock.h>
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#include <plat/clock-clksrc.h>
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#include <mach/map.h>
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#include <mach/regs-clock.h>
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static struct clk clk_sclk_hdmi27m = {
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.name = "sclk_hdmi27m",
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.id = -1,
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.rate = 27000000,
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};
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static int s5pv310_clksrc_mask_peril0_ctrl(struct clk *clk, int enable)
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{
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return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL0, clk, enable);
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}
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static int s5pv310_clk_ip_peril_ctrl(struct clk *clk, int enable)
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{
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return s5p_gatectrl(S5P_CLKGATE_IP_PERIL, clk, enable);
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}
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/* Core list of CMU_CPU side */
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static struct clksrc_clk clk_mout_apll = {
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.clk = {
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.name = "mout_apll",
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.id = -1,
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},
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.sources = &clk_src_apll,
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.reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 0, .size = 1 },
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};
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static struct clksrc_clk clk_sclk_apll = {
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.clk = {
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.name = "sclk_apll",
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.id = -1,
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.parent = &clk_mout_apll.clk,
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},
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.reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 24, .size = 3 },
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};
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static struct clksrc_clk clk_mout_epll = {
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.clk = {
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.name = "mout_epll",
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.id = -1,
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},
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.sources = &clk_src_epll,
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.reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 4, .size = 1 },
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};
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static struct clksrc_clk clk_mout_mpll = {
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.clk = {
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.name = "mout_mpll",
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.id = -1,
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},
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.sources = &clk_src_mpll,
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.reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 8, .size = 1 },
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};
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static struct clk *clkset_moutcore_list[] = {
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[0] = &clk_sclk_apll.clk,
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[1] = &clk_mout_mpll.clk,
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};
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static struct clksrc_sources clkset_moutcore = {
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.sources = clkset_moutcore_list,
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.nr_sources = ARRAY_SIZE(clkset_moutcore_list),
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};
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static struct clksrc_clk clk_moutcore = {
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.clk = {
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.name = "moutcore",
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.id = -1,
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},
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.sources = &clkset_moutcore,
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.reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 16, .size = 1 },
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};
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static struct clksrc_clk clk_coreclk = {
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.clk = {
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.name = "core_clk",
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.id = -1,
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.parent = &clk_moutcore.clk,
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},
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.reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 0, .size = 3 },
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};
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static struct clksrc_clk clk_armclk = {
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.clk = {
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.name = "armclk",
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.id = -1,
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.parent = &clk_coreclk.clk,
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},
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};
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static struct clksrc_clk clk_aclk_corem0 = {
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.clk = {
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.name = "aclk_corem0",
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.id = -1,
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.parent = &clk_coreclk.clk,
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},
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.reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
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};
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static struct clksrc_clk clk_aclk_cores = {
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.clk = {
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.name = "aclk_cores",
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.id = -1,
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.parent = &clk_coreclk.clk,
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},
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.reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
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};
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static struct clksrc_clk clk_aclk_corem1 = {
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.clk = {
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.name = "aclk_corem1",
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.id = -1,
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.parent = &clk_coreclk.clk,
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},
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.reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 8, .size = 3 },
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};
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static struct clksrc_clk clk_periphclk = {
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.clk = {
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.name = "periphclk",
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.id = -1,
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.parent = &clk_coreclk.clk,
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},
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.reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 12, .size = 3 },
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};
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static struct clksrc_clk clk_atclk = {
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.clk = {
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.name = "atclk",
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.id = -1,
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.parent = &clk_moutcore.clk,
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},
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.reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 16, .size = 3 },
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};
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static struct clksrc_clk clk_pclk_dbg = {
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.clk = {
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.name = "pclk_dbg",
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.id = -1,
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.parent = &clk_atclk.clk,
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},
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.reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 20, .size = 3 },
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};
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/* Core list of CMU_CORE side */
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static struct clk *clkset_corebus_list[] = {
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[0] = &clk_mout_mpll.clk,
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[1] = &clk_sclk_apll.clk,
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};
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static struct clksrc_sources clkset_mout_corebus = {
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.sources = clkset_corebus_list,
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.nr_sources = ARRAY_SIZE(clkset_corebus_list),
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};
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static struct clksrc_clk clk_mout_corebus = {
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.clk = {
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.name = "mout_corebus",
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.id = -1,
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},
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.sources = &clkset_mout_corebus,
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.reg_src = { .reg = S5P_CLKSRC_CORE, .shift = 4, .size = 1 },
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};
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static struct clksrc_clk clk_sclk_dmc = {
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.clk = {
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.name = "sclk_dmc",
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.id = -1,
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.parent = &clk_mout_corebus.clk,
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},
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.reg_div = { .reg = S5P_CLKDIV_CORE0, .shift = 12, .size = 3 },
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};
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static struct clksrc_clk clk_aclk_cored = {
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.clk = {
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.name = "aclk_cored",
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.id = -1,
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.parent = &clk_sclk_dmc.clk,
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},
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.reg_div = { .reg = S5P_CLKDIV_CORE0, .shift = 16, .size = 3 },
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};
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static struct clksrc_clk clk_aclk_corep = {
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.clk = {
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.name = "aclk_corep",
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.id = -1,
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.parent = &clk_aclk_cored.clk,
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},
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.reg_div = { .reg = S5P_CLKDIV_CORE0, .shift = 20, .size = 3 },
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};
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static struct clksrc_clk clk_aclk_acp = {
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.clk = {
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.name = "aclk_acp",
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.id = -1,
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.parent = &clk_mout_corebus.clk,
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},
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.reg_div = { .reg = S5P_CLKDIV_CORE0, .shift = 0, .size = 3 },
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};
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static struct clksrc_clk clk_pclk_acp = {
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.clk = {
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.name = "pclk_acp",
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.id = -1,
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.parent = &clk_aclk_acp.clk,
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},
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.reg_div = { .reg = S5P_CLKDIV_CORE0, .shift = 4, .size = 3 },
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};
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/* Core list of CMU_TOP side */
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static struct clk *clkset_aclk_top_list[] = {
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[0] = &clk_mout_mpll.clk,
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[1] = &clk_sclk_apll.clk,
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};
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static struct clksrc_sources clkset_aclk_200 = {
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.sources = clkset_aclk_top_list,
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.nr_sources = ARRAY_SIZE(clkset_aclk_top_list),
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};
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static struct clksrc_clk clk_aclk_200 = {
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.clk = {
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.name = "aclk_200",
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.id = -1,
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},
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.sources = &clkset_aclk_200,
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.reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 12, .size = 1 },
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.reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 0, .size = 3 },
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};
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static struct clksrc_sources clkset_aclk_100 = {
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.sources = clkset_aclk_top_list,
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.nr_sources = ARRAY_SIZE(clkset_aclk_top_list),
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};
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static struct clksrc_clk clk_aclk_100 = {
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.clk = {
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.name = "aclk_100",
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.id = -1,
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},
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.sources = &clkset_aclk_100,
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.reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 16, .size = 1 },
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.reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 4, .size = 4 },
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};
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static struct clksrc_sources clkset_aclk_160 = {
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.sources = clkset_aclk_top_list,
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.nr_sources = ARRAY_SIZE(clkset_aclk_top_list),
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};
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static struct clksrc_clk clk_aclk_160 = {
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.clk = {
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.name = "aclk_160",
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.id = -1,
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},
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.sources = &clkset_aclk_160,
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.reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 20, .size = 1 },
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.reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 8, .size = 3 },
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};
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static struct clksrc_sources clkset_aclk_133 = {
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.sources = clkset_aclk_top_list,
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.nr_sources = ARRAY_SIZE(clkset_aclk_top_list),
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};
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static struct clksrc_clk clk_aclk_133 = {
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.clk = {
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.name = "aclk_133",
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.id = -1,
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},
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.sources = &clkset_aclk_133,
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.reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 24, .size = 1 },
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.reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 12, .size = 3 },
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};
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static struct clk *clkset_vpllsrc_list[] = {
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[0] = &clk_fin_vpll,
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[1] = &clk_sclk_hdmi27m,
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};
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static struct clksrc_sources clkset_vpllsrc = {
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.sources = clkset_vpllsrc_list,
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.nr_sources = ARRAY_SIZE(clkset_vpllsrc_list),
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};
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static struct clksrc_clk clk_vpllsrc = {
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.clk = {
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.name = "vpll_src",
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.id = -1,
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},
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.sources = &clkset_vpllsrc,
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.reg_src = { .reg = S5P_CLKSRC_TOP1, .shift = 0, .size = 1 },
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};
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static struct clk *clkset_sclk_vpll_list[] = {
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[0] = &clk_vpllsrc.clk,
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[1] = &clk_fout_vpll,
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};
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static struct clksrc_sources clkset_sclk_vpll = {
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.sources = clkset_sclk_vpll_list,
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.nr_sources = ARRAY_SIZE(clkset_sclk_vpll_list),
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};
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static struct clksrc_clk clk_sclk_vpll = {
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.clk = {
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.name = "sclk_vpll",
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.id = -1,
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},
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.sources = &clkset_sclk_vpll,
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.reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 8, .size = 1 },
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};
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static struct clk init_clocks_disable[] = {
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{
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.name = "timers",
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.id = -1,
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.parent = &clk_aclk_100.clk,
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.enable = s5pv310_clk_ip_peril_ctrl,
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.ctrlbit = (1<<24),
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}
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};
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static struct clk init_clocks[] = {
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{
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.name = "uart",
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.id = 0,
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.enable = s5pv310_clk_ip_peril_ctrl,
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.ctrlbit = (1 << 0),
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}, {
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.name = "uart",
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.id = 1,
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.enable = s5pv310_clk_ip_peril_ctrl,
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.ctrlbit = (1 << 1),
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}, {
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.name = "uart",
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.id = 2,
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.enable = s5pv310_clk_ip_peril_ctrl,
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.ctrlbit = (1 << 2),
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}, {
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.name = "uart",
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.id = 3,
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.enable = s5pv310_clk_ip_peril_ctrl,
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.ctrlbit = (1 << 3),
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}, {
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.name = "uart",
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.id = 4,
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.enable = s5pv310_clk_ip_peril_ctrl,
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.ctrlbit = (1 << 4),
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}, {
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.name = "uart",
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.id = 5,
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.enable = s5pv310_clk_ip_peril_ctrl,
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.ctrlbit = (1 << 5),
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}
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};
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static struct clk *clkset_group_list[] = {
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[0] = &clk_ext_xtal_mux,
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[1] = &clk_xusbxti,
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[2] = &clk_sclk_hdmi27m,
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[6] = &clk_mout_mpll.clk,
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[7] = &clk_mout_epll.clk,
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[8] = &clk_sclk_vpll.clk,
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};
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static struct clksrc_sources clkset_group = {
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.sources = clkset_group_list,
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.nr_sources = ARRAY_SIZE(clkset_group_list),
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};
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static struct clksrc_clk clksrcs[] = {
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{
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.clk = {
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.name = "uclk1",
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.id = 0,
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.enable = s5pv310_clksrc_mask_peril0_ctrl,
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.ctrlbit = (1 << 0),
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},
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.sources = &clkset_group,
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.reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 0, .size = 4 },
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.reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 0, .size = 4 },
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}, {
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.clk = {
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.name = "uclk1",
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.id = 1,
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.enable = s5pv310_clksrc_mask_peril0_ctrl,
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.ctrlbit = (1 << 4),
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},
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.sources = &clkset_group,
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.reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 4, .size = 4 },
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.reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 4, .size = 4 },
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}, {
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.clk = {
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.name = "uclk1",
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.id = 2,
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.enable = s5pv310_clksrc_mask_peril0_ctrl,
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.ctrlbit = (1 << 8),
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},
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.sources = &clkset_group,
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.reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 8, .size = 4 },
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.reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 8, .size = 4 },
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}, {
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.clk = {
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.name = "uclk1",
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.id = 3,
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.enable = s5pv310_clksrc_mask_peril0_ctrl,
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.ctrlbit = (1 << 12),
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},
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.sources = &clkset_group,
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.reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 12, .size = 4 },
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.reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 12, .size = 4 },
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}, {
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.clk = {
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.name = "sclk_pwm",
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.id = -1,
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.enable = s5pv310_clksrc_mask_peril0_ctrl,
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.ctrlbit = (1 << 24),
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},
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.sources = &clkset_group,
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.reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 24, .size = 4 },
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.reg_div = { .reg = S5P_CLKDIV_PERIL3, .shift = 0, .size = 4 },
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},
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};
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/* Clock initialization code */
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static struct clksrc_clk *sysclks[] = {
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&clk_mout_apll,
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&clk_sclk_apll,
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&clk_mout_epll,
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&clk_mout_mpll,
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&clk_moutcore,
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&clk_coreclk,
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&clk_armclk,
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&clk_aclk_corem0,
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&clk_aclk_cores,
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&clk_aclk_corem1,
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&clk_periphclk,
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&clk_atclk,
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&clk_pclk_dbg,
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&clk_mout_corebus,
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&clk_sclk_dmc,
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&clk_aclk_cored,
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&clk_aclk_corep,
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&clk_aclk_acp,
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&clk_pclk_acp,
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&clk_vpllsrc,
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&clk_sclk_vpll,
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&clk_aclk_200,
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&clk_aclk_100,
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&clk_aclk_160,
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&clk_aclk_133,
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};
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|
|
|
void __init_or_cpufreq s5pv310_setup_clocks(void)
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|
{
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|
struct clk *xtal_clk;
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|
unsigned long apll;
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|
unsigned long mpll;
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|
unsigned long epll;
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|
unsigned long vpll;
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|
unsigned long vpllsrc;
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|
unsigned long xtal;
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|
unsigned long armclk;
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|
unsigned long aclk_corem0;
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|
unsigned long aclk_cores;
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|
unsigned long aclk_corem1;
|
|
unsigned long periphclk;
|
|
unsigned long sclk_dmc;
|
|
unsigned long aclk_cored;
|
|
unsigned long aclk_corep;
|
|
unsigned long aclk_acp;
|
|
unsigned long pclk_acp;
|
|
unsigned int ptr;
|
|
|
|
printk(KERN_DEBUG "%s: registering clocks\n", __func__);
|
|
|
|
xtal_clk = clk_get(NULL, "xtal");
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|
BUG_ON(IS_ERR(xtal_clk));
|
|
|
|
xtal = clk_get_rate(xtal_clk);
|
|
clk_put(xtal_clk);
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|
|
|
printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
|
|
|
|
apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON0), pll_4508);
|
|
mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON0), pll_4508);
|
|
epll = s5p_get_pll46xx(xtal, __raw_readl(S5P_EPLL_CON0),
|
|
__raw_readl(S5P_EPLL_CON1), pll_4600);
|
|
|
|
vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
|
|
vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(S5P_VPLL_CON0),
|
|
__raw_readl(S5P_VPLL_CON1), pll_4650);
|
|
|
|
clk_fout_apll.rate = apll;
|
|
clk_fout_mpll.rate = mpll;
|
|
clk_fout_epll.rate = epll;
|
|
clk_fout_vpll.rate = vpll;
|
|
|
|
printk(KERN_INFO "S5PV310: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
|
|
apll, mpll, epll, vpll);
|
|
|
|
armclk = clk_get_rate(&clk_armclk.clk);
|
|
aclk_corem0 = clk_get_rate(&clk_aclk_corem0.clk);
|
|
aclk_cores = clk_get_rate(&clk_aclk_cores.clk);
|
|
aclk_corem1 = clk_get_rate(&clk_aclk_corem1.clk);
|
|
periphclk = clk_get_rate(&clk_periphclk.clk);
|
|
sclk_dmc = clk_get_rate(&clk_sclk_dmc.clk);
|
|
aclk_cored = clk_get_rate(&clk_aclk_cored.clk);
|
|
aclk_corep = clk_get_rate(&clk_aclk_corep.clk);
|
|
aclk_acp = clk_get_rate(&clk_aclk_acp.clk);
|
|
pclk_acp = clk_get_rate(&clk_pclk_acp.clk);
|
|
|
|
printk(KERN_INFO "S5PV310: ARMCLK=%ld, COREM0=%ld, CORES=%ld\n"
|
|
"COREM1=%ld, PERI=%ld, DMC=%ld, CORED=%ld\n"
|
|
"COREP=%ld, ACLK_ACP=%ld, PCLK_ACP=%ld",
|
|
armclk, aclk_corem0, aclk_cores, aclk_corem1,
|
|
periphclk, sclk_dmc, aclk_cored, aclk_corep,
|
|
aclk_acp, pclk_acp);
|
|
|
|
clk_f.rate = armclk;
|
|
clk_h.rate = sclk_dmc;
|
|
clk_p.rate = periphclk;
|
|
|
|
for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
|
|
s3c_set_clksrc(&clksrcs[ptr], true);
|
|
}
|
|
|
|
static struct clk *clks[] __initdata = {
|
|
/* Nothing here yet */
|
|
};
|
|
|
|
void __init s5pv310_register_clocks(void)
|
|
{
|
|
struct clk *clkp;
|
|
int ret;
|
|
int ptr;
|
|
|
|
ret = s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
|
|
if (ret > 0)
|
|
printk(KERN_ERR "Failed to register %u clocks\n", ret);
|
|
|
|
for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
|
|
s3c_register_clksrc(sysclks[ptr], 1);
|
|
|
|
s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
|
|
s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
|
|
|
|
clkp = init_clocks_disable;
|
|
for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
|
|
ret = s3c24xx_register_clock(clkp);
|
|
if (ret < 0) {
|
|
printk(KERN_ERR "Failed to register clock %s (%d)\n",
|
|
clkp->name, ret);
|
|
}
|
|
(clkp->enable)(clkp, 0);
|
|
}
|
|
|
|
s3c_pwmclk_init();
|
|
}
|