ef077179a2
These three platforms didn't properly fill nr_chips in gen_nand
registration and therefore depended on gen_nand bug fixed by commit
81cbb0b177 ("mtd: gen_nand: fix support for
multiple chips")
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
280 lines
6.7 KiB
C
280 lines
6.7 KiB
C
/*
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* Copyright (C) 2009 Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/types.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/memory.h>
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#include <linux/platform_device.h>
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#include <linux/mtd/physmap.h>
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#include <linux/mtd/nand.h>
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#include <linux/gpio.h>
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#include <mach/hardware.h>
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#include <mach/irqs.h>
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#include <asm/mach-types.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/time.h>
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#include <asm/mach/map.h>
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#include <mach/common.h>
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#include <asm/page.h>
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#include <asm/setup.h>
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#include <mach/iomux-mx3.h>
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#include "devices-imx31.h"
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#include "devices.h"
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/* FPGA defines */
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#define QONG_FPGA_VERSION(major, minor, rev) \
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(((major & 0xF) << 12) | ((minor & 0xF) << 8) | (rev & 0xFF))
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#define QONG_FPGA_BASEADDR MX31_CS1_BASE_ADDR
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#define QONG_FPGA_PERIPH_SIZE (1 << 24)
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#define QONG_FPGA_CTRL_BASEADDR QONG_FPGA_BASEADDR
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#define QONG_FPGA_CTRL_SIZE 0x10
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/* FPGA control registers */
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#define QONG_FPGA_CTRL_VERSION 0x00
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#define QONG_DNET_ID 1
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#define QONG_DNET_BASEADDR \
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(QONG_FPGA_BASEADDR + QONG_DNET_ID * QONG_FPGA_PERIPH_SIZE)
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#define QONG_DNET_SIZE 0x00001000
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#define QONG_FPGA_IRQ IOMUX_TO_IRQ(MX31_PIN_DTR_DCE1)
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/*
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* This file contains the board-specific initialization routines.
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*/
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static const struct imxuart_platform_data uart_pdata __initconst = {
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.flags = IMXUART_HAVE_RTSCTS,
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};
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static int uart_pins[] = {
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MX31_PIN_CTS1__CTS1,
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MX31_PIN_RTS1__RTS1,
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MX31_PIN_TXD1__TXD1,
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MX31_PIN_RXD1__RXD1
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};
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static inline void __init mxc_init_imx_uart(void)
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{
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mxc_iomux_setup_multiple_pins(uart_pins, ARRAY_SIZE(uart_pins),
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"uart-0");
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imx31_add_imx_uart0(&uart_pdata);
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}
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static struct resource dnet_resources[] = {
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{
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.name = "dnet-memory",
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.start = QONG_DNET_BASEADDR,
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.end = QONG_DNET_BASEADDR + QONG_DNET_SIZE - 1,
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.flags = IORESOURCE_MEM,
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}, {
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.start = QONG_FPGA_IRQ,
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.end = QONG_FPGA_IRQ,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device dnet_device = {
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.name = "dnet",
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.id = -1,
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.num_resources = ARRAY_SIZE(dnet_resources),
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.resource = dnet_resources,
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};
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static int __init qong_init_dnet(void)
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{
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int ret;
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ret = platform_device_register(&dnet_device);
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return ret;
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}
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/* MTD NOR flash */
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static struct physmap_flash_data qong_flash_data = {
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.width = 2,
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};
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static struct resource qong_flash_resource = {
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.start = MX31_CS0_BASE_ADDR,
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.end = MX31_CS0_BASE_ADDR + SZ_128M - 1,
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.flags = IORESOURCE_MEM,
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};
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static struct platform_device qong_nor_mtd_device = {
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.name = "physmap-flash",
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.id = 0,
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.dev = {
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.platform_data = &qong_flash_data,
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},
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.resource = &qong_flash_resource,
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.num_resources = 1,
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};
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static void qong_init_nor_mtd(void)
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{
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(void)platform_device_register(&qong_nor_mtd_device);
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}
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/*
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* Hardware specific access to control-lines
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*/
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static void qong_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
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{
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struct nand_chip *nand_chip = mtd->priv;
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if (cmd == NAND_CMD_NONE)
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return;
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if (ctrl & NAND_CLE)
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writeb(cmd, nand_chip->IO_ADDR_W + (1 << 24));
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else
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writeb(cmd, nand_chip->IO_ADDR_W + (1 << 23));
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}
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/*
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* Read the Device Ready pin.
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*/
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static int qong_nand_device_ready(struct mtd_info *mtd)
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{
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return gpio_get_value(IOMUX_TO_GPIO(MX31_PIN_NFRB));
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}
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static void qong_nand_select_chip(struct mtd_info *mtd, int chip)
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{
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if (chip >= 0)
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gpio_set_value(IOMUX_TO_GPIO(MX31_PIN_NFCE_B), 0);
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else
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gpio_set_value(IOMUX_TO_GPIO(MX31_PIN_NFCE_B), 1);
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}
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static struct platform_nand_data qong_nand_data = {
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.chip = {
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.nr_chips = 1,
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.chip_delay = 20,
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.options = 0,
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},
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.ctrl = {
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.cmd_ctrl = qong_nand_cmd_ctrl,
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.dev_ready = qong_nand_device_ready,
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.select_chip = qong_nand_select_chip,
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}
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};
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static struct resource qong_nand_resource = {
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.start = MX31_CS3_BASE_ADDR,
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.end = MX31_CS3_BASE_ADDR + SZ_32M - 1,
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.flags = IORESOURCE_MEM,
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};
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static struct platform_device qong_nand_device = {
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.name = "gen_nand",
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.id = -1,
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.dev = {
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.platform_data = &qong_nand_data,
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},
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.num_resources = 1,
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.resource = &qong_nand_resource,
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};
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static void __init qong_init_nand_mtd(void)
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{
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/* init CS */
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mx31_setup_weimcs(3, 0x00004f00, 0x20013b31, 0x00020800);
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mxc_iomux_set_gpr(MUX_SDCTL_CSD1_SEL, true);
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/* enable pin */
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mxc_iomux_mode(IOMUX_MODE(MX31_PIN_NFCE_B, IOMUX_CONFIG_GPIO));
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if (!gpio_request(IOMUX_TO_GPIO(MX31_PIN_NFCE_B), "nand_enable"))
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gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_NFCE_B), 0);
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/* ready/busy pin */
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mxc_iomux_mode(IOMUX_MODE(MX31_PIN_NFRB, IOMUX_CONFIG_GPIO));
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if (!gpio_request(IOMUX_TO_GPIO(MX31_PIN_NFRB), "nand_rdy"))
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gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_NFRB));
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/* write protect pin */
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mxc_iomux_mode(IOMUX_MODE(MX31_PIN_NFWP_B, IOMUX_CONFIG_GPIO));
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if (!gpio_request(IOMUX_TO_GPIO(MX31_PIN_NFWP_B), "nand_wp"))
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gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_NFWP_B));
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platform_device_register(&qong_nand_device);
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}
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static void __init qong_init_fpga(void)
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{
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void __iomem *regs;
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u32 fpga_ver;
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regs = ioremap(QONG_FPGA_CTRL_BASEADDR, QONG_FPGA_CTRL_SIZE);
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if (!regs) {
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printk(KERN_ERR "%s: failed to map registers, aborting.\n",
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__func__);
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return;
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}
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fpga_ver = readl(regs + QONG_FPGA_CTRL_VERSION);
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iounmap(regs);
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printk(KERN_INFO "Qong FPGA version %d.%d.%d\n",
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(fpga_ver & 0xF000) >> 12,
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(fpga_ver & 0x0F00) >> 8, fpga_ver & 0x00FF);
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if (fpga_ver < QONG_FPGA_VERSION(0, 8, 7)) {
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printk(KERN_ERR "qong: Unexpected FPGA version, FPGA-based "
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"devices won't be registered!\n");
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return;
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}
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/* register FPGA-based devices */
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qong_init_nand_mtd();
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qong_init_dnet();
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}
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/*
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* Board specific initialization.
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*/
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static void __init mxc_board_init(void)
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{
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mxc_init_imx_uart();
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qong_init_nor_mtd();
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qong_init_fpga();
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}
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static void __init qong_timer_init(void)
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{
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mx31_clocks_init(26000000);
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}
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static struct sys_timer qong_timer = {
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.init = qong_timer_init,
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};
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/*
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* The following uses standard kernel macros defined in arch.h in order to
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* initialize __mach_desc_QONG data structure.
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*/
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MACHINE_START(QONG, "Dave/DENX QongEVB-LITE")
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/* Maintainer: DENX Software Engineering GmbH */
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.phys_io = MX31_AIPS1_BASE_ADDR,
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.io_pg_offst = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc,
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.boot_params = MX3x_PHYS_OFFSET + 0x100,
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.map_io = mx31_map_io,
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.init_irq = mx31_init_irq,
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.init_machine = mxc_board_init,
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.timer = &qong_timer,
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MACHINE_END
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