b89cd950cb
The PLLs can be from 3 different sources: osc1, osc2, or the f2s_ref_clk. Update the clock driver to be able to get the correct parent. Signed-off-by: Dinh Nguyen <dinguyen@altera.com> Cc: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Mike Turquette <mturquette@linaro.org> |
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clk-gate.c | ||
clk-periph.c | ||
clk-pll.c | ||
clk.c | ||
clk.h | ||
Makefile |