a09e64fbc0
This just leaves include/asm-arm/plat-* to deal with. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
125 lines
4.3 KiB
C
125 lines
4.3 KiB
C
/****************************************************************************/
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/*
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* arch/arm/mach-l7200/include/mach/pmu.h
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*
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* Registers and helper functions for the L7200 Link-Up Systems
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* Power Management Unit (PMU).
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*
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* (C) Copyright 2000, S A McConnell (samcconn@cotw.com)
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file COPYING in the main directory of this archive for
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* more details.
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*/
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/****************************************************************************/
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#define PMU_OFF 0x00050000 /* Offset from IO_START to the PMU registers. */
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/* IO_START and IO_BASE are defined in hardware.h */
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#define PMU_START (IO_START + PMU_OFF) /* Physical addr. of the PMU reg. */
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#define PMU_BASE (IO_BASE + PMU_OFF) /* Virtual addr. of the PMU reg. */
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/* Define the PMU registers for use by device drivers and the kernel. */
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typedef struct {
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unsigned int CURRENT; /* Current configuration register */
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unsigned int NEXT; /* Next configuration register */
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unsigned int reserved;
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unsigned int RUN; /* Run configuration register */
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unsigned int COMM; /* Configuration command register */
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unsigned int SDRAM; /* SDRAM configuration bypass register */
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} pmu_interface;
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#define PMU ((volatile pmu_interface *)(PMU_BASE))
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/* Macro's for reading the common register fields. */
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#define GET_TRANSOP(reg) ((reg >> 25) & 0x03) /* Bits 26-25 */
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#define GET_OSCEN(reg) ((reg >> 16) & 0x01)
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#define GET_OSCMUX(reg) ((reg >> 15) & 0x01)
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#define GET_PLLMUL(reg) ((reg >> 9) & 0x3f) /* Bits 14-9 */
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#define GET_PLLEN(reg) ((reg >> 8) & 0x01)
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#define GET_PLLMUX(reg) ((reg >> 7) & 0x01)
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#define GET_BCLK_DIV(reg) ((reg >> 3) & 0x03) /* Bits 4-3 */
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#define GET_SDRB_SEL(reg) ((reg >> 2) & 0x01)
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#define GET_SDRF_SEL(reg) ((reg >> 1) & 0x01)
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#define GET_FASTBUS(reg) (reg & 0x1)
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/* CFG_NEXT register */
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#define CFG_NEXT_CLOCKRECOVERY ((PMU->NEXT >> 18) & 0x7f) /* Bits 24-18 */
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#define CFG_NEXT_INTRET ((PMU->NEXT >> 17) & 0x01)
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#define CFG_NEXT_SDR_STOP ((PMU->NEXT >> 6) & 0x01)
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#define CFG_NEXT_SYSCLKEN ((PMU->NEXT >> 5) & 0x01)
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/* Useful field values that can be used to construct the
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* CFG_NEXT and CFG_RUN registers.
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*/
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#define TRANSOP_NOP 0<<25 /* NOCHANGE_NOSTALL */
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#define NOCHANGE_STALL 1<<25
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#define CHANGE_NOSTALL 2<<25
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#define CHANGE_STALL 3<<25
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#define INTRET 1<<17
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#define OSCEN 1<<16
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#define OSCMUX 1<<15
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/* PLL frequencies */
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#define PLLMUL_0 0<<9 /* 3.6864 MHz */
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#define PLLMUL_1 1<<9 /* ?????? MHz */
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#define PLLMUL_5 5<<9 /* 18.432 MHz */
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#define PLLMUL_10 10<<9 /* 36.864 MHz */
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#define PLLMUL_18 18<<9 /* ?????? MHz */
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#define PLLMUL_20 20<<9 /* 73.728 MHz */
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#define PLLMUL_32 32<<9 /* ?????? MHz */
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#define PLLMUL_35 35<<9 /* 129.024 MHz */
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#define PLLMUL_36 36<<9 /* ?????? MHz */
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#define PLLMUL_39 39<<9 /* ?????? MHz */
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#define PLLMUL_40 40<<9 /* 147.456 MHz */
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/* Clock recovery times */
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#define CRCLOCK_1 1<<18
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#define CRCLOCK_2 2<<18
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#define CRCLOCK_4 4<<18
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#define CRCLOCK_8 8<<18
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#define CRCLOCK_16 16<<18
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#define CRCLOCK_32 32<<18
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#define CRCLOCK_63 63<<18
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#define CRCLOCK_127 127<<18
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#define PLLEN 1<<8
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#define PLLMUX 1<<7
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#define SDR_STOP 1<<6
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#define SYSCLKEN 1<<5
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#define BCLK_DIV_4 2<<3
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#define BCLK_DIV_2 1<<3
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#define BCLK_DIV_1 0<<3
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#define SDRB_SEL 1<<2
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#define SDRF_SEL 1<<1
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#define FASTBUS 1<<0
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/* CFG_SDRAM */
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#define SDRREFFQ 1<<0 /* Only if SDRSTOPRQ is not set. */
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#define SDRREFACK 1<<1 /* Read-only */
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#define SDRSTOPRQ 1<<2 /* Only if SDRREFFQ is not set. */
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#define SDRSTOPACK 1<<3 /* Read-only */
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#define PICEN 1<<4 /* Enable Co-procesor */
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#define PICTEST 1<<5
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#define GET_SDRREFFQ ((PMU->SDRAM >> 0) & 0x01)
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#define GET_SDRREFACK ((PMU->SDRAM >> 1) & 0x01) /* Read-only */
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#define GET_SDRSTOPRQ ((PMU->SDRAM >> 2) & 0x01)
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#define GET_SDRSTOPACK ((PMU->SDRAM >> 3) & 0x01) /* Read-only */
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#define GET_PICEN ((PMU->SDRAM >> 4) & 0x01)
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#define GET_PICTEST ((PMU->SDRAM >> 5) & 0x01)
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