05af7bd2d7
MPIC U3/U4 MSI backend. Based on code from Segher, heavily hacked by me. This only deals with MSI on U3/U4 MPICs, aka. CPC 9x5. If we find a U3/U4 then we enable this backend, ie. take over the ppc_md MSI hooks. We might need more elaborate logic in future to decide which backend is enabled. We need our own irq_chip so that we can do MSI masking/unmasking on the device itself. We also need to mask explicitly on shutdown to make sure we don't get bitten by lazy-disable semantics. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
35 lines
1 KiB
Makefile
35 lines
1 KiB
Makefile
ifeq ($(CONFIG_PPC64),y)
|
|
EXTRA_CFLAGS += -mno-minimal-toc
|
|
endif
|
|
|
|
mpic-msi-obj-$(CONFIG_PCI_MSI) += mpic_msi.o mpic_u3msi.o
|
|
obj-$(CONFIG_MPIC) += mpic.o $(mpic-msi-obj-y)
|
|
|
|
obj-$(CONFIG_PPC_INDIRECT_PCI) += indirect_pci.o
|
|
obj-$(CONFIG_PPC_MPC106) += grackle.o
|
|
obj-$(CONFIG_PPC_DCR) += dcr.o
|
|
obj-$(CONFIG_PPC_DCR_NATIVE) += dcr-low.o
|
|
obj-$(CONFIG_PPC_PMI) += pmi.o
|
|
obj-$(CONFIG_U3_DART) += dart_iommu.o
|
|
obj-$(CONFIG_MMIO_NVRAM) += mmio_nvram.o
|
|
obj-$(CONFIG_FSL_SOC) += fsl_soc.o
|
|
obj-$(CONFIG_FSL_PCIE) += fsl_pcie.o
|
|
obj-$(CONFIG_TSI108_BRIDGE) += tsi108_pci.o tsi108_dev.o
|
|
obj-$(CONFIG_QUICC_ENGINE) += qe_lib/
|
|
|
|
# contains only the suspend handler for time
|
|
obj-$(CONFIG_PM) += timer.o
|
|
|
|
ifeq ($(CONFIG_PPC_MERGE),y)
|
|
obj-$(CONFIG_PPC_I8259) += i8259.o
|
|
obj-$(CONFIG_PPC_83xx) += ipic.o
|
|
obj-$(CONFIG_4xx) += uic.o
|
|
endif
|
|
|
|
# Temporary hack until we have migrated to asm-powerpc
|
|
ifeq ($(ARCH),powerpc)
|
|
obj-$(CONFIG_MTD) += rom.o
|
|
obj-$(CONFIG_CPM2) += cpm2_common.o cpm2_pic.o
|
|
obj-$(CONFIG_8xx) += mpc8xx_pic.o commproc.o
|
|
obj-$(CONFIG_UCODE_PATCH) += micropatch.o
|
|
endif
|