545 lines
16 KiB
C
545 lines
16 KiB
C
/*
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* PCI autoconfiguration library
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*
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* Author: Matt Porter <mporter@mvista.com>
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*
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* Copyright 2000, 2001 MontaVista Software Inc.
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* Copyright 2001 Bradley D. LaRonde <brad@ltc.com>
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* Copyright 2003 Paul Mundt <lethal@linux-sh.org>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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/*
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* Modified for MIPS by Jun Sun, jsun@mvista.com
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*
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* . Simplify the interface between pci_auto and the rest: a single function.
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* . Assign resources from low address to upper address.
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* . change most int to u32.
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*
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* Further modified to include it as mips generic code, ppopov@mvista.com.
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*
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* 2001-10-26 Bradley D. LaRonde <brad@ltc.com>
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* - Add a top_bus argument to the "early config" functions so that
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* they can set a fake parent bus pointer to convince the underlying
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* pci ops to use type 1 configuration for sub busses.
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* - Set bridge base and limit registers correctly.
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* - Align io and memory base properly before and after bridge setup.
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* - Don't fall through to pci_setup_bars for bridge.
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* - Reformat the debug output to look more like lspci's output.
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*
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* Cloned for SuperH by M. R. Brown, mrbrown@0xd6.org
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*
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* 2003-08-05 Paul Mundt <lethal@linux-sh.org>
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* - Don't update the BAR values on systems that already have valid addresses
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* and don't want these updated for whatever reason, by way of a new config
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* option check. However, we still read in the old BAR values so that they
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* can still be reported through the debug output.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/types.h>
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#include <linux/pci.h>
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#define DEBUG
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#ifdef DEBUG
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#define DBG(x...) printk(x)
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#else
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#define DBG(x...)
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#endif
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/*
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* These functions are used early on before PCI scanning is done
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* and all of the pci_dev and pci_bus structures have been created.
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*/
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static struct pci_dev *fake_pci_dev(struct pci_channel *hose,
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int top_bus, int busnr, int devfn)
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{
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static struct pci_dev dev;
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static struct pci_bus bus;
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dev.bus = &bus;
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dev.sysdata = hose;
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dev.devfn = devfn;
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bus.number = busnr;
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bus.ops = hose->pci_ops;
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if(busnr != top_bus)
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/* Fake a parent bus structure. */
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bus.parent = &bus;
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else
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bus.parent = NULL;
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return &dev;
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}
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#define EARLY_PCI_OP(rw, size, type) \
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int early_##rw##_config_##size(struct pci_channel *hose, \
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int top_bus, int bus, int devfn, int offset, type value) \
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{ \
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return pci_##rw##_config_##size( \
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fake_pci_dev(hose, top_bus, bus, devfn), \
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offset, value); \
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}
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EARLY_PCI_OP(read, byte, u8 *)
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EARLY_PCI_OP(read, word, u16 *)
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EARLY_PCI_OP(read, dword, u32 *)
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EARLY_PCI_OP(write, byte, u8)
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EARLY_PCI_OP(write, word, u16)
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EARLY_PCI_OP(write, dword, u32)
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static struct resource *io_resource_inuse;
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static struct resource *mem_resource_inuse;
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static u32 pciauto_lower_iospc;
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static u32 pciauto_upper_iospc;
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static u32 pciauto_lower_memspc;
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static u32 pciauto_upper_memspc;
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static void __init
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pciauto_setup_bars(struct pci_channel *hose,
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int top_bus,
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int current_bus,
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int pci_devfn,
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int bar_limit)
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{
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u32 bar_response, bar_size, bar_value;
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u32 bar, addr_mask, bar_nr = 0;
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u32 * upper_limit;
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u32 * lower_limit;
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int found_mem64 = 0;
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for (bar = PCI_BASE_ADDRESS_0; bar <= bar_limit; bar+=4) {
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u32 bar_addr;
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/* Read the old BAR value */
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early_read_config_dword(hose, top_bus,
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current_bus,
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pci_devfn,
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bar,
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&bar_addr);
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/* Tickle the BAR and get the response */
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early_write_config_dword(hose, top_bus,
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current_bus,
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pci_devfn,
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bar,
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0xffffffff);
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early_read_config_dword(hose, top_bus,
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current_bus,
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pci_devfn,
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bar,
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&bar_response);
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/*
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* Write the old BAR value back out, only update the BAR
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* if we implicitly want resources to be updated, which
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* is done by the generic code further down. -- PFM.
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*/
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early_write_config_dword(hose, top_bus,
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current_bus,
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pci_devfn,
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bar,
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bar_addr);
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/* If BAR is not implemented go to the next BAR */
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if (!bar_response)
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continue;
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/*
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* Workaround for a BAR that doesn't use its upper word,
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* like the ALi 1535D+ PCI DC-97 Controller Modem (M5457).
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* bdl <brad@ltc.com>
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*/
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if (!(bar_response & 0xffff0000))
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bar_response |= 0xffff0000;
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retry:
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/* Check the BAR type and set our address mask */
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if (bar_response & PCI_BASE_ADDRESS_SPACE) {
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addr_mask = PCI_BASE_ADDRESS_IO_MASK;
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upper_limit = &pciauto_upper_iospc;
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lower_limit = &pciauto_lower_iospc;
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DBG(" I/O");
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} else {
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if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
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PCI_BASE_ADDRESS_MEM_TYPE_64)
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found_mem64 = 1;
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addr_mask = PCI_BASE_ADDRESS_MEM_MASK;
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upper_limit = &pciauto_upper_memspc;
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lower_limit = &pciauto_lower_memspc;
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DBG(" Mem");
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}
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/* Calculate requested size */
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bar_size = ~(bar_response & addr_mask) + 1;
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/* Allocate a base address */
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bar_value = ((*lower_limit - 1) & ~(bar_size - 1)) + bar_size;
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if ((bar_value + bar_size) > *upper_limit) {
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if (bar_response & PCI_BASE_ADDRESS_SPACE) {
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if (io_resource_inuse->child) {
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io_resource_inuse =
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io_resource_inuse->child;
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pciauto_lower_iospc =
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io_resource_inuse->start;
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pciauto_upper_iospc =
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io_resource_inuse->end + 1;
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goto retry;
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}
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} else {
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if (mem_resource_inuse->child) {
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mem_resource_inuse =
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mem_resource_inuse->child;
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pciauto_lower_memspc =
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mem_resource_inuse->start;
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pciauto_upper_memspc =
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mem_resource_inuse->end + 1;
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goto retry;
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}
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}
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DBG(" unavailable -- skipping, value %x size %x\n",
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bar_value, bar_size);
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continue;
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}
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if (bar_value < *lower_limit || (bar_value + bar_size) >= *upper_limit) {
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DBG(" unavailable -- skipping, value %x size %x\n",
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bar_value, bar_size);
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continue;
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}
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#ifdef CONFIG_PCI_AUTO_UPDATE_RESOURCES
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/* Write it out and update our limit */
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early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
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bar, bar_value);
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#endif
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*lower_limit = bar_value + bar_size;
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/*
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* If we are a 64-bit decoder then increment to the
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* upper 32 bits of the bar and force it to locate
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* in the lower 4GB of memory.
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*/
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if (found_mem64) {
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bar += 4;
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early_write_config_dword(hose, top_bus,
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current_bus,
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pci_devfn,
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bar,
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0x00000000);
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}
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DBG(" at 0x%.8x [size=0x%x]\n", bar_value, bar_size);
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bar_nr++;
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}
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}
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static void __init
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pciauto_prescan_setup_bridge(struct pci_channel *hose,
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int top_bus,
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int current_bus,
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int pci_devfn,
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int sub_bus)
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{
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/* Configure bus number registers */
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early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
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PCI_PRIMARY_BUS, current_bus);
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early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
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PCI_SECONDARY_BUS, sub_bus + 1);
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early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
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PCI_SUBORDINATE_BUS, 0xff);
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/* Align memory and I/O to 1MB and 4KB boundaries. */
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pciauto_lower_memspc = (pciauto_lower_memspc + (0x100000 - 1))
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& ~(0x100000 - 1);
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pciauto_lower_iospc = (pciauto_lower_iospc + (0x1000 - 1))
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& ~(0x1000 - 1);
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/* Set base (lower limit) of address range behind bridge. */
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early_write_config_word(hose, top_bus, current_bus, pci_devfn,
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PCI_MEMORY_BASE, pciauto_lower_memspc >> 16);
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early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
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PCI_IO_BASE, (pciauto_lower_iospc & 0x0000f000) >> 8);
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early_write_config_word(hose, top_bus, current_bus, pci_devfn,
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PCI_IO_BASE_UPPER16, pciauto_lower_iospc >> 16);
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/* We don't support prefetchable memory for now, so disable */
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early_write_config_word(hose, top_bus, current_bus, pci_devfn,
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PCI_PREF_MEMORY_BASE, 0);
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early_write_config_word(hose, top_bus, current_bus, pci_devfn,
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PCI_PREF_MEMORY_LIMIT, 0);
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}
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static void __init
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pciauto_postscan_setup_bridge(struct pci_channel *hose,
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int top_bus,
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int current_bus,
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int pci_devfn,
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int sub_bus)
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{
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u32 temp;
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/*
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* [jsun] we always bump up baselines a little, so that if there
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* nothing behind P2P bridge, we don't wind up overlapping IO/MEM
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* spaces.
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*/
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pciauto_lower_memspc += 1;
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pciauto_lower_iospc += 1;
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/* Configure bus number registers */
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early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
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PCI_SUBORDINATE_BUS, sub_bus);
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/* Set upper limit of address range behind bridge. */
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early_write_config_word(hose, top_bus, current_bus, pci_devfn,
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PCI_MEMORY_LIMIT, pciauto_lower_memspc >> 16);
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early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
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PCI_IO_LIMIT, (pciauto_lower_iospc & 0x0000f000) >> 8);
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early_write_config_word(hose, top_bus, current_bus, pci_devfn,
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PCI_IO_LIMIT_UPPER16, pciauto_lower_iospc >> 16);
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/* Align memory and I/O to 1MB and 4KB boundaries. */
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pciauto_lower_memspc = (pciauto_lower_memspc + (0x100000 - 1))
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& ~(0x100000 - 1);
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pciauto_lower_iospc = (pciauto_lower_iospc + (0x1000 - 1))
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& ~(0x1000 - 1);
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/* Enable memory and I/O accesses, enable bus master */
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early_read_config_dword(hose, top_bus, current_bus, pci_devfn,
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PCI_COMMAND, &temp);
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early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
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PCI_COMMAND, temp | PCI_COMMAND_IO | PCI_COMMAND_MEMORY
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| PCI_COMMAND_MASTER);
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}
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static void __init
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pciauto_prescan_setup_cardbus_bridge(struct pci_channel *hose,
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int top_bus,
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int current_bus,
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int pci_devfn,
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int sub_bus)
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{
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/* Configure bus number registers */
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early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
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PCI_PRIMARY_BUS, current_bus);
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early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
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PCI_SECONDARY_BUS, sub_bus + 1);
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early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
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PCI_SUBORDINATE_BUS, 0xff);
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/* Align memory and I/O to 4KB and 4 byte boundaries. */
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pciauto_lower_memspc = (pciauto_lower_memspc + (0x1000 - 1))
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& ~(0x1000 - 1);
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pciauto_lower_iospc = (pciauto_lower_iospc + (0x4 - 1))
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& ~(0x4 - 1);
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early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
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PCI_CB_MEMORY_BASE_0, pciauto_lower_memspc);
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early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
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PCI_CB_IO_BASE_0, pciauto_lower_iospc);
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}
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static void __init
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pciauto_postscan_setup_cardbus_bridge(struct pci_channel *hose,
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int top_bus,
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int current_bus,
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int pci_devfn,
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int sub_bus)
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{
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u32 temp;
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/*
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* [jsun] we always bump up baselines a little, so that if there
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* nothing behind P2P bridge, we don't wind up overlapping IO/MEM
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* spaces.
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*/
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pciauto_lower_memspc += 1;
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pciauto_lower_iospc += 1;
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/*
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* Configure subordinate bus number. The PCI subsystem
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* bus scan will renumber buses (reserving three additional
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* for this PCI<->CardBus bridge for the case where a CardBus
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* adapter contains a P2P or CB2CB bridge.
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*/
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early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
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PCI_SUBORDINATE_BUS, sub_bus);
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/*
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* Reserve an additional 4MB for mem space and 16KB for
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* I/O space. This should cover any additional space
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* requirement of unusual CardBus devices with
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* additional bridges that can consume more address space.
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*
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* Although pcmcia-cs currently will reprogram bridge
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* windows, the goal is to add an option to leave them
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* alone and use the bridge window ranges as the regions
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* that are searched for free resources upon hot-insertion
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* of a device. This will allow a PCI<->CardBus bridge
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* configured by this routine to happily live behind a
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* P2P bridge in a system.
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*/
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/* Align memory and I/O to 4KB and 4 byte boundaries. */
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pciauto_lower_memspc = (pciauto_lower_memspc + (0x1000 - 1))
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& ~(0x1000 - 1);
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pciauto_lower_iospc = (pciauto_lower_iospc + (0x4 - 1))
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& ~(0x4 - 1);
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/* Set up memory and I/O filter limits, assume 32-bit I/O space */
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early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
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PCI_CB_MEMORY_LIMIT_0, pciauto_lower_memspc - 1);
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early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
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PCI_CB_IO_LIMIT_0, pciauto_lower_iospc - 1);
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/* Enable memory and I/O accesses, enable bus master */
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early_read_config_dword(hose, top_bus, current_bus, pci_devfn,
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PCI_COMMAND, &temp);
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early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
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PCI_COMMAND, temp | PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
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PCI_COMMAND_MASTER);
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}
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#define PCIAUTO_IDE_MODE_MASK 0x05
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static int __init
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pciauto_bus_scan(struct pci_channel *hose, int top_bus, int current_bus)
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{
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int sub_bus;
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u32 pci_devfn, pci_class, cmdstat, found_multi=0;
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unsigned short vid, did;
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unsigned char header_type;
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int devfn_start = 0;
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int devfn_stop = 0xff;
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sub_bus = current_bus;
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if (hose->first_devfn)
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devfn_start = hose->first_devfn;
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if (hose->last_devfn)
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devfn_stop = hose->last_devfn;
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for (pci_devfn=devfn_start; pci_devfn<devfn_stop; pci_devfn++) {
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if (PCI_FUNC(pci_devfn) && !found_multi)
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continue;
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early_read_config_word(hose, top_bus, current_bus, pci_devfn,
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PCI_VENDOR_ID, &vid);
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if (vid == 0xffff) continue;
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early_read_config_byte(hose, top_bus, current_bus, pci_devfn,
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PCI_HEADER_TYPE, &header_type);
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if (!PCI_FUNC(pci_devfn))
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found_multi = header_type & 0x80;
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early_read_config_word(hose, top_bus, current_bus, pci_devfn,
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PCI_DEVICE_ID, &did);
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early_read_config_dword(hose, top_bus, current_bus, pci_devfn,
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PCI_CLASS_REVISION, &pci_class);
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DBG("%.2x:%.2x.%x Class %.4x: %.4x:%.4x",
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current_bus, PCI_SLOT(pci_devfn), PCI_FUNC(pci_devfn),
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pci_class >> 16, vid, did);
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if (pci_class & 0xff)
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DBG(" (rev %.2x)", pci_class & 0xff);
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DBG("\n");
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if ((pci_class >> 16) == PCI_CLASS_BRIDGE_PCI) {
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DBG(" Bridge: primary=%.2x, secondary=%.2x\n",
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current_bus, sub_bus + 1);
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pciauto_prescan_setup_bridge(hose, top_bus, current_bus,
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pci_devfn, sub_bus);
|
|
DBG("Scanning sub bus %.2x, I/O 0x%.8x, Mem 0x%.8x\n",
|
|
sub_bus + 1,
|
|
pciauto_lower_iospc, pciauto_lower_memspc);
|
|
sub_bus = pciauto_bus_scan(hose, top_bus, sub_bus+1);
|
|
DBG("Back to bus %.2x\n", current_bus);
|
|
pciauto_postscan_setup_bridge(hose, top_bus, current_bus,
|
|
pci_devfn, sub_bus);
|
|
continue;
|
|
} else if ((pci_class >> 16) == PCI_CLASS_BRIDGE_CARDBUS) {
|
|
DBG(" CARDBUS Bridge: primary=%.2x, secondary=%.2x\n",
|
|
current_bus, sub_bus + 1);
|
|
DBG("PCI Autoconfig: Found CardBus bridge, device %d function %d\n", PCI_SLOT(pci_devfn), PCI_FUNC(pci_devfn));
|
|
/* Place CardBus Socket/ExCA registers */
|
|
pciauto_setup_bars(hose, top_bus, current_bus, pci_devfn, PCI_BASE_ADDRESS_0);
|
|
|
|
pciauto_prescan_setup_cardbus_bridge(hose, top_bus,
|
|
current_bus, pci_devfn, sub_bus);
|
|
|
|
DBG("Scanning sub bus %.2x, I/O 0x%.8x, Mem 0x%.8x\n",
|
|
sub_bus + 1,
|
|
pciauto_lower_iospc, pciauto_lower_memspc);
|
|
sub_bus = pciauto_bus_scan(hose, top_bus, sub_bus+1);
|
|
DBG("Back to bus %.2x, sub_bus is %x\n", current_bus, sub_bus);
|
|
pciauto_postscan_setup_cardbus_bridge(hose, top_bus,
|
|
current_bus, pci_devfn, sub_bus);
|
|
continue;
|
|
} else if ((pci_class >> 16) == PCI_CLASS_STORAGE_IDE) {
|
|
|
|
unsigned char prg_iface;
|
|
|
|
early_read_config_byte(hose, top_bus, current_bus,
|
|
pci_devfn, PCI_CLASS_PROG, &prg_iface);
|
|
if (!(prg_iface & PCIAUTO_IDE_MODE_MASK)) {
|
|
DBG("Skipping legacy mode IDE controller\n");
|
|
continue;
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Found a peripheral, enable some standard
|
|
* settings
|
|
*/
|
|
early_read_config_dword(hose, top_bus, current_bus, pci_devfn,
|
|
PCI_COMMAND, &cmdstat);
|
|
early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
|
|
PCI_COMMAND, cmdstat | PCI_COMMAND_IO |
|
|
PCI_COMMAND_MEMORY |
|
|
PCI_COMMAND_MASTER);
|
|
early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
|
|
PCI_LATENCY_TIMER, 0x80);
|
|
|
|
/* Allocate PCI I/O and/or memory space */
|
|
pciauto_setup_bars(hose, top_bus, current_bus, pci_devfn, PCI_BASE_ADDRESS_5);
|
|
}
|
|
return sub_bus;
|
|
}
|
|
|
|
int __init
|
|
pciauto_assign_resources(int busno, struct pci_channel *hose)
|
|
{
|
|
/* setup resource limits */
|
|
io_resource_inuse = hose->io_resource;
|
|
mem_resource_inuse = hose->mem_resource;
|
|
|
|
pciauto_lower_iospc = io_resource_inuse->start;
|
|
pciauto_upper_iospc = io_resource_inuse->end + 1;
|
|
pciauto_lower_memspc = mem_resource_inuse->start;
|
|
pciauto_upper_memspc = mem_resource_inuse->end + 1;
|
|
DBG("Autoconfig PCI channel 0x%p\n", hose);
|
|
DBG("Scanning bus %.2x, I/O 0x%.8x:0x%.8x, Mem 0x%.8x:0x%.8x\n",
|
|
busno, pciauto_lower_iospc, pciauto_upper_iospc,
|
|
pciauto_lower_memspc, pciauto_upper_memspc);
|
|
|
|
return pciauto_bus_scan(hose, busno, busno);
|
|
}
|