3c3e489831
This patch adds driver support for the I2C read-modify-write service in the U8500 PRCMU firmware. Signed-off-by: Mattias Nilsson <mattias.i.nilsson@stericsson.com> Reviewed-by: Jonas ABERG <jonas.aberg@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
915 lines
19 KiB
C
915 lines
19 KiB
C
/*
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* Copyright (C) ST Ericsson SA 2011
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*
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* License Terms: GNU General Public License v2
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*
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* STE Ux500 PRCMU API
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*/
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#ifndef __MACH_PRCMU_H
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#define __MACH_PRCMU_H
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#include <linux/interrupt.h>
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#include <linux/notifier.h>
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#include <linux/err.h>
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/* PRCMU Wakeup defines */
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enum prcmu_wakeup_index {
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PRCMU_WAKEUP_INDEX_RTC,
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PRCMU_WAKEUP_INDEX_RTT0,
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PRCMU_WAKEUP_INDEX_RTT1,
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PRCMU_WAKEUP_INDEX_HSI0,
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PRCMU_WAKEUP_INDEX_HSI1,
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PRCMU_WAKEUP_INDEX_USB,
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PRCMU_WAKEUP_INDEX_ABB,
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PRCMU_WAKEUP_INDEX_ABB_FIFO,
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PRCMU_WAKEUP_INDEX_ARM,
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PRCMU_WAKEUP_INDEX_CD_IRQ,
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NUM_PRCMU_WAKEUP_INDICES
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};
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#define PRCMU_WAKEUP(_name) (BIT(PRCMU_WAKEUP_INDEX_##_name))
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/* EPOD (power domain) IDs */
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/*
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* DB8500 EPODs
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* - EPOD_ID_SVAMMDSP: power domain for SVA MMDSP
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* - EPOD_ID_SVAPIPE: power domain for SVA pipe
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* - EPOD_ID_SIAMMDSP: power domain for SIA MMDSP
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* - EPOD_ID_SIAPIPE: power domain for SIA pipe
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* - EPOD_ID_SGA: power domain for SGA
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* - EPOD_ID_B2R2_MCDE: power domain for B2R2 and MCDE
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* - EPOD_ID_ESRAM12: power domain for ESRAM 1 and 2
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* - EPOD_ID_ESRAM34: power domain for ESRAM 3 and 4
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* - NUM_EPOD_ID: number of power domains
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*
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* TODO: These should be prefixed.
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*/
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#define EPOD_ID_SVAMMDSP 0
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#define EPOD_ID_SVAPIPE 1
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#define EPOD_ID_SIAMMDSP 2
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#define EPOD_ID_SIAPIPE 3
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#define EPOD_ID_SGA 4
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#define EPOD_ID_B2R2_MCDE 5
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#define EPOD_ID_ESRAM12 6
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#define EPOD_ID_ESRAM34 7
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#define NUM_EPOD_ID 8
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/*
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* DB5500 EPODs
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*/
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#define DB5500_EPOD_ID_BASE 0x0100
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#define DB5500_EPOD_ID_SGA (DB5500_EPOD_ID_BASE + 0)
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#define DB5500_EPOD_ID_HVA (DB5500_EPOD_ID_BASE + 1)
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#define DB5500_EPOD_ID_SIA (DB5500_EPOD_ID_BASE + 2)
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#define DB5500_EPOD_ID_DISP (DB5500_EPOD_ID_BASE + 3)
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#define DB5500_EPOD_ID_ESRAM12 (DB5500_EPOD_ID_BASE + 6)
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#define DB5500_NUM_EPOD_ID 7
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/*
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* state definition for EPOD (power domain)
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* - EPOD_STATE_NO_CHANGE: The EPOD should remain unchanged
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* - EPOD_STATE_OFF: The EPOD is switched off
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* - EPOD_STATE_RAMRET: The EPOD is switched off with its internal RAM in
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* retention
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* - EPOD_STATE_ON_CLK_OFF: The EPOD is switched on, clock is still off
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* - EPOD_STATE_ON: Same as above, but with clock enabled
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*/
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#define EPOD_STATE_NO_CHANGE 0x00
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#define EPOD_STATE_OFF 0x01
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#define EPOD_STATE_RAMRET 0x02
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#define EPOD_STATE_ON_CLK_OFF 0x03
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#define EPOD_STATE_ON 0x04
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/* DB5500 CLKOUT IDs */
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enum {
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DB5500_CLKOUT0 = 0,
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DB5500_CLKOUT1,
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};
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/* DB5500 CLKOUTx sources */
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enum {
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DB5500_CLKOUT_REF_CLK_SEL0,
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DB5500_CLKOUT_RTC_CLK0_SEL0,
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DB5500_CLKOUT_ULP_CLK_SEL0,
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DB5500_CLKOUT_STATIC0,
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DB5500_CLKOUT_REFCLK,
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DB5500_CLKOUT_ULPCLK,
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DB5500_CLKOUT_ARMCLK,
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DB5500_CLKOUT_SYSACC0CLK,
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DB5500_CLKOUT_SOC0PLLCLK,
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DB5500_CLKOUT_SOC1PLLCLK,
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DB5500_CLKOUT_DDRPLLCLK,
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DB5500_CLKOUT_TVCLK,
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DB5500_CLKOUT_IRDACLK,
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};
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/*
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* CLKOUT sources
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*/
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#define PRCMU_CLKSRC_CLK38M 0x00
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#define PRCMU_CLKSRC_ACLK 0x01
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#define PRCMU_CLKSRC_SYSCLK 0x02
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#define PRCMU_CLKSRC_LCDCLK 0x03
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#define PRCMU_CLKSRC_SDMMCCLK 0x04
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#define PRCMU_CLKSRC_TVCLK 0x05
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#define PRCMU_CLKSRC_TIMCLK 0x06
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#define PRCMU_CLKSRC_CLK009 0x07
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/* These are only valid for CLKOUT1: */
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#define PRCMU_CLKSRC_SIAMMDSPCLK 0x40
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#define PRCMU_CLKSRC_I2CCLK 0x41
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#define PRCMU_CLKSRC_MSP02CLK 0x42
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#define PRCMU_CLKSRC_ARMPLL_OBSCLK 0x43
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#define PRCMU_CLKSRC_HSIRXCLK 0x44
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#define PRCMU_CLKSRC_HSITXCLK 0x45
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#define PRCMU_CLKSRC_ARMCLKFIX 0x46
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#define PRCMU_CLKSRC_HDMICLK 0x47
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/*
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* Clock identifiers.
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*/
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enum prcmu_clock {
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PRCMU_SGACLK,
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PRCMU_UARTCLK,
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PRCMU_MSP02CLK,
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PRCMU_MSP1CLK,
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PRCMU_I2CCLK,
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PRCMU_SDMMCCLK,
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PRCMU_SPARE1CLK,
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PRCMU_SLIMCLK,
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PRCMU_PER1CLK,
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PRCMU_PER2CLK,
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PRCMU_PER3CLK,
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PRCMU_PER5CLK,
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PRCMU_PER6CLK,
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PRCMU_PER7CLK,
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PRCMU_LCDCLK,
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PRCMU_BMLCLK,
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PRCMU_HSITXCLK,
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PRCMU_HSIRXCLK,
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PRCMU_HDMICLK,
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PRCMU_APEATCLK,
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PRCMU_APETRACECLK,
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PRCMU_MCDECLK,
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PRCMU_IPI2CCLK,
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PRCMU_DSIALTCLK,
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PRCMU_DMACLK,
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PRCMU_B2R2CLK,
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PRCMU_TVCLK,
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PRCMU_SSPCLK,
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PRCMU_RNGCLK,
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PRCMU_UICCCLK,
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PRCMU_PWMCLK,
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PRCMU_IRDACLK,
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PRCMU_IRRCCLK,
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PRCMU_SIACLK,
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PRCMU_SVACLK,
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PRCMU_ACLK,
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PRCMU_NUM_REG_CLOCKS,
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PRCMU_SYSCLK = PRCMU_NUM_REG_CLOCKS,
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PRCMU_CDCLK,
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PRCMU_TIMCLK,
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PRCMU_PLLSOC0,
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PRCMU_PLLSOC1,
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PRCMU_PLLDDR,
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PRCMU_PLLDSI,
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PRCMU_DSI0CLK,
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PRCMU_DSI1CLK,
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PRCMU_DSI0ESCCLK,
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PRCMU_DSI1ESCCLK,
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PRCMU_DSI2ESCCLK,
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};
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/**
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* enum ape_opp - APE OPP states definition
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* @APE_OPP_INIT:
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* @APE_NO_CHANGE: The APE operating point is unchanged
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* @APE_100_OPP: The new APE operating point is ape100opp
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* @APE_50_OPP: 50%
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* @APE_50_PARTLY_25_OPP: 50%, except some clocks at 25%.
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*/
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enum ape_opp {
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APE_OPP_INIT = 0x00,
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APE_NO_CHANGE = 0x01,
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APE_100_OPP = 0x02,
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APE_50_OPP = 0x03,
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APE_50_PARTLY_25_OPP = 0xFF,
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};
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/**
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* enum arm_opp - ARM OPP states definition
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* @ARM_OPP_INIT:
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* @ARM_NO_CHANGE: The ARM operating point is unchanged
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* @ARM_100_OPP: The new ARM operating point is arm100opp
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* @ARM_50_OPP: The new ARM operating point is arm50opp
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* @ARM_MAX_OPP: Operating point is "max" (more than 100)
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* @ARM_MAX_FREQ100OPP: Set max opp if available, else 100
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* @ARM_EXTCLK: The new ARM operating point is armExtClk
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*/
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enum arm_opp {
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ARM_OPP_INIT = 0x00,
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ARM_NO_CHANGE = 0x01,
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ARM_100_OPP = 0x02,
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ARM_50_OPP = 0x03,
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ARM_MAX_OPP = 0x04,
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ARM_MAX_FREQ100OPP = 0x05,
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ARM_EXTCLK = 0x07
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};
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/**
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* enum ddr_opp - DDR OPP states definition
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* @DDR_100_OPP: The new DDR operating point is ddr100opp
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* @DDR_50_OPP: The new DDR operating point is ddr50opp
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* @DDR_25_OPP: The new DDR operating point is ddr25opp
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*/
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enum ddr_opp {
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DDR_100_OPP = 0x00,
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DDR_50_OPP = 0x01,
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DDR_25_OPP = 0x02,
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};
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/*
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* Definitions for controlling ESRAM0 in deep sleep.
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*/
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#define ESRAM0_DEEP_SLEEP_STATE_OFF 1
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#define ESRAM0_DEEP_SLEEP_STATE_RET 2
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/**
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* enum ddr_pwrst - DDR power states definition
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* @DDR_PWR_STATE_UNCHANGED: SDRAM and DDR controller state is unchanged
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* @DDR_PWR_STATE_ON:
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* @DDR_PWR_STATE_OFFLOWLAT:
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* @DDR_PWR_STATE_OFFHIGHLAT:
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*/
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enum ddr_pwrst {
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DDR_PWR_STATE_UNCHANGED = 0x00,
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DDR_PWR_STATE_ON = 0x01,
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DDR_PWR_STATE_OFFLOWLAT = 0x02,
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DDR_PWR_STATE_OFFHIGHLAT = 0x03
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};
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#include <linux/mfd/db8500-prcmu.h>
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#include <linux/mfd/db5500-prcmu.h>
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#if defined(CONFIG_UX500_SOC_DB8500) || defined(CONFIG_UX500_SOC_DB5500)
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#include <mach/id.h>
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static inline void __init prcmu_early_init(void)
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{
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if (cpu_is_u5500())
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return db5500_prcmu_early_init();
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else
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return db8500_prcmu_early_init();
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}
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static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk,
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bool keep_ap_pll)
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{
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if (cpu_is_u5500())
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return db5500_prcmu_set_power_state(state, keep_ulp_clk,
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keep_ap_pll);
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else
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return db8500_prcmu_set_power_state(state, keep_ulp_clk,
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keep_ap_pll);
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}
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static inline u8 prcmu_get_power_state_result(void)
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{
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if (cpu_is_u5500())
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return -EINVAL;
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else
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return db8500_prcmu_get_power_state_result();
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}
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static inline int prcmu_gic_decouple(void)
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{
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if (cpu_is_u5500())
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return -EINVAL;
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else
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return db8500_prcmu_gic_decouple();
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}
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static inline int prcmu_gic_recouple(void)
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{
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if (cpu_is_u5500())
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return -EINVAL;
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else
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return db8500_prcmu_gic_recouple();
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}
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static inline bool prcmu_gic_pending_irq(void)
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{
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if (cpu_is_u5500())
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return -EINVAL;
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else
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return db8500_prcmu_gic_pending_irq();
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}
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static inline bool prcmu_is_cpu_in_wfi(int cpu)
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{
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if (cpu_is_u5500())
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return -EINVAL;
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else
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return db8500_prcmu_is_cpu_in_wfi(cpu);
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}
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static inline int prcmu_copy_gic_settings(void)
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{
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if (cpu_is_u5500())
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return -EINVAL;
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else
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return db8500_prcmu_copy_gic_settings();
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}
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static inline bool prcmu_pending_irq(void)
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{
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if (cpu_is_u5500())
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return -EINVAL;
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else
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return db8500_prcmu_pending_irq();
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}
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static inline int prcmu_set_epod(u16 epod_id, u8 epod_state)
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{
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if (cpu_is_u5500())
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return -EINVAL;
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else
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return db8500_prcmu_set_epod(epod_id, epod_state);
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}
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static inline void prcmu_enable_wakeups(u32 wakeups)
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{
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if (cpu_is_u5500())
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db5500_prcmu_enable_wakeups(wakeups);
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else
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db8500_prcmu_enable_wakeups(wakeups);
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}
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static inline void prcmu_disable_wakeups(void)
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{
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prcmu_enable_wakeups(0);
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}
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static inline void prcmu_config_abb_event_readout(u32 abb_events)
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{
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if (cpu_is_u5500())
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db5500_prcmu_config_abb_event_readout(abb_events);
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else
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db8500_prcmu_config_abb_event_readout(abb_events);
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}
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static inline void prcmu_get_abb_event_buffer(void __iomem **buf)
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{
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if (cpu_is_u5500())
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db5500_prcmu_get_abb_event_buffer(buf);
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else
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db8500_prcmu_get_abb_event_buffer(buf);
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}
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int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size);
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int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size);
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int prcmu_abb_write_masked(u8 slave, u8 reg, u8 *value, u8 *mask, u8 size);
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int prcmu_config_clkout(u8 clkout, u8 source, u8 div);
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static inline int prcmu_request_clock(u8 clock, bool enable)
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{
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if (cpu_is_u5500())
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return db5500_prcmu_request_clock(clock, enable);
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else
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return db8500_prcmu_request_clock(clock, enable);
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}
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unsigned long prcmu_clock_rate(u8 clock);
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long prcmu_round_clock_rate(u8 clock, unsigned long rate);
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int prcmu_set_clock_rate(u8 clock, unsigned long rate);
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static inline int prcmu_set_ddr_opp(u8 opp)
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{
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if (cpu_is_u5500())
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return -EINVAL;
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else
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return db8500_prcmu_set_ddr_opp(opp);
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}
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static inline int prcmu_get_ddr_opp(void)
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{
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if (cpu_is_u5500())
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return -EINVAL;
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else
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return db8500_prcmu_get_ddr_opp();
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}
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static inline int prcmu_set_arm_opp(u8 opp)
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{
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if (cpu_is_u5500())
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return -EINVAL;
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else
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return db8500_prcmu_set_arm_opp(opp);
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}
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static inline int prcmu_get_arm_opp(void)
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{
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if (cpu_is_u5500())
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return -EINVAL;
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else
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return db8500_prcmu_get_arm_opp();
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}
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static inline int prcmu_set_ape_opp(u8 opp)
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{
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if (cpu_is_u5500())
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return -EINVAL;
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else
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return db8500_prcmu_set_ape_opp(opp);
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}
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static inline int prcmu_get_ape_opp(void)
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{
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if (cpu_is_u5500())
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return -EINVAL;
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else
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return db8500_prcmu_get_ape_opp();
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}
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static inline void prcmu_system_reset(u16 reset_code)
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{
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if (cpu_is_u5500())
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return db5500_prcmu_system_reset(reset_code);
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else
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return db8500_prcmu_system_reset(reset_code);
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}
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static inline u16 prcmu_get_reset_code(void)
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{
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if (cpu_is_u5500())
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return db5500_prcmu_get_reset_code();
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else
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return db8500_prcmu_get_reset_code();
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}
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void prcmu_ac_wake_req(void);
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void prcmu_ac_sleep_req(void);
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static inline void prcmu_modem_reset(void)
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{
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if (cpu_is_u5500())
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return;
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else
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return db8500_prcmu_modem_reset();
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}
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static inline bool prcmu_is_ac_wake_requested(void)
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{
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if (cpu_is_u5500())
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return db5500_prcmu_is_ac_wake_requested();
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else
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return db8500_prcmu_is_ac_wake_requested();
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}
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static inline int prcmu_set_display_clocks(void)
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{
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if (cpu_is_u5500())
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return db5500_prcmu_set_display_clocks();
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else
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return db8500_prcmu_set_display_clocks();
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}
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static inline int prcmu_disable_dsipll(void)
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{
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if (cpu_is_u5500())
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return db5500_prcmu_disable_dsipll();
|
|
else
|
|
return db8500_prcmu_disable_dsipll();
|
|
}
|
|
|
|
static inline int prcmu_enable_dsipll(void)
|
|
{
|
|
if (cpu_is_u5500())
|
|
return db5500_prcmu_enable_dsipll();
|
|
else
|
|
return db8500_prcmu_enable_dsipll();
|
|
}
|
|
|
|
static inline int prcmu_config_esram0_deep_sleep(u8 state)
|
|
{
|
|
if (cpu_is_u5500())
|
|
return -EINVAL;
|
|
else
|
|
return db8500_prcmu_config_esram0_deep_sleep(state);
|
|
}
|
|
|
|
static inline int prcmu_config_hotdog(u8 threshold)
|
|
{
|
|
if (cpu_is_u5500())
|
|
return -EINVAL;
|
|
else
|
|
return db8500_prcmu_config_hotdog(threshold);
|
|
}
|
|
|
|
static inline int prcmu_config_hotmon(u8 low, u8 high)
|
|
{
|
|
if (cpu_is_u5500())
|
|
return -EINVAL;
|
|
else
|
|
return db8500_prcmu_config_hotmon(low, high);
|
|
}
|
|
|
|
static inline int prcmu_start_temp_sense(u16 cycles32k)
|
|
{
|
|
if (cpu_is_u5500())
|
|
return -EINVAL;
|
|
else
|
|
return db8500_prcmu_start_temp_sense(cycles32k);
|
|
}
|
|
|
|
static inline int prcmu_stop_temp_sense(void)
|
|
{
|
|
if (cpu_is_u5500())
|
|
return -EINVAL;
|
|
else
|
|
return db8500_prcmu_stop_temp_sense();
|
|
}
|
|
|
|
static inline u32 prcmu_read(unsigned int reg)
|
|
{
|
|
if (cpu_is_u5500())
|
|
return -EINVAL;
|
|
else
|
|
return db8500_prcmu_read(reg);
|
|
}
|
|
|
|
static inline void prcmu_write(unsigned int reg, u32 value)
|
|
{
|
|
if (cpu_is_u5500())
|
|
return;
|
|
else
|
|
db8500_prcmu_write(reg, value);
|
|
}
|
|
|
|
static inline void prcmu_write_masked(unsigned int reg, u32 mask, u32 value)
|
|
{
|
|
if (cpu_is_u5500())
|
|
return;
|
|
else
|
|
db8500_prcmu_write_masked(reg, mask, value);
|
|
}
|
|
|
|
static inline int prcmu_enable_a9wdog(u8 id)
|
|
{
|
|
if (cpu_is_u5500())
|
|
return -EINVAL;
|
|
else
|
|
return db8500_prcmu_enable_a9wdog(id);
|
|
}
|
|
|
|
static inline int prcmu_disable_a9wdog(u8 id)
|
|
{
|
|
if (cpu_is_u5500())
|
|
return -EINVAL;
|
|
else
|
|
return db8500_prcmu_disable_a9wdog(id);
|
|
}
|
|
|
|
static inline int prcmu_kick_a9wdog(u8 id)
|
|
{
|
|
if (cpu_is_u5500())
|
|
return -EINVAL;
|
|
else
|
|
return db8500_prcmu_kick_a9wdog(id);
|
|
}
|
|
|
|
static inline int prcmu_load_a9wdog(u8 id, u32 timeout)
|
|
{
|
|
if (cpu_is_u5500())
|
|
return -EINVAL;
|
|
else
|
|
return db8500_prcmu_load_a9wdog(id, timeout);
|
|
}
|
|
|
|
static inline int prcmu_config_a9wdog(u8 num, bool sleep_auto_off)
|
|
{
|
|
if (cpu_is_u5500())
|
|
return -EINVAL;
|
|
else
|
|
return db8500_prcmu_config_a9wdog(num, sleep_auto_off);
|
|
}
|
|
#else
|
|
|
|
static inline void __init prcmu_early_init(void) {}
|
|
|
|
static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk,
|
|
bool keep_ap_pll)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline int prcmu_set_epod(u16 epod_id, u8 epod_state)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline void prcmu_enable_wakeups(u32 wakeups) {}
|
|
|
|
static inline void prcmu_disable_wakeups(void) {}
|
|
|
|
static inline int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size)
|
|
{
|
|
return -ENOSYS;
|
|
}
|
|
|
|
static inline int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size)
|
|
{
|
|
return -ENOSYS;
|
|
}
|
|
|
|
static inline int prcmu_abb_write_masked(u8 slave, u8 reg, u8 *value, u8 *mask,
|
|
u8 size)
|
|
{
|
|
return -ENOSYS;
|
|
}
|
|
|
|
static inline int prcmu_config_clkout(u8 clkout, u8 source, u8 div)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline int prcmu_request_clock(u8 clock, bool enable)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline long prcmu_round_clock_rate(u8 clock, unsigned long rate)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline int prcmu_set_clock_rate(u8 clock, unsigned long rate)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline unsigned long prcmu_clock_rate(u8 clock)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline int prcmu_set_ape_opp(u8 opp)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline int prcmu_get_ape_opp(void)
|
|
{
|
|
return APE_100_OPP;
|
|
}
|
|
|
|
static inline int prcmu_set_arm_opp(u8 opp)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline int prcmu_get_arm_opp(void)
|
|
{
|
|
return ARM_100_OPP;
|
|
}
|
|
|
|
static inline int prcmu_set_ddr_opp(u8 opp)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline int prcmu_get_ddr_opp(void)
|
|
{
|
|
return DDR_100_OPP;
|
|
}
|
|
|
|
static inline void prcmu_system_reset(u16 reset_code) {}
|
|
|
|
static inline u16 prcmu_get_reset_code(void)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline void prcmu_ac_wake_req(void) {}
|
|
|
|
static inline void prcmu_ac_sleep_req(void) {}
|
|
|
|
static inline void prcmu_modem_reset(void) {}
|
|
|
|
static inline bool prcmu_is_ac_wake_requested(void)
|
|
{
|
|
return false;
|
|
}
|
|
|
|
static inline int prcmu_set_display_clocks(void)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline int prcmu_disable_dsipll(void)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline int prcmu_enable_dsipll(void)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline int prcmu_config_esram0_deep_sleep(u8 state)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline void prcmu_config_abb_event_readout(u32 abb_events) {}
|
|
|
|
static inline void prcmu_get_abb_event_buffer(void __iomem **buf)
|
|
{
|
|
*buf = NULL;
|
|
}
|
|
|
|
static inline int prcmu_config_hotdog(u8 threshold)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline int prcmu_config_hotmon(u8 low, u8 high)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline int prcmu_start_temp_sense(u16 cycles32k)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline int prcmu_stop_temp_sense(void)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline u32 prcmu_read(unsigned int reg)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline void prcmu_write(unsigned int reg, u32 value) {}
|
|
|
|
static inline void prcmu_write_masked(unsigned int reg, u32 mask, u32 value) {}
|
|
|
|
#endif
|
|
|
|
static inline void prcmu_set(unsigned int reg, u32 bits)
|
|
{
|
|
prcmu_write_masked(reg, bits, bits);
|
|
}
|
|
|
|
static inline void prcmu_clear(unsigned int reg, u32 bits)
|
|
{
|
|
prcmu_write_masked(reg, bits, 0);
|
|
}
|
|
|
|
#if defined(CONFIG_UX500_SOC_DB8500) || defined(CONFIG_UX500_SOC_DB5500)
|
|
|
|
/**
|
|
* prcmu_enable_spi2 - Enables pin muxing for SPI2 on OtherAlternateC1.
|
|
*/
|
|
static inline void prcmu_enable_spi2(void)
|
|
{
|
|
if (cpu_is_u8500())
|
|
prcmu_set(DB8500_PRCM_GPIOCR, DB8500_PRCM_GPIOCR_SPI2_SELECT);
|
|
}
|
|
|
|
/**
|
|
* prcmu_disable_spi2 - Disables pin muxing for SPI2 on OtherAlternateC1.
|
|
*/
|
|
static inline void prcmu_disable_spi2(void)
|
|
{
|
|
if (cpu_is_u8500())
|
|
prcmu_clear(DB8500_PRCM_GPIOCR, DB8500_PRCM_GPIOCR_SPI2_SELECT);
|
|
}
|
|
|
|
/**
|
|
* prcmu_enable_stm_mod_uart - Enables pin muxing for STMMOD
|
|
* and UARTMOD on OtherAlternateC3.
|
|
*/
|
|
static inline void prcmu_enable_stm_mod_uart(void)
|
|
{
|
|
if (cpu_is_u8500()) {
|
|
prcmu_set(DB8500_PRCM_GPIOCR,
|
|
(DB8500_PRCM_GPIOCR_DBG_STM_MOD_CMD1 |
|
|
DB8500_PRCM_GPIOCR_DBG_UARTMOD_CMD0));
|
|
}
|
|
}
|
|
|
|
/**
|
|
* prcmu_disable_stm_mod_uart - Disables pin muxing for STMMOD
|
|
* and UARTMOD on OtherAlternateC3.
|
|
*/
|
|
static inline void prcmu_disable_stm_mod_uart(void)
|
|
{
|
|
if (cpu_is_u8500()) {
|
|
prcmu_clear(DB8500_PRCM_GPIOCR,
|
|
(DB8500_PRCM_GPIOCR_DBG_STM_MOD_CMD1 |
|
|
DB8500_PRCM_GPIOCR_DBG_UARTMOD_CMD0));
|
|
}
|
|
}
|
|
|
|
/**
|
|
* prcmu_enable_stm_ape - Enables pin muxing for STM APE on OtherAlternateC1.
|
|
*/
|
|
static inline void prcmu_enable_stm_ape(void)
|
|
{
|
|
if (cpu_is_u8500()) {
|
|
prcmu_set(DB8500_PRCM_GPIOCR,
|
|
DB8500_PRCM_GPIOCR_DBG_STM_APE_CMD);
|
|
}
|
|
}
|
|
|
|
/**
|
|
* prcmu_disable_stm_ape - Disables pin muxing for STM APE on OtherAlternateC1.
|
|
*/
|
|
static inline void prcmu_disable_stm_ape(void)
|
|
{
|
|
if (cpu_is_u8500()) {
|
|
prcmu_clear(DB8500_PRCM_GPIOCR,
|
|
DB8500_PRCM_GPIOCR_DBG_STM_APE_CMD);
|
|
}
|
|
}
|
|
|
|
#else
|
|
|
|
static inline void prcmu_enable_spi2(void) {}
|
|
static inline void prcmu_disable_spi2(void) {}
|
|
static inline void prcmu_enable_stm_mod_uart(void) {}
|
|
static inline void prcmu_disable_stm_mod_uart(void) {}
|
|
static inline void prcmu_enable_stm_ape(void) {}
|
|
static inline void prcmu_disable_stm_ape(void) {}
|
|
|
|
#endif
|
|
|
|
/* PRCMU QoS APE OPP class */
|
|
#define PRCMU_QOS_APE_OPP 1
|
|
#define PRCMU_QOS_DDR_OPP 2
|
|
#define PRCMU_QOS_ARM_OPP 3
|
|
#define PRCMU_QOS_DEFAULT_VALUE -1
|
|
|
|
#ifdef CONFIG_DBX500_PRCMU_QOS_POWER
|
|
|
|
unsigned long prcmu_qos_get_cpufreq_opp_delay(void);
|
|
void prcmu_qos_set_cpufreq_opp_delay(unsigned long);
|
|
void prcmu_qos_force_opp(int, s32);
|
|
int prcmu_qos_requirement(int pm_qos_class);
|
|
int prcmu_qos_add_requirement(int pm_qos_class, char *name, s32 value);
|
|
int prcmu_qos_update_requirement(int pm_qos_class, char *name, s32 new_value);
|
|
void prcmu_qos_remove_requirement(int pm_qos_class, char *name);
|
|
int prcmu_qos_add_notifier(int prcmu_qos_class,
|
|
struct notifier_block *notifier);
|
|
int prcmu_qos_remove_notifier(int prcmu_qos_class,
|
|
struct notifier_block *notifier);
|
|
|
|
#else
|
|
|
|
static inline unsigned long prcmu_qos_get_cpufreq_opp_delay(void)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline void prcmu_qos_set_cpufreq_opp_delay(unsigned long n) {}
|
|
|
|
static inline void prcmu_qos_force_opp(int prcmu_qos_class, s32 i) {}
|
|
|
|
static inline int prcmu_qos_requirement(int prcmu_qos_class)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline int prcmu_qos_add_requirement(int prcmu_qos_class,
|
|
char *name, s32 value)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline int prcmu_qos_update_requirement(int prcmu_qos_class,
|
|
char *name, s32 new_value)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline void prcmu_qos_remove_requirement(int prcmu_qos_class, char *name)
|
|
{
|
|
}
|
|
|
|
static inline int prcmu_qos_add_notifier(int prcmu_qos_class,
|
|
struct notifier_block *notifier)
|
|
{
|
|
return 0;
|
|
}
|
|
static inline int prcmu_qos_remove_notifier(int prcmu_qos_class,
|
|
struct notifier_block *notifier)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
#endif
|
|
|
|
#endif /* __MACH_PRCMU_H */
|