1626aeb881
The intention of using port_mask in SFF init helpers was to eventually support exoctic configurations such as combination of legacy and native port on the same controller. This never became actually necessary and the related code always has been subtly broken one way or the other. Now that new init model is in place, there is no reason to make common helpers capable of handling all corner cases. Exotic cases can simply dealt within LLDs as necessary. This patch removes port_mask handling in SFF init helpers. SFF init helpers don't take n_ports argument and interpret it into port_mask anymore. All information is carried via port_info. n_ports argument is dropped and always two ports are allocated. LLD can tell SFF to skip certain port by marking it dummy. Note that SFF code has been treating unuvailable ports this way for a long time until recent breakage fix from Linus and is consistent with how other drivers handle with unavailable ports. This fixes 1-port legacy host handling still broken after the recent native mode fix and simplifies SFF init logic. The following changes are made... * ata_pci_init_native_host() and ata_init_legacy_host() both now try to initialized whatever they can and mark failed ports dummy. They return 0 if any port is successfully initialized. * ata_pci_prepare_native_host() and ata_pci_init_one() now doesn't take n_ports argument. All info should be specified via port_info array. Always two ports are allocated. * ata_pci_init_bmdma() exported to be used by LLDs in exotic cases. * port_info handling in all LLDs are standardized - all port_info arrays are const stack variable named ppi. Unless the second port is different from the first, its port_info is specified as NULL (tells libata that it's identical to the last non-NULL port_info). * pata_hpt37x/hpt3x2n: don't modify static variable directly. Make an on-stack copy instead as ata_piix does. * pata_uli: It has 4 ports instead of 2. Don't use ata_pci_prepare_native_host(). Allocate the host explicitly and use init helpers. It's simple enough. Signed-off-by: Tejun Heo <htejun@gmail.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
400 lines
10 KiB
C
400 lines
10 KiB
C
/*
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* pata_pdc202xx_old.c - Promise PDC202xx PATA for new ATA layer
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* (C) 2005 Red Hat Inc
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* Alan Cox <alan@redhat.com>
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* (C) 2007 Bartlomiej Zolnierkiewicz
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*
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* Based in part on linux/drivers/ide/pci/pdc202xx_old.c
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*
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* First cut with LBA48/ATAPI
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*
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* TODO:
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* Channel interlock/reset on both required
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/blkdev.h>
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#include <linux/delay.h>
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#include <scsi/scsi_host.h>
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#include <linux/libata.h>
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#define DRV_NAME "pata_pdc202xx_old"
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#define DRV_VERSION "0.4.2"
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static int pdc2026x_cable_detect(struct ata_port *ap)
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{
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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u16 cis;
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pci_read_config_word(pdev, 0x50, &cis);
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if (cis & (1 << (10 + ap->port_no)))
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return ATA_CBL_PATA80;
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return ATA_CBL_PATA40;
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}
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/**
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* pdc202xx_configure_piomode - set chip PIO timing
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* @ap: ATA interface
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* @adev: ATA device
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* @pio: PIO mode
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*
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* Called to do the PIO mode setup. Our timing registers are shared
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* so a configure_dmamode call will undo any work we do here and vice
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* versa
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*/
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static void pdc202xx_configure_piomode(struct ata_port *ap, struct ata_device *adev, int pio)
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{
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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int port = 0x60 + 8 * ap->port_no + 4 * adev->devno;
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static u16 pio_timing[5] = {
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0x0913, 0x050C , 0x0308, 0x0206, 0x0104
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};
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u8 r_ap, r_bp;
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pci_read_config_byte(pdev, port, &r_ap);
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pci_read_config_byte(pdev, port + 1, &r_bp);
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r_ap &= ~0x3F; /* Preserve ERRDY_EN, SYNC_IN */
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r_bp &= ~0x1F;
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r_ap |= (pio_timing[pio] >> 8);
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r_bp |= (pio_timing[pio] & 0xFF);
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if (ata_pio_need_iordy(adev))
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r_ap |= 0x20; /* IORDY enable */
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if (adev->class == ATA_DEV_ATA)
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r_ap |= 0x10; /* FIFO enable */
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pci_write_config_byte(pdev, port, r_ap);
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pci_write_config_byte(pdev, port + 1, r_bp);
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}
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/**
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* pdc202xx_set_piomode - set initial PIO mode data
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* @ap: ATA interface
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* @adev: ATA device
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*
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* Called to do the PIO mode setup. Our timing registers are shared
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* but we want to set the PIO timing by default.
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*/
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static void pdc202xx_set_piomode(struct ata_port *ap, struct ata_device *adev)
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{
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pdc202xx_configure_piomode(ap, adev, adev->pio_mode - XFER_PIO_0);
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}
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/**
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* pdc202xx_configure_dmamode - set DMA mode in chip
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* @ap: ATA interface
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* @adev: ATA device
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*
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* Load DMA cycle times into the chip ready for a DMA transfer
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* to occur.
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*/
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static void pdc202xx_set_dmamode(struct ata_port *ap, struct ata_device *adev)
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{
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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int port = 0x60 + 8 * ap->port_no + 4 * adev->devno;
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static u8 udma_timing[6][2] = {
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{ 0x60, 0x03 }, /* 33 Mhz Clock */
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{ 0x40, 0x02 },
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{ 0x20, 0x01 },
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{ 0x40, 0x02 }, /* 66 Mhz Clock */
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{ 0x20, 0x01 },
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{ 0x20, 0x01 }
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};
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static u8 mdma_timing[3][2] = {
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{ 0x60, 0x03 },
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{ 0x60, 0x04 },
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{ 0xe0, 0x0f },
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};
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u8 r_bp, r_cp;
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pci_read_config_byte(pdev, port + 1, &r_bp);
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pci_read_config_byte(pdev, port + 2, &r_cp);
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r_bp &= ~0xE0;
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r_cp &= ~0x0F;
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if (adev->dma_mode >= XFER_UDMA_0) {
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int speed = adev->dma_mode - XFER_UDMA_0;
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r_bp |= udma_timing[speed][0];
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r_cp |= udma_timing[speed][1];
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} else {
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int speed = adev->dma_mode - XFER_MW_DMA_0;
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r_bp |= mdma_timing[speed][0];
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r_cp |= mdma_timing[speed][1];
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}
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pci_write_config_byte(pdev, port + 1, r_bp);
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pci_write_config_byte(pdev, port + 2, r_cp);
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}
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/**
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* pdc2026x_bmdma_start - DMA engine begin
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* @qc: ATA command
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*
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* In UDMA3 or higher we have to clock switch for the duration of the
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* DMA transfer sequence.
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*/
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static void pdc2026x_bmdma_start(struct ata_queued_cmd *qc)
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{
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struct ata_port *ap = qc->ap;
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struct ata_device *adev = qc->dev;
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struct ata_taskfile *tf = &qc->tf;
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int sel66 = ap->port_no ? 0x08: 0x02;
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void __iomem *master = ap->host->ports[0]->ioaddr.bmdma_addr;
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void __iomem *clock = master + 0x11;
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void __iomem *atapi_reg = master + 0x20 + (4 * ap->port_no);
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u32 len;
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/* Check we keep host level locking here */
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if (adev->dma_mode >= XFER_UDMA_2)
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iowrite8(ioread8(clock) | sel66, clock);
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else
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iowrite8(ioread8(clock) & ~sel66, clock);
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/* The DMA clocks may have been trashed by a reset. FIXME: make conditional
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and move to qc_issue ? */
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pdc202xx_set_dmamode(ap, qc->dev);
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/* Cases the state machine will not complete correctly without help */
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if ((tf->flags & ATA_TFLAG_LBA48) || tf->protocol == ATA_PROT_ATAPI_DMA)
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{
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len = qc->nbytes / 2;
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if (tf->flags & ATA_TFLAG_WRITE)
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len |= 0x06000000;
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else
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len |= 0x05000000;
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iowrite32(len, atapi_reg);
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}
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/* Activate DMA */
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ata_bmdma_start(qc);
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}
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/**
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* pdc2026x_bmdma_end - DMA engine stop
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* @qc: ATA command
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*
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* After a DMA completes we need to put the clock back to 33MHz for
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* PIO timings.
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*/
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static void pdc2026x_bmdma_stop(struct ata_queued_cmd *qc)
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{
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struct ata_port *ap = qc->ap;
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struct ata_device *adev = qc->dev;
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struct ata_taskfile *tf = &qc->tf;
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int sel66 = ap->port_no ? 0x08: 0x02;
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/* The clock bits are in the same register for both channels */
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void __iomem *master = ap->host->ports[0]->ioaddr.bmdma_addr;
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void __iomem *clock = master + 0x11;
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void __iomem *atapi_reg = master + 0x20 + (4 * ap->port_no);
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/* Cases the state machine will not complete correctly */
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if (tf->protocol == ATA_PROT_ATAPI_DMA || ( tf->flags & ATA_TFLAG_LBA48)) {
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iowrite32(0, atapi_reg);
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iowrite8(ioread8(clock) & ~sel66, clock);
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}
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/* Check we keep host level locking here */
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/* Flip back to 33Mhz for PIO */
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if (adev->dma_mode >= XFER_UDMA_2)
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iowrite8(ioread8(clock) & ~sel66, clock);
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ata_bmdma_stop(qc);
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}
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/**
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* pdc2026x_dev_config - device setup hook
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* @adev: newly found device
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*
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* Perform chip specific early setup. We need to lock the transfer
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* sizes to 8bit to avoid making the state engine on the 2026x cards
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* barf.
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*/
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static void pdc2026x_dev_config(struct ata_device *adev)
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{
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adev->max_sectors = 256;
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}
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static struct scsi_host_template pdc202xx_sht = {
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.module = THIS_MODULE,
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.name = DRV_NAME,
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.ioctl = ata_scsi_ioctl,
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.queuecommand = ata_scsi_queuecmd,
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.can_queue = ATA_DEF_QUEUE,
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.this_id = ATA_SHT_THIS_ID,
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.sg_tablesize = LIBATA_MAX_PRD,
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.cmd_per_lun = ATA_SHT_CMD_PER_LUN,
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.emulated = ATA_SHT_EMULATED,
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.use_clustering = ATA_SHT_USE_CLUSTERING,
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.proc_name = DRV_NAME,
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.dma_boundary = ATA_DMA_BOUNDARY,
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.slave_configure = ata_scsi_slave_config,
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.slave_destroy = ata_scsi_slave_destroy,
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.bios_param = ata_std_bios_param,
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};
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static struct ata_port_operations pdc2024x_port_ops = {
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.port_disable = ata_port_disable,
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.set_piomode = pdc202xx_set_piomode,
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.set_dmamode = pdc202xx_set_dmamode,
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.mode_filter = ata_pci_default_filter,
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.tf_load = ata_tf_load,
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.tf_read = ata_tf_read,
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.check_status = ata_check_status,
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.exec_command = ata_exec_command,
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.dev_select = ata_std_dev_select,
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.freeze = ata_bmdma_freeze,
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.thaw = ata_bmdma_thaw,
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.error_handler = ata_bmdma_error_handler,
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.post_internal_cmd = ata_bmdma_post_internal_cmd,
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.cable_detect = ata_cable_40wire,
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.bmdma_setup = ata_bmdma_setup,
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.bmdma_start = ata_bmdma_start,
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.bmdma_stop = ata_bmdma_stop,
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.bmdma_status = ata_bmdma_status,
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.qc_prep = ata_qc_prep,
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.qc_issue = ata_qc_issue_prot,
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.data_xfer = ata_data_xfer,
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.irq_handler = ata_interrupt,
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.irq_clear = ata_bmdma_irq_clear,
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.irq_on = ata_irq_on,
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.irq_ack = ata_irq_ack,
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.port_start = ata_port_start,
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};
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static struct ata_port_operations pdc2026x_port_ops = {
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.port_disable = ata_port_disable,
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.set_piomode = pdc202xx_set_piomode,
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.set_dmamode = pdc202xx_set_dmamode,
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.mode_filter = ata_pci_default_filter,
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.tf_load = ata_tf_load,
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.tf_read = ata_tf_read,
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.check_status = ata_check_status,
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.exec_command = ata_exec_command,
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.dev_select = ata_std_dev_select,
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.dev_config = pdc2026x_dev_config,
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.freeze = ata_bmdma_freeze,
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.thaw = ata_bmdma_thaw,
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.error_handler = ata_bmdma_error_handler,
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.post_internal_cmd = ata_bmdma_post_internal_cmd,
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.cable_detect = pdc2026x_cable_detect,
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.bmdma_setup = ata_bmdma_setup,
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.bmdma_start = pdc2026x_bmdma_start,
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.bmdma_stop = pdc2026x_bmdma_stop,
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.bmdma_status = ata_bmdma_status,
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.qc_prep = ata_qc_prep,
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.qc_issue = ata_qc_issue_prot,
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.data_xfer = ata_data_xfer,
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.irq_handler = ata_interrupt,
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.irq_clear = ata_bmdma_irq_clear,
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.irq_on = ata_irq_on,
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.irq_ack = ata_irq_ack,
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.port_start = ata_port_start,
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};
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static int pdc202xx_init_one(struct pci_dev *dev, const struct pci_device_id *id)
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{
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static const struct ata_port_info info[3] = {
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{
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.sht = &pdc202xx_sht,
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.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
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.pio_mask = 0x1f,
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.mwdma_mask = 0x07,
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.udma_mask = ATA_UDMA2,
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.port_ops = &pdc2024x_port_ops
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},
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{
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.sht = &pdc202xx_sht,
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.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
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.pio_mask = 0x1f,
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.mwdma_mask = 0x07,
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.udma_mask = ATA_UDMA4,
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.port_ops = &pdc2026x_port_ops
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},
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{
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.sht = &pdc202xx_sht,
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.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
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.pio_mask = 0x1f,
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.mwdma_mask = 0x07,
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.udma_mask = ATA_UDMA5,
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.port_ops = &pdc2026x_port_ops
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}
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};
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const struct ata_port_info *ppi[] = { &info[id->driver_data], NULL };
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if (dev->device == PCI_DEVICE_ID_PROMISE_20265) {
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struct pci_dev *bridge = dev->bus->self;
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/* Don't grab anything behind a Promise I2O RAID */
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if (bridge && bridge->vendor == PCI_VENDOR_ID_INTEL) {
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if( bridge->device == PCI_DEVICE_ID_INTEL_I960)
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return -ENODEV;
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if( bridge->device == PCI_DEVICE_ID_INTEL_I960RM)
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return -ENODEV;
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}
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}
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return ata_pci_init_one(dev, ppi);
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}
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static const struct pci_device_id pdc202xx[] = {
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{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20246), 0 },
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{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20262), 1 },
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{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20263), 1 },
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{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20265), 2 },
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{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20267), 2 },
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{ },
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};
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static struct pci_driver pdc202xx_pci_driver = {
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.name = DRV_NAME,
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.id_table = pdc202xx,
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.probe = pdc202xx_init_one,
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.remove = ata_pci_remove_one,
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#ifdef CONFIG_PM
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.suspend = ata_pci_device_suspend,
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.resume = ata_pci_device_resume,
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#endif
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};
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static int __init pdc202xx_init(void)
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{
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return pci_register_driver(&pdc202xx_pci_driver);
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}
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static void __exit pdc202xx_exit(void)
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{
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pci_unregister_driver(&pdc202xx_pci_driver);
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}
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MODULE_AUTHOR("Alan Cox");
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MODULE_DESCRIPTION("low-level driver for Promise 2024x and 20262-20267");
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MODULE_LICENSE("GPL");
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MODULE_DEVICE_TABLE(pci, pdc202xx);
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MODULE_VERSION(DRV_VERSION);
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module_init(pdc202xx_init);
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module_exit(pdc202xx_exit);
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