0397526d6a
While we're at it, add symbols for SDHCI_MAX_DIV_SPEC_{200,300}.
Signed-off-by: Zhangfei Gao <zhangfei.gao@marvell.com>
Signed-off-by: Chris Ball <cjb@laptop.org>
443 lines
14 KiB
C
443 lines
14 KiB
C
/*
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* linux/drivers/mmc/host/sdhci.h - Secure Digital Host Controller Interface driver
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*
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* Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or (at
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* your option) any later version.
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*/
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#ifndef __SDHCI_H
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#define __SDHCI_H
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#include <linux/scatterlist.h>
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#include <linux/compiler.h>
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#include <linux/types.h>
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#include <linux/io.h>
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/*
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* Controller registers
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*/
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#define SDHCI_DMA_ADDRESS 0x00
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#define SDHCI_BLOCK_SIZE 0x04
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#define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF))
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#define SDHCI_BLOCK_COUNT 0x06
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#define SDHCI_ARGUMENT 0x08
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#define SDHCI_TRANSFER_MODE 0x0C
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#define SDHCI_TRNS_DMA 0x01
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#define SDHCI_TRNS_BLK_CNT_EN 0x02
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#define SDHCI_TRNS_ACMD12 0x04
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#define SDHCI_TRNS_READ 0x10
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#define SDHCI_TRNS_MULTI 0x20
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#define SDHCI_COMMAND 0x0E
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#define SDHCI_CMD_RESP_MASK 0x03
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#define SDHCI_CMD_CRC 0x08
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#define SDHCI_CMD_INDEX 0x10
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#define SDHCI_CMD_DATA 0x20
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#define SDHCI_CMD_RESP_NONE 0x00
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#define SDHCI_CMD_RESP_LONG 0x01
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#define SDHCI_CMD_RESP_SHORT 0x02
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#define SDHCI_CMD_RESP_SHORT_BUSY 0x03
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#define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff))
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#define SDHCI_RESPONSE 0x10
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#define SDHCI_BUFFER 0x20
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#define SDHCI_PRESENT_STATE 0x24
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#define SDHCI_CMD_INHIBIT 0x00000001
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#define SDHCI_DATA_INHIBIT 0x00000002
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#define SDHCI_DOING_WRITE 0x00000100
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#define SDHCI_DOING_READ 0x00000200
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#define SDHCI_SPACE_AVAILABLE 0x00000400
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#define SDHCI_DATA_AVAILABLE 0x00000800
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#define SDHCI_CARD_PRESENT 0x00010000
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#define SDHCI_WRITE_PROTECT 0x00080000
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#define SDHCI_HOST_CONTROL 0x28
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#define SDHCI_CTRL_LED 0x01
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#define SDHCI_CTRL_4BITBUS 0x02
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#define SDHCI_CTRL_HISPD 0x04
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#define SDHCI_CTRL_DMA_MASK 0x18
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#define SDHCI_CTRL_SDMA 0x00
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#define SDHCI_CTRL_ADMA1 0x08
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#define SDHCI_CTRL_ADMA32 0x10
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#define SDHCI_CTRL_ADMA64 0x18
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#define SDHCI_CTRL_8BITBUS 0x20
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#define SDHCI_POWER_CONTROL 0x29
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#define SDHCI_POWER_ON 0x01
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#define SDHCI_POWER_180 0x0A
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#define SDHCI_POWER_300 0x0C
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#define SDHCI_POWER_330 0x0E
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#define SDHCI_BLOCK_GAP_CONTROL 0x2A
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#define SDHCI_WAKE_UP_CONTROL 0x2B
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#define SDHCI_CLOCK_CONTROL 0x2C
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#define SDHCI_DIVIDER_SHIFT 8
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#define SDHCI_DIVIDER_HI_SHIFT 6
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#define SDHCI_DIV_MASK 0xFF
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#define SDHCI_DIV_MASK_LEN 8
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#define SDHCI_DIV_HI_MASK 0x300
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#define SDHCI_CLOCK_CARD_EN 0x0004
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#define SDHCI_CLOCK_INT_STABLE 0x0002
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#define SDHCI_CLOCK_INT_EN 0x0001
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#define SDHCI_TIMEOUT_CONTROL 0x2E
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#define SDHCI_SOFTWARE_RESET 0x2F
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#define SDHCI_RESET_ALL 0x01
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#define SDHCI_RESET_CMD 0x02
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#define SDHCI_RESET_DATA 0x04
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#define SDHCI_INT_STATUS 0x30
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#define SDHCI_INT_ENABLE 0x34
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#define SDHCI_SIGNAL_ENABLE 0x38
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#define SDHCI_INT_RESPONSE 0x00000001
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#define SDHCI_INT_DATA_END 0x00000002
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#define SDHCI_INT_DMA_END 0x00000008
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#define SDHCI_INT_SPACE_AVAIL 0x00000010
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#define SDHCI_INT_DATA_AVAIL 0x00000020
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#define SDHCI_INT_CARD_INSERT 0x00000040
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#define SDHCI_INT_CARD_REMOVE 0x00000080
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#define SDHCI_INT_CARD_INT 0x00000100
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#define SDHCI_INT_ERROR 0x00008000
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#define SDHCI_INT_TIMEOUT 0x00010000
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#define SDHCI_INT_CRC 0x00020000
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#define SDHCI_INT_END_BIT 0x00040000
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#define SDHCI_INT_INDEX 0x00080000
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#define SDHCI_INT_DATA_TIMEOUT 0x00100000
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#define SDHCI_INT_DATA_CRC 0x00200000
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#define SDHCI_INT_DATA_END_BIT 0x00400000
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#define SDHCI_INT_BUS_POWER 0x00800000
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#define SDHCI_INT_ACMD12ERR 0x01000000
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#define SDHCI_INT_ADMA_ERROR 0x02000000
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#define SDHCI_INT_NORMAL_MASK 0x00007FFF
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#define SDHCI_INT_ERROR_MASK 0xFFFF8000
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#define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | \
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SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX)
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#define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \
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SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \
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SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \
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SDHCI_INT_DATA_END_BIT | SDHCI_INT_ADMA_ERROR)
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#define SDHCI_INT_ALL_MASK ((unsigned int)-1)
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#define SDHCI_ACMD12_ERR 0x3C
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/* 3E-3F reserved */
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#define SDHCI_CAPABILITIES 0x40
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#define SDHCI_TIMEOUT_CLK_MASK 0x0000003F
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#define SDHCI_TIMEOUT_CLK_SHIFT 0
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#define SDHCI_TIMEOUT_CLK_UNIT 0x00000080
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#define SDHCI_CLOCK_BASE_MASK 0x00003F00
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#define SDHCI_CLOCK_V3_BASE_MASK 0x0000FF00
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#define SDHCI_CLOCK_BASE_SHIFT 8
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#define SDHCI_MAX_BLOCK_MASK 0x00030000
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#define SDHCI_MAX_BLOCK_SHIFT 16
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#define SDHCI_CAN_DO_ADMA2 0x00080000
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#define SDHCI_CAN_DO_ADMA1 0x00100000
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#define SDHCI_CAN_DO_HISPD 0x00200000
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#define SDHCI_CAN_DO_SDMA 0x00400000
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#define SDHCI_CAN_VDD_330 0x01000000
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#define SDHCI_CAN_VDD_300 0x02000000
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#define SDHCI_CAN_VDD_180 0x04000000
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#define SDHCI_CAN_64BIT 0x10000000
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/* 44-47 reserved for more caps */
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#define SDHCI_MAX_CURRENT 0x48
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/* 4C-4F reserved for more max current */
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#define SDHCI_SET_ACMD12_ERROR 0x50
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#define SDHCI_SET_INT_ERROR 0x52
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#define SDHCI_ADMA_ERROR 0x54
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/* 55-57 reserved */
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#define SDHCI_ADMA_ADDRESS 0x58
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/* 60-FB reserved */
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#define SDHCI_SLOT_INT_STATUS 0xFC
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#define SDHCI_HOST_VERSION 0xFE
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#define SDHCI_VENDOR_VER_MASK 0xFF00
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#define SDHCI_VENDOR_VER_SHIFT 8
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#define SDHCI_SPEC_VER_MASK 0x00FF
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#define SDHCI_SPEC_VER_SHIFT 0
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#define SDHCI_SPEC_100 0
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#define SDHCI_SPEC_200 1
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#define SDHCI_SPEC_300 2
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/*
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* End of controller registers.
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*/
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#define SDHCI_MAX_DIV_SPEC_200 256
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#define SDHCI_MAX_DIV_SPEC_300 2046
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struct sdhci_ops;
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struct sdhci_host {
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/* Data set by hardware interface driver */
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const char *hw_name; /* Hardware bus name */
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unsigned int quirks; /* Deviations from spec. */
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/* Controller doesn't honor resets unless we touch the clock register */
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#define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1<<0)
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/* Controller has bad caps bits, but really supports DMA */
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#define SDHCI_QUIRK_FORCE_DMA (1<<1)
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/* Controller doesn't like to be reset when there is no card inserted. */
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#define SDHCI_QUIRK_NO_CARD_NO_RESET (1<<2)
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/* Controller doesn't like clearing the power reg before a change */
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#define SDHCI_QUIRK_SINGLE_POWER_WRITE (1<<3)
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/* Controller has flaky internal state so reset it on each ios change */
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#define SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS (1<<4)
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/* Controller has an unusable DMA engine */
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#define SDHCI_QUIRK_BROKEN_DMA (1<<5)
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/* Controller has an unusable ADMA engine */
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#define SDHCI_QUIRK_BROKEN_ADMA (1<<6)
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/* Controller can only DMA from 32-bit aligned addresses */
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#define SDHCI_QUIRK_32BIT_DMA_ADDR (1<<7)
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/* Controller can only DMA chunk sizes that are a multiple of 32 bits */
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#define SDHCI_QUIRK_32BIT_DMA_SIZE (1<<8)
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/* Controller can only ADMA chunks that are a multiple of 32 bits */
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#define SDHCI_QUIRK_32BIT_ADMA_SIZE (1<<9)
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/* Controller needs to be reset after each request to stay stable */
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#define SDHCI_QUIRK_RESET_AFTER_REQUEST (1<<10)
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/* Controller needs voltage and power writes to happen separately */
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#define SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER (1<<11)
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/* Controller provides an incorrect timeout value for transfers */
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#define SDHCI_QUIRK_BROKEN_TIMEOUT_VAL (1<<12)
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/* Controller has an issue with buffer bits for small transfers */
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#define SDHCI_QUIRK_BROKEN_SMALL_PIO (1<<13)
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/* Controller does not provide transfer-complete interrupt when not busy */
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#define SDHCI_QUIRK_NO_BUSY_IRQ (1<<14)
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/* Controller has unreliable card detection */
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#define SDHCI_QUIRK_BROKEN_CARD_DETECTION (1<<15)
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/* Controller reports inverted write-protect state */
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#define SDHCI_QUIRK_INVERTED_WRITE_PROTECT (1<<16)
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/* Controller has nonstandard clock management */
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#define SDHCI_QUIRK_NONSTANDARD_CLOCK (1<<17)
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/* Controller does not like fast PIO transfers */
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#define SDHCI_QUIRK_PIO_NEEDS_DELAY (1<<18)
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/* Controller losing signal/interrupt enable states after reset */
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#define SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET (1<<19)
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/* Controller has to be forced to use block size of 2048 bytes */
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#define SDHCI_QUIRK_FORCE_BLK_SZ_2048 (1<<20)
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/* Controller cannot do multi-block transfers */
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#define SDHCI_QUIRK_NO_MULTIBLOCK (1<<21)
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/* Controller can only handle 1-bit data transfers */
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#define SDHCI_QUIRK_FORCE_1_BIT_DATA (1<<22)
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/* Controller needs 10ms delay between applying power and clock */
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#define SDHCI_QUIRK_DELAY_AFTER_POWER (1<<23)
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/* Controller uses SDCLK instead of TMCLK for data timeouts */
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#define SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK (1<<24)
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/* Controller reports wrong base clock capability */
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#define SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN (1<<25)
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/* Controller cannot support End Attribute in NOP ADMA descriptor */
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#define SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC (1<<26)
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/* Controller is missing device caps. Use caps provided by host */
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#define SDHCI_QUIRK_MISSING_CAPS (1<<27)
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/* Controller uses Auto CMD12 command to stop the transfer */
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#define SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12 (1<<28)
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/* Controller doesn't have HISPD bit field in HI-SPEED SD card */
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#define SDHCI_QUIRK_NO_HISPD_BIT (1<<29)
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int irq; /* Device IRQ */
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void __iomem * ioaddr; /* Mapped address */
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const struct sdhci_ops *ops; /* Low level hw interface */
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struct regulator *vmmc; /* Power regulator */
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/* Internal data */
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struct mmc_host *mmc; /* MMC structure */
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u64 dma_mask; /* custom DMA mask */
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#if defined(CONFIG_LEDS_CLASS) || defined(CONFIG_LEDS_CLASS_MODULE)
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struct led_classdev led; /* LED control */
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char led_name[32];
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#endif
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spinlock_t lock; /* Mutex */
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int flags; /* Host attributes */
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#define SDHCI_USE_SDMA (1<<0) /* Host is SDMA capable */
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#define SDHCI_USE_ADMA (1<<1) /* Host is ADMA capable */
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#define SDHCI_REQ_USE_DMA (1<<2) /* Use DMA for this req. */
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#define SDHCI_DEVICE_DEAD (1<<3) /* Device unresponsive */
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unsigned int version; /* SDHCI spec. version */
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unsigned int max_clk; /* Max possible freq (MHz) */
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unsigned int timeout_clk; /* Timeout freq (KHz) */
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unsigned int clock; /* Current clock (MHz) */
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u8 pwr; /* Current voltage */
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struct mmc_request *mrq; /* Current request */
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struct mmc_command *cmd; /* Current command */
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struct mmc_data *data; /* Current data request */
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unsigned int data_early:1; /* Data finished before cmd */
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struct sg_mapping_iter sg_miter; /* SG state for PIO */
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unsigned int blocks; /* remaining PIO blocks */
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int sg_count; /* Mapped sg entries */
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u8 *adma_desc; /* ADMA descriptor table */
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u8 *align_buffer; /* Bounce buffer */
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dma_addr_t adma_addr; /* Mapped ADMA descr. table */
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dma_addr_t align_addr; /* Mapped bounce buffer */
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struct tasklet_struct card_tasklet; /* Tasklet structures */
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struct tasklet_struct finish_tasklet;
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struct timer_list timer; /* Timer for timeouts */
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unsigned int caps; /* Alternative capabilities */
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unsigned long private[0] ____cacheline_aligned;
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};
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struct sdhci_ops {
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#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
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u32 (*read_l)(struct sdhci_host *host, int reg);
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u16 (*read_w)(struct sdhci_host *host, int reg);
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u8 (*read_b)(struct sdhci_host *host, int reg);
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void (*write_l)(struct sdhci_host *host, u32 val, int reg);
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void (*write_w)(struct sdhci_host *host, u16 val, int reg);
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void (*write_b)(struct sdhci_host *host, u8 val, int reg);
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#endif
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void (*set_clock)(struct sdhci_host *host, unsigned int clock);
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int (*enable_dma)(struct sdhci_host *host);
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unsigned int (*get_max_clock)(struct sdhci_host *host);
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unsigned int (*get_min_clock)(struct sdhci_host *host);
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unsigned int (*get_timeout_clock)(struct sdhci_host *host);
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};
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#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
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static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)
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{
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if (unlikely(host->ops->write_l))
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host->ops->write_l(host, val, reg);
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else
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writel(val, host->ioaddr + reg);
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}
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static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg)
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{
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if (unlikely(host->ops->write_w))
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host->ops->write_w(host, val, reg);
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else
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writew(val, host->ioaddr + reg);
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}
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static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
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{
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if (unlikely(host->ops->write_b))
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host->ops->write_b(host, val, reg);
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else
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writeb(val, host->ioaddr + reg);
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}
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static inline u32 sdhci_readl(struct sdhci_host *host, int reg)
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{
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if (unlikely(host->ops->read_l))
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return host->ops->read_l(host, reg);
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else
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return readl(host->ioaddr + reg);
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}
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static inline u16 sdhci_readw(struct sdhci_host *host, int reg)
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{
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if (unlikely(host->ops->read_w))
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return host->ops->read_w(host, reg);
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else
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return readw(host->ioaddr + reg);
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}
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static inline u8 sdhci_readb(struct sdhci_host *host, int reg)
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{
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if (unlikely(host->ops->read_b))
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return host->ops->read_b(host, reg);
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else
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return readb(host->ioaddr + reg);
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}
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#else
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static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)
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{
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writel(val, host->ioaddr + reg);
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}
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static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg)
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{
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writew(val, host->ioaddr + reg);
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}
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static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
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{
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writeb(val, host->ioaddr + reg);
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}
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static inline u32 sdhci_readl(struct sdhci_host *host, int reg)
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{
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return readl(host->ioaddr + reg);
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}
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static inline u16 sdhci_readw(struct sdhci_host *host, int reg)
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{
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return readw(host->ioaddr + reg);
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}
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static inline u8 sdhci_readb(struct sdhci_host *host, int reg)
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{
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return readb(host->ioaddr + reg);
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}
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#endif /* CONFIG_MMC_SDHCI_IO_ACCESSORS */
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extern struct sdhci_host *sdhci_alloc_host(struct device *dev,
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size_t priv_size);
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extern void sdhci_free_host(struct sdhci_host *host);
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static inline void *sdhci_priv(struct sdhci_host *host)
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{
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return (void *)host->private;
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}
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extern void sdhci_card_detect(struct sdhci_host *host);
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extern int sdhci_add_host(struct sdhci_host *host);
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extern void sdhci_remove_host(struct sdhci_host *host, int dead);
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#ifdef CONFIG_PM
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extern int sdhci_suspend_host(struct sdhci_host *host, pm_message_t state);
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extern int sdhci_resume_host(struct sdhci_host *host);
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#endif
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#endif /* __SDHCI_H */
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