f9e7592230
Select the generic mvebu kirkwood pincltr driver and generic mvebu gpio driver. This requires minor changes to the DT, and the calls to configure plat-orion gpio driver are removed. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Tested-by: Michael Walle <michael@walle.cc> Tested-by: Simon Baatz <gmbnomis@gmail.com> Tested-by: Jamie Lentin <jm@lentin.co.uk> Tested-by: Joshua Coombs <josh.coombs@gmail.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
70 lines
1.6 KiB
C
70 lines
1.6 KiB
C
/*
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* arch/arm/plat-orion/irq.c
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*
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* Marvell Orion SoC IRQ handling.
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/irqdomain.h>
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#include <linux/io.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <plat/irq.h>
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#include <plat/orion-gpio.h>
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void __init orion_irq_init(unsigned int irq_start, void __iomem *maskaddr)
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{
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struct irq_chip_generic *gc;
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struct irq_chip_type *ct;
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/*
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* Mask all interrupts initially.
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*/
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writel(0, maskaddr);
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gc = irq_alloc_generic_chip("orion_irq", 1, irq_start, maskaddr,
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handle_level_irq);
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ct = gc->chip_types;
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ct->chip.irq_mask = irq_gc_mask_clr_bit;
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ct->chip.irq_unmask = irq_gc_mask_set_bit;
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irq_setup_generic_chip(gc, IRQ_MSK(32), IRQ_GC_INIT_MASK_CACHE,
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IRQ_NOREQUEST, IRQ_LEVEL | IRQ_NOPROBE);
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}
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#ifdef CONFIG_OF
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static int __init orion_add_irq_domain(struct device_node *np,
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struct device_node *interrupt_parent)
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{
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int i = 0;
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void __iomem *base;
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do {
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base = of_iomap(np, i);
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if (base) {
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orion_irq_init(i * 32, base);
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i++;
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}
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} while (base);
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irq_domain_add_legacy(np, i * 32, 0, 0,
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&irq_domain_simple_ops, NULL);
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return 0;
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}
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static const struct of_device_id orion_irq_match[] = {
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{ .compatible = "marvell,orion-intc",
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.data = orion_add_irq_domain, },
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{},
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};
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void __init orion_dt_init_irq(void)
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{
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of_irq_init(orion_irq_match);
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}
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#endif
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