bac4e960b5
Mathieu Desnoyers pointed out that the ARM barriers were lacking: - cmpxchg, xchg and atomic add return need memory barriers on architectures which can reorder the relative order in which memory read/writes can be seen between CPUs, which seems to include recent ARM architectures. Those barriers are currently missing on ARM. - test_and_xxx_bit were missing SMP barriers. So put these barriers in. Provide separate atomic_add/atomic_sub operations which do not require barriers. Reported-Reviewed-and-Acked-by: Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
67 lines
1.3 KiB
C
67 lines
1.3 KiB
C
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#if __LINUX_ARM_ARCH__ >= 6 && defined(CONFIG_CPU_32v6K)
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.macro bitop, instr
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mov r2, #1
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and r3, r0, #7 @ Get bit offset
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add r1, r1, r0, lsr #3 @ Get byte offset
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mov r3, r2, lsl r3
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1: ldrexb r2, [r1]
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\instr r2, r2, r3
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strexb r0, r2, [r1]
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cmp r0, #0
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bne 1b
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mov pc, lr
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.endm
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.macro testop, instr, store
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and r3, r0, #7 @ Get bit offset
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mov r2, #1
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add r1, r1, r0, lsr #3 @ Get byte offset
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mov r3, r2, lsl r3 @ create mask
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smp_dmb
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1: ldrexb r2, [r1]
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ands r0, r2, r3 @ save old value of bit
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\instr r2, r2, r3 @ toggle bit
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strexb ip, r2, [r1]
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cmp ip, #0
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bne 1b
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smp_dmb
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cmp r0, #0
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movne r0, #1
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2: mov pc, lr
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.endm
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#else
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.macro bitop, instr
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and r2, r0, #7
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mov r3, #1
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mov r3, r3, lsl r2
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save_and_disable_irqs ip
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ldrb r2, [r1, r0, lsr #3]
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\instr r2, r2, r3
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strb r2, [r1, r0, lsr #3]
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restore_irqs ip
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mov pc, lr
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.endm
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/**
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* testop - implement a test_and_xxx_bit operation.
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* @instr: operational instruction
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* @store: store instruction
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*
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* Note: we can trivially conditionalise the store instruction
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* to avoid dirtying the data cache.
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*/
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.macro testop, instr, store
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add r1, r1, r0, lsr #3
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and r3, r0, #7
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mov r0, #1
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save_and_disable_irqs ip
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ldrb r2, [r1]
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tst r2, r0, lsl r3
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\instr r2, r2, r0, lsl r3
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\store r2, [r1]
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restore_irqs ip
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moveq r0, #0
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mov pc, lr
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.endm
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#endif
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