Markos Chandras 02dc6bfb08 MIPS: mm: c-r4k: Detect instruction cache aliases ... The *Aptiv cores can use the CONF7/IAR bit to detect if the core has hardware support to remove instruction cache aliasing. This also defines the CONF7/AR bit in order to avoid using the '16' magic number. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6499/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>		2014-03-06 21:25:21 +01:00
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asm	MIPS: mm: c-r4k: Detect instruction cache aliases	2014-03-06 21:25:21 +01:00
uapi/asm	MIPS: Wire up sched_setattr/sched_getattr syscalls	2014-02-04 13:47:46 +01:00