2e0cea1dec
Use the generic IRQ framework Signed-off-by: Mikael Starvik <starvik@axis.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
160 lines
5.9 KiB
C
160 lines
5.9 KiB
C
/*
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* Interrupt handling assembler and defines for Linux/CRISv10
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*/
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#ifndef _ASM_ARCH_IRQ_H
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#define _ASM_ARCH_IRQ_H
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#include <asm/arch/sv_addr_ag.h>
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#define NR_IRQS 32
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/* The first vector number used for IRQs in v10 is really 0x20 */
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/* but all the code and constants are offseted to make 0 the first */
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#define FIRST_IRQ 0
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#define SOME_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, some) /* 0 ? */
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#define NMI_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, nmi) /* 1 */
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#define TIMER0_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, timer0) /* 2 */
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#define TIMER1_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, timer1) /* 3 */
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/* mio, ata, par0, scsi0 on 4 */
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/* par1, scsi1 on 5 */
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#define NETWORK_STATUS_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, network) /* 6 */
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#define SERIAL_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, serial) /* 8 */
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#define PA_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, pa) /* 11 */
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/* extdma0 and extdma1 is at irq 12 and 13 and/or same as dma5 and dma6 ? */
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#define EXTDMA0_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, ext_dma0)
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#define EXTDMA1_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, ext_dma1)
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/* dma0-9 is irq 16..25 */
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/* 16,17: network */
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#define DMA0_TX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma0)
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#define DMA1_RX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma1)
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#define NETWORK_DMA_TX_IRQ_NBR DMA0_TX_IRQ_NBR
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#define NETWORK_DMA_RX_IRQ_NBR DMA1_RX_IRQ_NBR
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/* 18,19: dma2 and dma3 shared by par0, scsi0, ser2 and ata */
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#define DMA2_TX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma2)
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#define DMA3_RX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma3)
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#define SER2_DMA_TX_IRQ_NBR DMA2_TX_IRQ_NBR
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#define SER2_DMA_RX_IRQ_NBR DMA3_RX_IRQ_NBR
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/* 20,21: dma4 and dma5 shared by par1, scsi1, ser3 and extdma0 */
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#define DMA4_TX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma4)
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#define DMA5_RX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma5)
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#define SER3_DMA_TX_IRQ_NBR DMA4_TX_IRQ_NBR
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#define SER3_DMA_RX_IRQ_NBR DMA5_RX_IRQ_NBR
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/* 22,23: dma6 and dma7 shared by ser0, extdma1 and mem2mem */
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#define DMA6_TX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma6)
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#define DMA7_RX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma7)
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#define SER0_DMA_TX_IRQ_NBR DMA6_TX_IRQ_NBR
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#define SER0_DMA_RX_IRQ_NBR DMA7_RX_IRQ_NBR
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#define MEM2MEM_DMA_TX_IRQ_NBR DMA6_TX_IRQ_NBR
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#define MEM2MEM_DMA_RX_IRQ_NBR DMA7_RX_IRQ_NBR
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/* 24,25: dma8 and dma9 shared by ser1 and usb */
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#define DMA8_TX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma8)
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#define DMA9_RX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma9)
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#define SER1_DMA_TX_IRQ_NBR DMA8_TX_IRQ_NBR
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#define SER1_DMA_RX_IRQ_NBR DMA9_RX_IRQ_NBR
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#define USB_DMA_TX_IRQ_NBR DMA8_TX_IRQ_NBR
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#define USB_DMA_RX_IRQ_NBR DMA9_RX_IRQ_NBR
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/* usb: controller at irq 31 + uses DMA8 and DMA9 */
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#define USB_HC_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, usb)
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/* our fine, global, etrax irq vector! the pointer lives in the head.S file. */
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typedef void (*irqvectptr)(void);
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struct etrax_interrupt_vector {
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irqvectptr v[256];
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};
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extern struct etrax_interrupt_vector *etrax_irv;
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void set_int_vector(int n, irqvectptr addr);
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void set_break_vector(int n, irqvectptr addr);
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#define __STR(x) #x
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#define STR(x) __STR(x)
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/* SAVE_ALL saves registers so they match pt_regs */
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#define SAVE_ALL \
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"move $irp,[$sp=$sp-16]\n\t" /* push instruction pointer and fake SBFS struct */ \
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"push $srp\n\t" /* push subroutine return pointer */ \
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"push $dccr\n\t" /* push condition codes */ \
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"push $mof\n\t" /* push multiply overflow reg */ \
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"di\n\t" /* need to disable irq's at this point */\
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"subq 14*4,$sp\n\t" /* make room for r0-r13 */ \
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"movem $r13,[$sp]\n\t" /* push the r0-r13 registers */ \
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"push $r10\n\t" /* push orig_r10 */ \
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"clear.d [$sp=$sp-4]\n\t" /* frametype - this is a normal stackframe */
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/* BLOCK_IRQ and UNBLOCK_IRQ do the same as mask_irq and unmask_irq */
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#define BLOCK_IRQ(mask,nr) \
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"move.d " #mask ",$r0\n\t" \
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"move.d $r0,[0xb00000d8]\n\t"
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#define UNBLOCK_IRQ(mask) \
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"move.d " #mask ",$r0\n\t" \
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"move.d $r0,[0xb00000dc]\n\t"
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#define IRQ_NAME2(nr) nr##_interrupt(void)
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#define IRQ_NAME(nr) IRQ_NAME2(IRQ##nr)
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#define sIRQ_NAME(nr) IRQ_NAME2(sIRQ##nr)
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#define BAD_IRQ_NAME(nr) IRQ_NAME2(bad_IRQ##nr)
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/* the asm IRQ handler makes sure the causing IRQ is blocked, then it calls
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* do_IRQ (with irq disabled still). after that it unblocks and jumps to
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* ret_from_intr (entry.S)
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*
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* The reason the IRQ is blocked is to allow an sti() before the handler which
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* will acknowledge the interrupt is run.
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*/
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#define BUILD_IRQ(nr,mask) \
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void IRQ_NAME(nr); \
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__asm__ ( \
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".text\n\t" \
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"IRQ" #nr "_interrupt:\n\t" \
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SAVE_ALL \
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BLOCK_IRQ(mask,nr) /* this must be done to prevent irq loops when we ei later */ \
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"moveq "#nr",$r10\n\t" \
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"move.d $sp,$r11\n\t" \
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"jsr do_IRQ\n\t" /* irq.c, r10 and r11 are arguments */ \
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UNBLOCK_IRQ(mask) \
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"moveq 0,$r9\n\t" /* make ret_from_intr realise we came from an irq */ \
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"jump ret_from_intr\n\t");
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/* This is subtle. The timer interrupt is crucial and it should not be disabled for
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* too long. However, if it had been a normal interrupt as per BUILD_IRQ, it would
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* have been BLOCK'ed, and then softirq's are run before we return here to UNBLOCK.
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* If the softirq's take too much time to run, the timer irq won't run and the
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* watchdog will kill us.
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*
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* Furthermore, if a lot of other irq's occur before we return here, the multiple_irq
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* handler is run and it prioritizes the timer interrupt. However if we had BLOCK'ed
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* it here, we would not get the multiple_irq at all.
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*
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* The non-blocking here is based on the knowledge that the timer interrupt is
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* registred as a fast interrupt (SA_INTERRUPT) so that we _know_ there will not
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* be an sti() before the timer irq handler is run to acknowledge the interrupt.
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*/
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#define BUILD_TIMER_IRQ(nr,mask) \
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void IRQ_NAME(nr); \
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__asm__ ( \
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".text\n\t" \
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"IRQ" #nr "_interrupt:\n\t" \
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SAVE_ALL \
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"moveq "#nr",$r10\n\t" \
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"move.d $sp,$r11\n\t" \
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"jsr do_IRQ\n\t" /* irq.c, r10 and r11 are arguments */ \
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"moveq 0,$r9\n\t" /* make ret_from_intr realise we came from an irq */ \
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"jump ret_from_intr\n\t");
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#endif
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