The wrong test was used, gpio is unsigned and it had an off-by-one.
Signed-off-by: Roel Kluin <roel.kluin@gmail.com>
Cc: Alek Du <alek.du@intel.com>
Cc: David Brownell <david-b@pacbell.net>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
- Remove wrong and unnecessary unmask operation
- Remove extra GEDR reading
This fixes the loss of interrupts which occurs when two or more pins are
triggered in close succession.
Signed-off-by: Alek Du <alek.du@intel.com>
Cc: David Brownell <david-b@pacbell.net>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
The Langwell chip is the IO hub for Intel Moorestown platform which has a
64-pin gpio block device inside. It is exposed as a dedicated PCI device.
We use it to control outside peripheral as well as to do IRQ demuxing.
The gpio block uses MSI to send level type interrupt to IOAPIC.
Signed-off-by: Alek Du <alek.du@intel.com>
Cc: David Brownell <david-b@pacbell.net>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
