3 commits

Author	SHA1	Message	Date
Geert Uytterhoeven	24e9c85c6e	soc: renesas: r8a77990-sysc: Fix initialization order of 3DG-{A,B} ... [ Upstream commit b0d7fbf8b174168c580bb310964c3c809e5569a9 ] The workaround for the wrong hierarchy of the 3DG-{A,B} power domains on R-Car E3 ES1.0 corrected the parent domains. However, the 3DG-{A,B} power domains were still initialized and powered in the wrong order, causing 3DG operation to fail. Fix this by changing the order in the table at runtime, when running on an affected SoC. Fixes: 086b399965 ("soc: renesas: r8a77990-sysc: Add workaround for 3DG-{A,B}") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Sasha Levin <sashal@kernel.org>	2019-12-13 08:52:29 +01:00
Yoshihiro Shimoda	086b399965	soc: renesas: r8a77990-sysc: Add workaround for 3DG-{A,B} ... This patch adds workaround for 3DG-{A,B} of R-Car E3 ES1.0 because the SoC has a restriction about the order. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>	2018-05-16 10:57:44 +02:00
Takeshi Kihara	44b12d4311	soc: renesas: rcar-sysc: Add support for R-Car E3 power areas ... This patch adds Cortex-A53 CPU{0,1}, Cortex-A53 SCU, Cortex-R7, A3VC, A2VC1 and 3DG-{A,B} power domain areas for the R8A77990 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> [shimoda: fix 3DG-{A,B} and add SPDX-License-Identifier] Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>	2018-05-16 10:57:13 +02:00