commit 9203d59 (ARM:mach-mx5/mx53_ard: Add I2C2 and I2C3 support) missed to include
the define for ARD_I2CPORTEXP_B.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
MX53 has five UART ports.
Add support for the missing UART4 and UART5 ports.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
It is not good to have cpu_name and to_version encoded into sdma
firmware name as variables. For example, there are three TOs of
imx51 soc, the sdma script never changes since TO1, which means
all three TOs of imx51 uses TO1 version of sdma script. But we
have to prepare three identical firmwares, sdma-imx51-to1.bin
sdma-imx51-to2.bin and sdma-imx51-to3.bin, to have the kernel
capable of running on all three TOs.
The patch removes cpu_name and to_version from sdma platform data,
and instead uses fw_name to pass the firmware name, so that we can
pass the TO version where it's relevant and skip it where only one
firmware exists.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The patch follows the implementation of gpio-mxc device registration
to break the concentrated imx-dma device registration into soc
specific setup function. Then we can avoid the churn of "#ifdef"
and the cpu_is_mx checking on such a long list, which makes no sense,
considering more soc supports need to be added and we need to support
single image for multiple socs in the long run.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
On mx27_3ds board there is a l4f00242t03 LCD that is controlled via CSPI1.
Add support for CSPI1 and LCD.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
On MX1, MX21 and MX27 each GPIO port has an address space of 256 bytes.
Fix the iosize for these platforms.
Tested on a mx27_3ds board that can boot fine after this change.
Cc: Shawn Guo <shawn.guo@freescale.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
It adds LED2 on mx28evk board as heartbeat trigger for diagnostic
purpose.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The patch adds following configurations to enable build of mx23evk
and mx28evk in defconfig.
CONFIG_MACH_MX23EVK
CONFIG_MACH_MX28EVK
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
On the i.MX SPI driver the chipselect pins can be of the following types:
- internal: when the chipselect pin is used as a dedicated CS pin of the CSPI controller
- GPIO: a generic GPIO can be used as a chipselect funtion
On the mx27_3ds the SPI2 chip select is a GPIO, so don't annotate 'internal' in the chip select
definition.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Use the standard gpio_to_irq function instead of a dedicated IRQ_GPIOx macro.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Place the UART gpio initialization inside the scb9328_init function as it is done on
other i.MX boards.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
As no flag is passed into UART0 platform data, pass NULL argument
when registering UART0.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
There are several occurences where MXC_INTERNAL_IRQ is
assumed to be the start of the gpio interrupts. It was never
meant this way. Replace these with gpio_to_irq.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Acked-by: Fabio Estevam <fabio.estevam@freescale.com>
We have a clocksource which renders CLOCK_TICK_RATE useless. Define
it to a bogus value to get rid of some ifdeffery.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This allows to move the led definition to .init.rodata.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Cc: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This gets rid of per machine struct platform_device definitions and allows
to move the platform data and led definition to .init.rodata.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This gets rid of per machine struct platform_device definitions and allows
to move the platform data and led definition to .init.rodata.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Instead of using gpio_request followed by gpio_direction_output use gpio_request_array
when requesting multiple pins.
Also fixed the location of the delay for the reset and make the BABBAGE_USB_PHY_RESET to toggle.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The USB PHY Reset GPIO can be configured in the same place as the other GPIOs.
While at it rename the pin as BABBAGE_USB_PHY_RESET to make clearer its purpose.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
", o" was used for ", 0"
", 17" was used for ", 7 | 0x10"
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The clock from which the I2C timing is derived is the ipg_perclk not ipg_clk.
I2C bus frequency was lower by a factor of ~8 due to the clock divider
calculation being based on 66.5MHz IPG clock while the bus actually
uses 8MHz ipg_perclk.
Kernel version: 3.0.0-rc2 branch 'imx-for-next' of git://git.pengutronix.de/git/imx/linux-2.6
Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The pins are actually used (not in mainline yet):
D4 -> SSP2_D0
D5 -> GPIO
D6 -> GPIO
D7 -> GPIO for owire
so their pinmapping for SSP0 is wrong.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
