Commit graph

219 commits

Author SHA1 Message Date
Chris Wilson
48b956c5a8 drm/i915: Push pipelining of display plane flushes to the caller
This ensures that we do wait upon the flushes to complete if necessary
and avoid the visual tears, whilst enabling pipelined page-flips.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-14 21:08:35 +01:00
Chris Wilson
7213342db5 drm/i915: Consolidate flushing the display plane
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-14 10:34:27 +01:00
Chris Wilson
b3b079dbef drm/i915: Reduce hangcheck frequency
By reducing the hangcheck frequency we check less often, conserving
resources, and still detect a lock up quickly. On a fast machine with a
slow GPU (like a Core2 paired with a 945G) it is easy for the hangcheck to
misfire as we check too fast.

Also once hung and if we fail to completely reset the chip, we have a
nasty habit of proclaming a hang many times a second and generating a
strobe-like display.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-14 10:30:10 +01:00
Chris Wilson
788319d48d drm/i915/lvds: Move private data to the connector from the device.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-13 10:27:41 +01:00
Chris Wilson
bed4a6734b drm/i915: Fix updating FBC
We need to track different state on each generation in order to detect
when we need to refresh the FBC registers.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-11 10:50:55 +01:00
Daniel Vetter
1996675432 drm/i915: die, i915_probe_agp, die
Use the detection from intel-gtt.ko instead. Hooray!

Also move the stolen mem allocator to the other gtt stuff in dev_prv->mem.

v2: Chris Wilson noted that my error handling was crap. Fix it. He also
said that this fixes a problem on his i845. Indeed, i915_probe_agp
misses a special case for i830/i845 stolen mem detection.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=25476
Cc: stable@kernel.org
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-08 21:20:21 +01:00
Daniel Vetter
0ade638655 intel-gtt: introduce drm/intel-gtt.h
Add a few definitions to it that are already shared and that will
be shared in the future (like the number of stolen entries).
No functional changes in here.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-08 21:20:07 +01:00
Chris Wilson
a957355693 drm/i915: Refactor panel backlight controls
There were two instances of code to control the panel backlight and
neither handled the complete set of device variations.

Fixes:

  Bug 29716 - [GM965] Regression: Backlight resets to minimum when changing resolution
  https://bugs.freedesktop.org/show_bug.cgi?id=29716

And a bug on one of my PineView boxes which overflowed the backlight
value.

Incorporates part of a similar patch by Matthew Garrett that exposes a
native Intel backlight controller.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-08 10:23:58 +01:00
Chris Wilson
de227ef090 drm/i915: Kill the active list spinlock
This spinlock only served debugging purposes in a time when we could not
be sure of the mutex ever being released upon a GPU hang. As we now
should be able rely on hangcheck to do the job for us (and that error
reporting should not itself require the struct mutex) we can kill the
incomplete attempt at protection.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-08 10:23:56 +01:00
Chris Wilson
3bd3c93299 drm/i915: Compile out error state without DEBUG_FS
Alexander reported that the compilation of intel_overlay.c was failing
due to an inclusion that was only valid with CONFIG_DEBUG_FS. As the
whole error reporting is only useful with debugfs enabled, remove all
the redundant error state collection code when compiling without
CONFIG_DEBUG_FS.

Reported-by: Alexander Lam <lambchop468@gmail.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-08 10:23:55 +01:00
Chris Wilson
8dc5d14741 drm/i915: Preallocate requests
By allocating the request prior to writing to the ringbuffer, we can
abort the operation without leaving the GPU in an inconsistent state.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2010-09-08 10:23:50 +01:00
Chris Wilson
31578148b2 drm/i915/overlay: Move capabilities bits to common info block.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2010-09-08 10:23:42 +01:00
Daniel Vetter
8a1a49f954 drm/i915: move flushing list processing to i915_retire_commands
... instead of threading flush_domains through the execbuf code to
i915_add_request.

With this change 2 small cleanups are possible (likewise the majority
of the patch):

- The flush_domains parameter of i915_add_request is always 0. Drop it
  and the corresponding logic.
- Ditto for the seqno param of i915_gem_process_flushing_list.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-08 10:23:36 +01:00
Daniel Vetter
a6910434e1 drm/i915: only one interrupt per batchbuffer is not enough!
Previously I thought that one interrupt per batchbuffer should be
enough. Now tedious benchmarking showed this to be wrong.

Therefore track whether any commands have been isssued with a future
seqno (like pipelined fencing changes or flushes). If this is the case
emit a request before issueing the batchbuffer.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-08 10:23:35 +01:00
Jesse Barnes
be282fd48e drm/i915: add MMIO debug output
Useful for capturing register read/write traces to send to the hw guys.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-08 10:23:33 +01:00
Chris Wilson
44834a67c0 drm/i915: Use the VBT from OpRegion when available (v3)
It is recommended that we use the Video BIOS tables that were copied
into the OpRegion during POST when initialising the driver. This saves
us from having to furtle around inside the ROM ourselves and possibly
allows the vBIOS to adjust the tables prior to initialisation.

On some systems, such as the Samsung N210, there is no accessible VBIOS
and the only means of finding the VBT is through the OpRegion.

v2: Rearrange the code so that ASLE is enabled along with ACPI
v3: Enable OpRegion parsing even without ACPI

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Matthew Garrett <mjg@redhat.com>
2010-09-08 10:13:32 +01:00
Chris Wilson
3b61796785 drm/i915: Rename i915_opregion.c to intel_opregion.c
It's part of the generic Intel driver infrastructure so rename it in
prepreparation for using it for VBT.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-08 10:13:31 +01:00
Daniel Vetter
75ef9da2cd drm/i915: unload: fix retire_work races
ums-gem code correctly cancels the retire work (at lastclose time),
kms does not do so. Fix this by canceling the work right after ideling
the gpu.

While staring at the code I noticed that the work function is not
static. Fix this, too.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-08 10:13:28 +01:00
Chris Wilson
c96c3a8cb7 drm/i915: Include a generation number in the device info
To simplify the IS_GEN[234] macros and to enable switching.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-07 11:13:00 +01:00
Zou Nan hai
aa40d6bbb9 drm/i915: Set up a render context on Ironlake
RC6 power state requires a logical render context in place for saving
render context.

Signed-off-by: Zou Nan hai <nanhai.zou@intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
2010-08-09 11:34:12 -07:00
Chris Wilson
6eeefaf3c8 drm/i915: Apply i830 errata for cursor alignment
i830 requires 32bpp cursors to be aligned to 16KB, so we have to expose
the alignment parameter to i915_gem_attach_phys_object().

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Eric Anholt <eric@anholt.net>
2010-08-09 11:24:36 -07:00
Chris Wilson
1d8e1c75ff drm/i915: Enable aspect/centering panel fitting for Ironlake.
v2: Hook in DP paths to keep FULLSCREEN panel fitting on eDP.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
2010-08-09 11:24:34 -07:00
Chris Wilson
cd377ea93f drm/i915: Implement fair lru eviction across both rings. (v2)
Based in a large part upon Daniel Vetter's implementation and adapted
for handling multiple rings in a single pass.

This should lead to better gtt usage and fixes the page-fault-of-doom
triggered. The fairness is provided by scanning through the GTT space
amalgamating space in rendering order. As soon as we have a contiguous
space in the GTT large enough for the new object (and its alignment),
evict any object which lies within that space. This should keep more
objects resident in the GTT.

Doing throughput testing on a PineView machine with cairo-perf-trace
indicates that there is very little difference with the new LRU scan,
perhaps a small improvement... Except oddly for the poppler trace.

Reference:

  Bug 15911 - Intermittent X crash (freeze)
  https://bugzilla.kernel.org/show_bug.cgi?id=15911

  Bug 20152 - cannot view JPG in firefox when running UXA
  https://bugs.freedesktop.org/show_bug.cgi?id=20152

  Bug 24369 - Hang when scrolling firefox page with window in front
  https://bugs.freedesktop.org/show_bug.cgi?id=24369

  Bug 28478 - Intermittent graphics lockups due to overflow/loop
  https://bugs.freedesktop.org/show_bug.cgi?id=28478

v2: Attempt to clarify the logic and order of eviction through the use
of comments and macros.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Daniel Vetter <daniel@ffwll.ch>
Signed-off-by: Eric Anholt <eric@anholt.net>
2010-08-09 11:24:32 -07:00
Chris Wilson
b47eb4a2b3 drm/i915: Move the eviction logic to its own file.
The eviction code is the gnarly underbelly of memory management, and is
clearer if kept separated from the normal domain management in GEM.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Eric Anholt <eric@anholt.net>
2010-08-09 11:24:32 -07:00
Chris Wilson
6f392d5486 drm/i915: Use a common seqno for all rings.
This will be used by the eviction logic to maintain fairness between the
rings.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Eric Anholt <eric@anholt.net>
2010-08-09 11:24:32 -07:00
Chris Wilson
6ef3d42780 drm/i915: Capture the overlay status upon a GPU hang.
v2: Add the interrupt status and address.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Eric Anholt <eric@anholt.net>
2010-08-09 11:24:31 -07:00
Chris Wilson
dbd7ac9661 drm/i915: Use an uncommon name for the local dev_priv in macros
Using dev_priv__ avoids sparse complaining about shadowed variables in
the *LP_RING() macros.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Eric Anholt <eric@anholt.net>
2010-08-09 11:24:31 -07:00
Chris Wilson
88f356b725 drm/i915: Only emit flushes on active rings.
This avoids the excess flush and requests on idle rings (and spamming
the debug log ;-)

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Eric Anholt <eric@anholt.net>
2010-08-09 11:24:29 -07:00
Chris Wilson
be72615bcf drm/i915: Repeat unbinding during free if interrupted (v6)
If during the freeing of an object the unbind is interrupted by a system
call, which is quite possible if we have outstanding GPU writes that
must be flushed, the unbind is silently aborted. This still leaves the
AGP region and backing pages allocated, and perhaps more importantly,
the object remains upon the various lists exposing us to memory
corruption.

I think this is the cause behind the use-after-free, such as

  Bug 15664 - Graphics hang and kernel backtrace when starting Azureus
              with Compiz enabled
  https://bugzilla.kernel.org/show_bug.cgi?id=15664

v2: Daniel Vetter reminded me that kernel space programming is never easy.
We cannot simply spin to clear the pending signal and so must deferred
the freeing of the object until later.
v3: Run from the top level retire requests.
v4: Tested with P(return -ERESTARTSYS)=.5 from i915_gem_do_wait_request()
v5: Rebase against Eric's for-linus tree.
v6: Refactor, split and add a comment about avoiding unbounded recursion.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Daniel Vetter <daniel@ffwll.ch>
Signed-off-by: Eric Anholt <eric@anholt.net>
2010-08-01 19:53:24 -07:00
Chris Wilson
b09a1feca6 drm/i915: Refactor i915_gem_retire_requests()
Combine the iteration over active render rings into a common function.
This is in preparation for reusing the idle function to also retire
deferred free requests.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Eric Anholt <eric@anholt.net>
2010-08-01 19:52:57 -07:00
Eric Anholt
2bd34f6ca8 Merge remote branch 'origin/master' into drm-intel-next
This resolves the conflict in the EDP code, which has been rather
popular to hack on recently.

Conflicts:
	drivers/gpu/drm/i915/intel_dp.c
2010-08-01 19:34:47 -07:00
Chris Wilson
534843dabf drm/i915: Use 128k alignment for untiled display surface on i965 (v2)
The original i965, including the revised G35 and Q35, requires an
alignment of 128K for the display surface with linear memory, so
increase the requirement from 64k for these chipsets. For the later
chipsets in the i965 family, only a 4k alignment is required. (So
long as we do not start performing asynchronous flips.)

Note the impact of this should be slight as on i965 we should be using a
tiled frontbuffer for anything up to a 4096x4096 display.

v2: compilation fixes and note that the docs do not exclude the G35 from
the extra alignment.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
2010-08-01 19:03:47 -07:00
Chris Wilson
cbb465e72a drm/i915: Include instdone[1] in hangcheck
References:

  Bug 26691 - Spurious hangcheck whilst executing a long shader over a
              large vertex buffer
  https://bugs.freedesktop.org/show_bug.cgi?id=26691

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Eric Anholt <eric@anholt.net>
2010-08-01 19:03:46 -07:00
Chris Wilson
d312ec2517 drm/i915: Sparse warns about the incorrect sign for storing bit17
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Eric Anholt <eric@anholt.net>
2010-08-01 19:03:45 -07:00
Chris Wilson
11824e8c4e drm/i915: Silence sparse complaints over insufficient bitfield int types.
drivers/gpu/drm/i915/i915_drv.h|676 col 19| warning: dubious bitfield without explicit `signed' or `unsigned'
drivers/gpu/drm/i915/i915_drv.h|712 col 19| warning: dubious bitfield without explicit `signed' or `unsigned'

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Eric Anholt <eric@anholt.net>
2010-08-01 19:03:45 -07:00
Chris Wilson
2dafb1e082 drm/i915: Propagate error from i915_gem_object_flush_gpu_write_domain()
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Eric Anholt <eric@anholt.net>
2010-08-01 19:03:44 -07:00
Zhao Yakui
b52eb4dcab drm/i915: Add frame buffer compression support on Ironlake mobile
About 0.2W power can be saved on one HP laptop.

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
2010-08-01 19:03:44 -07:00
Zhao Yakui
fa143215b1 drm/i915: Fix watermark calculation in self-refresh mode
For self-refresh mode WM calculation's "line time" should use
mode's htotal instead of hdisplay. "surface width" is the hdisplay
for display plane and 64 for cursor plane.

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
2010-08-01 19:03:43 -07:00
Jesse Barnes
b690e96cf9 drm/i915: add pipe A force quirks to i915 driver
Ported over from the old UMS list.  Unfortunately they're still
necessary especially on older laptop platforms.

Fixes https://bugs.freedesktop.org/show_bug.cgi?id=22126.

Tested-by: Xavier <shiningxc@gmail.com>
Tested-by: Diego Escalante Urrelo <diegoe@gnome.org>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
2010-07-26 12:00:43 -07:00
Jesse Barnes
9c928d168d drm/i915: disable FBC when more than one pipe is active
We're really supposed to do this to avoid trouble with underflows when
multiple planes are active.

Fixes https://bugs.freedesktop.org/show_bug.cgi?id=26987.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Tested-by: fangxun <xunx.fang@intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
2010-07-26 11:27:06 -07:00
Linus Torvalds
97e0214044 Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/anholt/drm-intel
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/anholt/drm-intel:
  drm/i915: fix page flip finish vs. prepare on plane B
  drm/i915: change default panel fitting mode to preserve aspect ratio
  drm/i915: fix uninitialized variable warning in i915_setup_compression()
  drm/i915: take struct_mutex in i915_dma_cleanup()
  drm/i915: Fix CRT hotplug regression in 2.6.35-rc1
  i915: fix ironlake edp panel setup (v4)
  drm/i915: don't access FW_BLC_SELF on 965G
  drm/i915: Account for space on the ring buffer consumed whilst wrapping.
  drm/i915: gen3 page flipping fixes
  drm/i915: don't queue flips during a flip pending event
  drm/i915: Fix incorrect intel_ring_begin size in BSD ringbuffer.
  drm/i915: Turn on 945 self-refresh only if single CRTC is active
  drm/i915/gen4: Fix interrupt setup ordering
  drm/i915: Use RSEN instead of HTPLG for tfp410 monitor detection.
  drm/i915: Move non-phys cursors into the GTT
  Revert "drm/i915: Don't enable pipe/plane/VCO early (wait for DPMS on)."

(Included the "fix page flip finish vs.  prepare on plane B" patch from
Jesse on top of the pull request from Eric.   -- Linus)
2010-07-01 18:48:11 -07:00
Jesse Barnes
1afe3e9d43 drm/i915: gen3 page flipping fixes
Gen3 chips have slightly different flip commands, and also contain a bit
that indicates whether a "flip pending" interrupt means the flip has
been queued or has been completed.

So implement support for the gen3 flip command, and make sure we use the
flip pending interrupt correctly depending on the value of ECOSKPD bit
0.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
2010-06-18 17:59:53 -07:00
Zou Nan hai
be26a10bd1 drm/i915: Fix incorrect intel_ring_begin size in BSD ringbuffer.
The ring_begin API was taking a number of bytes, while all of our
other begin/end macros take number of dwords.  Change the API over to
dwords to prevent future bugs.

Signed-off-by: Zou Nan hai <nanhai.zou@intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
2010-06-14 18:26:25 -07:00
Dave Airlie
a3524f1b27 drm/i915: fix oops on single crtc devices.
(regression fix since fbdev/kms rework).

My fb rework didn't remember about the 84/65s.

Reported-by: Ondrej Zary <linux@rainbow-software.org>
Tested-by: Ondrej Zary <linux@rainbow-software.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2010-06-08 09:31:16 +10:00
Eric Anholt
e20f9c64c7 drm/i915: Clean up leftover bits from hws move to ring structure.
Fixes /debug/dri/0/i915_gem_interrupt output for status page.

Signed-off-by: Eric Anholt <eric@anholt.net>
2010-05-26 14:51:47 -07:00
Li Peng
9553426372 drm/i915: Add CxSR support on Pineview DDR3
Pineview with DDR3 memory has different latencies to enable CxSR.
This patch updates CxSR latency table to add Pineview DDR3 latency
configuration. It also adds one flag "is_ddr3" for checking DDR3
setting in MCHBAR.

Cc: Shaohua Li <shaohua.li@intel.com>
Cc: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Li Peng <peng.li@intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
2010-05-26 14:22:51 -07:00
Daniel Vetter
778c35444f drm/i915: combine all small integers into one single bitfield
This saves a whooping 7 dwords. Zero functional changes. Because
some of the refcounts are rather tightly calculated, I've put
BUG_ONs in the code to check for overflows.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Eric Anholt <eric@anholt.net>
2010-05-26 14:13:36 -07:00
Jesse Barnes
7648fa99eb drm/i915: add power monitoring support
Add power monitoring support to the i915 driver for use by the IPS
driver.  Export the available power info to the IPS driver through a few
new inter-driver hooks.  When used together, the IPS driver and this
patch can significantly increase graphics performance on Ironlake class
chips.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
[anholt: Fixed 32-bit compile.  stupid obfuscating div_u64()]
Signed-off-by: Eric Anholt <eric@anholt.net>
2010-05-26 14:10:01 -07:00
Zou Nan hai
d1b851fc0d drm/i915: implement BSD ring buffer V2
The BSD (bit stream decoder) ring is used for accessing the BSD engine
which decodes video bitstream for H.264 and VC1 on G45+.  It is
asynchronous with the render ring and has access to separate parts of
the GPU from it, though the render cache is coherent between the two.

Signed-off-by: Zou Nan hai <nanhai.zou@intel.com>
Signed-off-by: Xiang Hai hao <haihao.xiang@intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
2010-05-26 13:46:58 -07:00
Zou Nan hai
852835f343 drm/i915: convert some gem structures to per-ring V2
The active list and request list move into the ringbuffer structure,
so each can track its active objects in the order they are in that
ring.  The flushing list does not, as it doesn't matter which ring
caused data to end up in the render cache.  Objects gain a pointer to
the ring they are active on (if any).

Signed-off-by: Zou Nan hai <nanhai.zou@intel.com>
Signed-off-by: Xiang Hai hao <haihao.xiang@intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
2010-05-26 13:42:11 -07:00