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4 commits

Author SHA1 Message Date
Jean-Christophe PLAGNIOL-VILLARD
f363c407b4 ARM: at91: make sdram/ddr register base soc independent
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
2012-02-23 14:57:56 +01:00
Jean-Christophe PLAGNIOL-VILLARD
9918ceafd4 ARM: at91: code removal of CAP9 SoC
Following removal announce and addition to feature-removal-schedule.txt,
here is the actual source code deletion for Atmel CAP9 family.

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
2012-02-03 13:33:05 +01:00
Jean-Christophe PLAGNIOL-VILLARD
17d2cc25f0 ARM: at91: merge at91cap9_ddrsdr.h in at91sam9_ddrsdr.h
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
2012-01-20 17:20:23 +01:00
Nicolas Ferre
7dca3343fc ARM: 6185/1: AT91: PM: dual ram controller support
This rework allows to address tow memory controllers. AT91SAM9263 and
AT91SAM9G45 family have tow SDRAM or DDR/SDRAM controllers. Power management
should take care of this.
This patch modify the way RAM IP header files are implemented to allow
access to registers of both controllers ; it also adds some macros.

We also modify the power management files to use those modified header files.
Slow clock (assembly) and regular power management functions are synchronized
for setting of RAM self-refresh procedure:
(lpr & ~AT91_DDRSDRC_LPCB) | AT91_DDRSDRC_LPCB_SELF_REFRESH

Note that AT91RM9200 is not impacted by this modification.

Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Acked-by: Andrew Victor <linux@maxim.org.za>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-07-09 12:31:50 +01:00