Enable config for SPMI TEMP ALARM driver for SPF targets
to be able to read temperature of temp alarm sensor.
Change-Id: If704bf800d79d06f070e63178748ac759af513e2
Signed-off-by: Archana Sriram <apsrir@codeaurora.org>
Enable all the coresight configs required for the ETR
functionality.
Change-Id: Ieccc48c5999fb1142265829c87b797853eb50c1b
Signed-off-by: Shilpa Suresh <sbsure@codeaurora.org>
For MSM8937_64 targets, add PMIC configs related to
charging, vibrator and rtc.
Change-Id: I2891118f051ff9697aafcfa394940e1765fba2e4
Signed-off-by: Shilpa Suresh <sbsure@codeaurora.org>
Enable configs for ADC_TM and SPMI VADC, ADC5 drivers for
SPF targets for 32, 32Go and 64 bit variants.
Change-Id: Ic75dbe6fcafb1e4d2a49bbe87439fde4351b1218
Signed-off-by: Archana Sriram <apsrir@codeaurora.org>
Signed-off-by: Manjunatha Madana <mamanj@codeaurora.org>
* These have all moved into the ramdisk, and boot devices
has gone to the kernel commandline.
Bug: 117933812
Change-Id: I0d06607c522c08f50484b9eff4dc78b21cc083f5
* Similar to what I've done on other devices, revert
to normal grace periods to reduce power usage.
* Expedited RCU hammers CPUs with IPIs to reduce grace
period durations and thus RCU latency, but that disrupts
busy CPUs and causes unnecessary wakeups while providing
little to no improvement in real-world performance.
Change-Id: I2b55e4aaa82bb670dfd6fb417b05fe9ae685e0a8
* Our kernel only runs on known systems where broken
IRQs would already have been discovered, so disable
this to reduce overhead in the IRQ handling path.
Change-Id: Ia9e655dc9891f9cb94a6123ceaec43ba7c5fd5b1
Set the wakeup timeout for qrtr to 500 ms for lito. This change
will help ensure the TUI client thread gets a chance to run before
the system is suspended again.
Change-Id: I8c8831995bf58fc39a3e8c107d0fd761745bbfed
Signed-off-by: Sarannya S <sarannya@codeaurora.org>
Enable RPM SMD cooling device driver for KHAJE. It monitors
device temperature and request different temperature band levels
to RPM hardware.
Change-Id: Ia0c4deed12ee94f8fa0a6e98950e0654576740e1
Signed-off-by: Gopala Krishna Nuthaki <gnuthaki@codeaurora.org>
ARM erratum 1188873 can cause very severe issues if left unmitigated on
affected cores. However, if unrelated ARM arch timer mitigations are
disabled (e.g. Freescale, Hisilicon, and Cortex-A73 errata), the
mitigation for 1188873 will no longer be applied even if the config
option is on. This is because this mitigation is implemented as a
generic OOL erratum workaround, and disabling other mitigations will
cause the OOL workaround framework to stop being compiled.
Add an explicit dependency on the workaround framework to fix this, and
also add a dependency on ARM_ARCH_TIMER while we're at it.
On Android, leaving this erratum causes the AlarmManager thread in
system_server to use 100% CPU in the background after 20 minutes of
screen-off idle. The CPU hogging never stops until sytem_server is
killed and sometimes also causes system_server crashes due to invalid
negative durations in batterystats resulting from the corrupted timer
values.
Test: Let device idle for 20 minutes and check AlarmManager CPU usage
Signed-off-by: Danny Lin <danny@kdrag0n.dev>
The fix for ARM erratum 1188873 is the only configurable one in use.
Disable the rest.
Signed-off-by: Sultan Alsawaf <sultan@kerneltoast.com>
Signed-off-by: Gagan Malvi <malvigagan@gmail.com>
On a Kryo 485 CPU (semi-custom Cortex-A76 derivative) in a Snapdragon
855 (SM8150) SoC, switching from traditional LL/SC atomics to LSE
causes LKDTM's ATOMIC_TIMING test to regress by 2x:
LL/SC ATOMIC_TIMING: 34.14s 34.08s
LSE ATOMIC_TIMING: 70.84s 71.06s
Prefetching the target operands fixes the regression and makes LSE
perform better than LSE as expected:
LSE+prfm ATOMIC_TIMING: 21.36s 21.21s
"dd if=/dev/zero of=/dev/null count=10000000" also runs faster:
LL/SC: 3.3 3.2 3.3 s
LSE: 3.1 3.2 3.2 s
LSE+p: 2.3 2.3 2.3 s
Commit 0ea366f5e1 applied the same change
to LL/SC atomics, but it was never ported to LSE.
Signed-off-by: Danny Lin <danny@kdrag0n.dev>
This adds support to arm64 for fast refcount checking, as contributed
by Kees for x86 based on the implementation by grsecurity/PaX.
The general approach is identical: the existing atomic_t helpers are
cloned for refcount_t, with the arithmetic instruction modified to set
the PSTATE flags, and one or two branch instructions added that jump to
an out of line handler if overflow, decrement to zero or increment from
zero are detected.
One complication that we have to deal with on arm64 is the fact that
it has two atomics implementations: the original LL/SC implementation
using load/store exclusive loops, and the newer LSE one that does mostly
the same in a single instruction. So we need to clone some parts of
both for the refcount handlers, but we also need to deal with the way
LSE builds fall back to LL/SC at runtime if the hardware does not
support it.
As is the case with the x86 version, the performance gain is substantial
(ThunderX2 @ 2.2 GHz, using LSE), even though the arm64 implementation
incorporates an add-from-zero check as well:
perf stat -B -- echo ATOMIC_TIMING >/sys/kernel/debug/provoke-crash/DIRECT
116252672661 cycles # 2.207 GHz
52.689793525 seconds time elapsed
perf stat -B -- echo REFCOUNT_TIMING >/sys/kernel/debug/provoke-crash/DIRECT
127060259162 cycles # 2.207 GHz
57.243690077 seconds time elapsed
For comparison, the numbers below were captured using CONFIG_REFCOUNT_FULL,
which uses the validation routines implemented in C using cmpxchg():
perf stat -B -- echo REFCOUNT_TIMING >/sys/kernel/debug/provoke-crash/DIRECT
Performance counter stats for 'cat /dev/fd/63':
191057942484 cycles # 2.207 GHz
86.568269904 seconds time elapsed
As a bonus, this code has been found to perform significantly better on
systems with many CPUs, due to the fact that it no longer relies on the
load/compare-and-swap combo performed in a tight loop, which is what we
emit for cmpxchg() on arm64.
Cc: Will Deacon <will.deacon@arm.com>
Cc: Jayachandran Chandrasekharan Nair <jnair@marvell.com>,
Cc: Kees Cook <keescook@chromium.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>,
Cc: Jan Glauber <jglauber@cavium.com>,
Cc: Linus Torvalds <torvalds@linux-foundation.org>,
Cc: Hanjun Guo <guohanjun@huawei.com>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
[kdrag0n]
- Backported to k4.14 from:
https://www.spinics.net/lists/arm-kernel/msg735992.html
- Forward-ported to k4.19
- Benchmarked on sm8150 using perf and LKDTM REFCOUNT_TIMING:
https://docs.google.com/spreadsheets/d/14CctCmWzQAGhOmpHrBJfXQy_HuNFTpEkMEYSUGKOZR8/edit
| Fast checking | Generic checking
---------+--------------------+-----------------------
Cycles | 79235532616 | 102554062037
| 79391767237 | 99625955749
Time | 32.99879212 sec | 42.5354029 sec
| 32.97133254 sec | 41.31902045 sec
Average:
Cycles | 79313649927 | 101090008893
Time | 33 sec | 42 sec
Signed-off-by: Danny Lin <danny@kdrag0n.dev>
Mixing kernel and user debug hooks together is highly error-prone as it
relies on all of the hooks to figure out whether the exception came from
kernel or user, and then to act accordingly.
Make our debug hook code a little more robust by maintaining separate
hook lists for user and kernel, with separate registration functions
to force callers to be explicit about the exception levels that they
care about.
Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
[kdrag0n: Ported to android-4.19 with adaptations for KASAN hook]
Signed-off-by: Danny Lin <danny@kdrag0n.dev>
This matches the ULPS timeout used in msm_drm, which is defined as 58 ms
by IDLE_POWERCOLLAPSE_DURATION. No need to keep the GPU running after
the display enters a low-power state.
Signed-off-by: Sultan Alsawaf <sultan@kerneltoast.com>
Signed-off-by: alk3pInjection <webmaster@raspii.tech>
Signed-off-by: dreamisbaka <jolinux.g@gmail.com>
Change-Id: I465a6aca32b6cded284fbcebf0dd0c52f2d7732d
Signed-off-by: starlight5234 <starlight5234@protonmail.ch>
Userspace reads /proc/config.gz and spits out an error message after boot
finishes when it doesn't like the kernel's configuration. In order to
preserve our freedom to customize the kernel however we'd like, show
userspace the stock defconfig so that it never complains about our
kernel configuration.
Signed-off-by: Sultan Alsawaf <sultanxda@gmail.com>
lime-r-oss defconfig from kernel 4.19.113-perf Redmi 9 Power A11 Miui
Signed-off-by: Carlos Jimenez (JavaShin-X) <javashin1986@gmail.com>
Change-Id: Ibbe0a7d8d34298369a5e939882984fe882786767
Signed-off-by: starlight5234 <starlight5234@protonmail.ch>
