ath9k: Fix rd_ext EEPROM capability for AR9285
AR9285 chipsets have a different EEPROM layout, handle this appropriately when populating the rd_ext capability. Signed-off-by: Sujith <Sujith.Manoharan@atheros.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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2 changed files with 14 additions and 1 deletions
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@ -78,6 +78,18 @@
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#define INCREASE_MAXPOW_BY_TWO_CHAIN 6 /* 10*log10(2)*2 */
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#define INCREASE_MAXPOW_BY_THREE_CHAIN 10 /* 10*log10(3)*2 */
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/*
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* For AR9285 and later chipsets, the following bits are not being programmed
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* in EEPROM and so need to be enabled always.
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*
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* Bit 0: en_fcc_mid
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* Bit 1: en_jap_mid
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* Bit 2: en_fcc_dfs_ht40
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* Bit 3: en_jap_ht40
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* Bit 4: en_jap_dfs_ht40
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*/
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#define AR9285_RDEXT_DEFAULT 0x1F
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#define AR_EEPROM_MAC(i) (0x1d+(i))
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#define ATH9K_POW_SM(_r, _s) (((_r) & 0x3f) << (_s))
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#define FREQ2FBIN(x, y) ((y) ? ((x) - 2300) : (((x) - 4800) / 5))
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@ -3128,10 +3128,11 @@ bool ath9k_hw_fill_cap_info(struct ath_hw *ah)
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u16 capField = 0, eeval;
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eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
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ah->regulatory.current_rd = eeval;
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eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
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if (AR_SREV_9285_10_OR_LATER(ah))
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eeval |= AR9285_RDEXT_DEFAULT;
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ah->regulatory.current_rd_ext = eeval;
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capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
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