iwlagn: remove dereferences of priv from transport
There are still quite a few, but much less. A few fields have been moved /copied to hw_params which sits in the shared area: * priv->cfg->base_params->num_of_ampdu_queues * priv->cfg->base_params->shadow_reg_enable * priv->cfg->sku * priv->ucode_owner Signed-off-by: Emmanuel Grumbach <emmanuel.grumbach@intel.com> Signed-off-by: Wey-Yi Guy <wey-yi.w.guy@intel.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
parent
5f85a7890c
commit
fd656935cd
10 changed files with 64 additions and 58 deletions
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@ -102,12 +102,12 @@ static int iwlagn_txq_agg_enable(struct iwl_priv *priv, int txq_id, int sta_id,
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{
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if ((IWLAGN_FIRST_AMPDU_QUEUE > txq_id) ||
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(IWLAGN_FIRST_AMPDU_QUEUE +
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priv->cfg->base_params->num_of_ampdu_queues <= txq_id)) {
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hw_params(priv).num_ampdu_queues <= txq_id)) {
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IWL_WARN(priv,
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"queue number out of range: %d, must be %d to %d\n",
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txq_id, IWLAGN_FIRST_AMPDU_QUEUE,
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IWLAGN_FIRST_AMPDU_QUEUE +
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priv->cfg->base_params->num_of_ampdu_queues - 1);
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hw_params(priv).num_ampdu_queues - 1);
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return -EINVAL;
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}
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@ -3207,6 +3207,13 @@ static int iwl_set_hw_params(struct iwl_priv *priv)
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if (iwlagn_mod_params.disable_11n)
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priv->cfg->sku &= ~EEPROM_SKU_CAP_11N_ENABLE;
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hw_params(priv).num_ampdu_queues =
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priv->cfg->base_params->num_of_ampdu_queues;
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hw_params(priv).shadow_reg_enable =
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priv->cfg->base_params->shadow_reg_enable;
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hw_params(priv).sku =
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priv->cfg->sku;
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/* Device-specific setup */
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return priv->cfg->lib->set_hw_params(priv);
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}
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@ -1056,10 +1056,6 @@ struct iwl_testmode_trace {
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};
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#endif
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/* uCode ownership */
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#define IWL_OWNERSHIP_DRIVER 0
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#define IWL_OWNERSHIP_TM 1
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struct iwl_priv {
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/*data shared among all the driver's layers */
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@ -1147,9 +1143,6 @@ struct iwl_priv {
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u32 ucode_ver; /* version of ucode, copy of
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iwl_ucode.ver */
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/* uCode owner: default: IWL_OWNERSHIP_DRIVER */
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u8 ucode_owner;
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struct fw_img ucode_rt;
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struct fw_img ucode_init;
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struct fw_img ucode_wowlan;
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@ -215,7 +215,7 @@ static void iwl_static_sleep_cmd(struct iwl_priv *priv,
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else
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cmd->flags &= ~IWL_POWER_SLEEP_OVER_DTIM_MSK;
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if (priv->cfg->base_params->shadow_reg_enable)
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if (hw_params(priv).shadow_reg_enable)
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cmd->flags |= IWL_POWER_SHADOW_REG_ENA;
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else
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cmd->flags &= ~IWL_POWER_SHADOW_REG_ENA;
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@ -301,7 +301,7 @@ static void iwl_power_fill_sleep_cmd(struct iwl_priv *priv,
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if (priv->power_data.bus_pm)
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cmd->flags |= IWL_POWER_PCI_PM_MSK;
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if (priv->cfg->base_params->shadow_reg_enable)
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if (hw_params(priv).shadow_reg_enable)
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cmd->flags |= IWL_POWER_SHADOW_REG_ENA;
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else
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cmd->flags &= ~IWL_POWER_SHADOW_REG_ENA;
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@ -133,36 +133,41 @@ struct iwl_mod_params {
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/**
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* struct iwl_hw_params
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* @max_txq_num: Max # Tx queues supported
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* @num_ampdu_queues: num of ampdu queues
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* @tx/rx_chains_num: Number of TX/RX chains
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* @valid_tx/rx_ant: usable antennas
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* @rx_page_order: Rx buffer page order
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* @rx_wrt_ptr_reg: FH{39}_RSCSR_CHNL0_WPTR
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* @max_stations:
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* @ht40_channel: is 40MHz width possible in band 2.4
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* @beacon_time_tsf_bits: number of valid tsf bits for beacon time
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* @sku:
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* @rx_page_order: Rx buffer page order
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* @rx_wrt_ptr_reg: FH{39}_RSCSR_CHNL0_WPTR
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* BIT(IEEE80211_BAND_5GHZ) BIT(IEEE80211_BAND_5GHZ)
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* @sw_crypto: 0 for hw, 1 for sw
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* @max_xxx_size: for ucode uses
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* @ct_kill_threshold: temperature threshold
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* @beacon_time_tsf_bits: number of valid tsf bits for beacon time
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* @calib_init_cfg: setup initial calibrations for the hw
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* @calib_rt_cfg: setup runtime calibrations for the hw
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* @struct iwl_sensitivity_ranges: range of sensitivity values
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*/
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struct iwl_hw_params {
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u8 max_txq_num;
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u8 max_txq_num;
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u8 num_ampdu_queues;
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u8 tx_chains_num;
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u8 rx_chains_num;
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u8 valid_tx_ant;
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u8 valid_rx_ant;
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u32 rx_page_order;
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u8 max_stations;
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u8 ht40_channel;
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bool shadow_reg_enable;
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u16 beacon_time_tsf_bits;
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u16 sku;
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u32 rx_page_order;
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u32 max_inst_size;
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u32 max_data_size;
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u32 ct_kill_threshold; /* value in hw-dependent units */
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u32 ct_kill_exit_threshold; /* value in hw-dependent units */
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/* for 1000, 6000 series and up */
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u16 beacon_time_tsf_bits;
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u32 calib_init_cfg;
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u32 calib_rt_cfg;
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const struct iwl_sensitivity_ranges *sens;
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@ -201,6 +206,7 @@ struct iwl_tid_data {
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*
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* @dbg_level_dev: dbg level set per device. Prevails on
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* iwlagn_mod_params.debug_level if set (!= 0)
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* @ucode_owner: IWL_OWNERSHIP_*
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* @cmd_queue: command queue number
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* @status: STATUS_*
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* @bus: pointer to the bus layer data
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@ -217,6 +223,9 @@ struct iwl_shared {
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u32 dbg_level_dev;
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#endif /* CONFIG_IWLWIFI_DEBUG */
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#define IWL_OWNERSHIP_DRIVER 0
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#define IWL_OWNERSHIP_TM 1
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u8 ucode_owner;
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u8 cmd_queue;
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unsigned long status;
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bool wowlan;
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@ -612,7 +612,7 @@ static int iwl_testmode_ownership(struct ieee80211_hw *hw, struct nlattr **tb)
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owner = nla_get_u8(tb[IWL_TM_ATTR_UCODE_OWNER]);
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if ((owner == IWL_OWNERSHIP_DRIVER) || (owner == IWL_OWNERSHIP_TM))
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priv->ucode_owner = owner;
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priv->shrd->ucode_owner = owner;
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else {
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IWL_DEBUG_INFO(priv, "Invalid owner\n");
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return -EINVAL;
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@ -162,7 +162,8 @@ irqreturn_t iwl_isr_ict(int irq, void *data);
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/*****************************************************
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* TX / HCMD
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******************************************************/
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void iwl_txq_update_write_ptr(struct iwl_priv *priv, struct iwl_tx_queue *txq);
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void iwl_txq_update_write_ptr(struct iwl_trans *trans,
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struct iwl_tx_queue *txq);
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int iwlagn_txq_attach_buf_to_tfd(struct iwl_trans *trans,
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struct iwl_tx_queue *txq,
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dma_addr_t addr, u16 len, u8 reset);
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@ -130,7 +130,6 @@ static int iwl_rx_queue_space(const struct iwl_rx_queue *q)
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void iwl_rx_queue_update_write_ptr(struct iwl_trans *trans,
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struct iwl_rx_queue *q)
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{
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struct iwl_priv *priv = priv(trans);
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unsigned long flags;
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u32 reg;
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@ -139,34 +138,34 @@ void iwl_rx_queue_update_write_ptr(struct iwl_trans *trans,
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if (q->need_update == 0)
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goto exit_unlock;
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if (priv->cfg->base_params->shadow_reg_enable) {
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if (hw_params(trans).shadow_reg_enable) {
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/* shadow register enabled */
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/* Device expects a multiple of 8 */
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q->write_actual = (q->write & ~0x7);
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iwl_write32(bus(priv), FH_RSCSR_CHNL0_WPTR, q->write_actual);
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iwl_write32(bus(trans), FH_RSCSR_CHNL0_WPTR, q->write_actual);
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} else {
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/* If power-saving is in use, make sure device is awake */
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if (test_bit(STATUS_POWER_PMI, &trans->shrd->status)) {
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reg = iwl_read32(bus(priv), CSR_UCODE_DRV_GP1);
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reg = iwl_read32(bus(trans), CSR_UCODE_DRV_GP1);
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if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
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IWL_DEBUG_INFO(trans,
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"Rx queue requesting wakeup,"
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" GP1 = 0x%x\n", reg);
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iwl_set_bit(bus(priv), CSR_GP_CNTRL,
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iwl_set_bit(bus(trans), CSR_GP_CNTRL,
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CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
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goto exit_unlock;
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}
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q->write_actual = (q->write & ~0x7);
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iwl_write_direct32(bus(priv), FH_RSCSR_CHNL0_WPTR,
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iwl_write_direct32(bus(trans), FH_RSCSR_CHNL0_WPTR,
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q->write_actual);
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/* Else device is assumed to be awake */
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} else {
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/* Device expects a multiple of 8 */
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q->write_actual = (q->write & ~0x7);
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iwl_write_direct32(bus(priv), FH_RSCSR_CHNL0_WPTR,
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iwl_write_direct32(bus(trans), FH_RSCSR_CHNL0_WPTR,
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q->write_actual);
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}
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}
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@ -1032,7 +1031,7 @@ void iwl_irq_tasklet(struct iwl_trans *trans)
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IWL_DEBUG_ISR(trans, "Wakeup interrupt\n");
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iwl_rx_queue_update_write_ptr(trans, &trans_pcie->rxq);
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for (i = 0; i < hw_params(trans).max_txq_num; i++)
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iwl_txq_update_write_ptr(priv(trans),
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iwl_txq_update_write_ptr(trans,
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&priv(trans)->txq[i]);
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isr_stats->wakeup++;
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@ -86,7 +86,7 @@ void iwl_trans_txq_update_byte_cnt_tbl(struct iwl_trans *trans,
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/**
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* iwl_txq_update_write_ptr - Send new write index to hardware
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*/
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void iwl_txq_update_write_ptr(struct iwl_priv *priv, struct iwl_tx_queue *txq)
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void iwl_txq_update_write_ptr(struct iwl_trans *trans, struct iwl_tx_queue *txq)
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{
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u32 reg = 0;
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int txq_id = txq->q.id;
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@ -94,28 +94,28 @@ void iwl_txq_update_write_ptr(struct iwl_priv *priv, struct iwl_tx_queue *txq)
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if (txq->need_update == 0)
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return;
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if (priv->cfg->base_params->shadow_reg_enable) {
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if (hw_params(trans).shadow_reg_enable) {
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/* shadow register enabled */
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iwl_write32(bus(priv), HBUS_TARG_WRPTR,
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iwl_write32(bus(trans), HBUS_TARG_WRPTR,
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txq->q.write_ptr | (txq_id << 8));
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} else {
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/* if we're trying to save power */
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if (test_bit(STATUS_POWER_PMI, &priv->shrd->status)) {
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if (test_bit(STATUS_POWER_PMI, &trans->shrd->status)) {
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/* wake up nic if it's powered down ...
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* uCode will wake up, and interrupt us again, so next
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* time we'll skip this part. */
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reg = iwl_read32(bus(priv), CSR_UCODE_DRV_GP1);
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reg = iwl_read32(bus(trans), CSR_UCODE_DRV_GP1);
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if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
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IWL_DEBUG_INFO(priv,
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IWL_DEBUG_INFO(trans,
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"Tx queue %d requesting wakeup,"
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" GP1 = 0x%x\n", txq_id, reg);
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iwl_set_bit(bus(priv), CSR_GP_CNTRL,
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iwl_set_bit(bus(trans), CSR_GP_CNTRL,
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CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
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return;
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}
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iwl_write_direct32(bus(priv), HBUS_TARG_WRPTR,
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iwl_write_direct32(bus(trans), HBUS_TARG_WRPTR,
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txq->q.write_ptr | (txq_id << 8));
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/*
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@ -124,7 +124,7 @@ void iwl_txq_update_write_ptr(struct iwl_priv *priv, struct iwl_tx_queue *txq)
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* trying to tx (during RFKILL, we're not trying to tx).
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*/
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} else
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iwl_write32(bus(priv), HBUS_TARG_WRPTR,
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iwl_write32(bus(trans), HBUS_TARG_WRPTR,
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txq->q.write_ptr | (txq_id << 8));
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}
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txq->need_update = 0;
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@ -498,12 +498,12 @@ int iwl_trans_pcie_txq_agg_disable(struct iwl_priv *priv, u16 txq_id,
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struct iwl_trans *trans = trans(priv);
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if ((IWLAGN_FIRST_AMPDU_QUEUE > txq_id) ||
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(IWLAGN_FIRST_AMPDU_QUEUE +
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priv->cfg->base_params->num_of_ampdu_queues <= txq_id)) {
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hw_params(priv).num_ampdu_queues <= txq_id)) {
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IWL_ERR(priv,
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"queue number out of range: %d, must be %d to %d\n",
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txq_id, IWLAGN_FIRST_AMPDU_QUEUE,
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IWLAGN_FIRST_AMPDU_QUEUE +
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priv->cfg->base_params->num_of_ampdu_queues - 1);
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hw_params(priv).num_ampdu_queues - 1);
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return -EINVAL;
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}
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@ -536,8 +536,7 @@ int iwl_trans_pcie_txq_agg_disable(struct iwl_priv *priv, u16 txq_id,
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*/
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static int iwl_enqueue_hcmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd)
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{
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struct iwl_priv *priv = priv(trans);
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struct iwl_tx_queue *txq = &priv->txq[priv->shrd->cmd_queue];
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struct iwl_tx_queue *txq = &priv(trans)->txq[trans->shrd->cmd_queue];
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struct iwl_queue *q = &txq->q;
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struct iwl_device_cmd *out_cmd;
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struct iwl_cmd_meta *out_meta;
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@ -560,7 +559,7 @@ static int iwl_enqueue_hcmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd)
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return -EIO;
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}
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if ((priv->ucode_owner == IWL_OWNERSHIP_TM) &&
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if ((trans->shrd->ucode_owner == IWL_OWNERSHIP_TM) &&
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!(cmd->flags & CMD_ON_DEMAND)) {
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IWL_DEBUG_HC(trans, "tm own the uCode, no regular hcmd send\n");
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return -EIO;
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@ -607,10 +606,10 @@ static int iwl_enqueue_hcmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd)
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spin_unlock_irqrestore(&trans->hcmd_lock, flags);
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IWL_ERR(trans, "No space in command queue\n");
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is_ct_kill = iwl_check_for_ct_kill(priv);
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is_ct_kill = iwl_check_for_ct_kill(priv(trans));
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if (!is_ct_kill) {
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IWL_ERR(trans, "Restarting adapter queue is full\n");
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iwlagn_fw_error(priv, false);
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iwlagn_fw_error(priv(trans), false);
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}
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return -ENOSPC;
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}
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@ -702,7 +701,7 @@ static int iwl_enqueue_hcmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd)
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/* check that tracing gets all possible blocks */
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BUILD_BUG_ON(IWL_MAX_CMD_TFDS + 1 != 3);
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#ifdef CONFIG_IWLWIFI_DEVICE_TRACING
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trace_iwlwifi_dev_hcmd(priv, cmd->flags,
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trace_iwlwifi_dev_hcmd(priv(trans), cmd->flags,
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trace_bufs[0], trace_lens[0],
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trace_bufs[1], trace_lens[1],
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trace_bufs[2], trace_lens[2]);
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@ -710,7 +709,7 @@ static int iwl_enqueue_hcmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd)
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/* Increment and update queue's write index */
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q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
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iwl_txq_update_write_ptr(priv, txq);
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iwl_txq_update_write_ptr(trans, txq);
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out:
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spin_unlock_irqrestore(&trans->hcmd_lock, flags);
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@ -138,13 +138,12 @@ static void iwl_trans_rxq_free_rx_bufs(struct iwl_trans *trans)
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}
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}
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static void iwl_trans_rx_hw_init(struct iwl_priv *priv,
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static void iwl_trans_rx_hw_init(struct iwl_trans *trans,
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struct iwl_rx_queue *rxq)
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{
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u32 rb_size;
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const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
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u32 rb_timeout = 0; /* FIXME: RX_RB_TIMEOUT for all devices? */
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struct iwl_trans *trans = trans(priv);
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rb_timeout = RX_RB_TIMEOUT;
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@ -221,7 +220,7 @@ static int iwl_rx_init(struct iwl_trans *trans)
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iwlagn_rx_replenish(trans);
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iwl_trans_rx_hw_init(priv(trans), rxq);
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iwl_trans_rx_hw_init(trans, rxq);
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spin_lock_irqsave(&trans->shrd->lock, flags);
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rxq->need_update = 1;
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@ -509,7 +508,7 @@ static int iwl_trans_tx_alloc(struct iwl_trans *trans)
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struct iwl_trans_pcie *trans_pcie =
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IWL_TRANS_GET_PCIE_TRANS(trans);
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|
||||
u16 scd_bc_tbls_size = priv->cfg->base_params->num_of_queues *
|
||||
u16 scd_bc_tbls_size = hw_params(trans).max_txq_num *
|
||||
sizeof(struct iwlagn_scd_bc_tbl);
|
||||
|
||||
/*It is not allowed to alloc twice, so warn when this happens.
|
||||
|
@ -534,7 +533,7 @@ static int iwl_trans_tx_alloc(struct iwl_trans *trans)
|
|||
}
|
||||
|
||||
priv->txq = kzalloc(sizeof(struct iwl_tx_queue) *
|
||||
priv->cfg->base_params->num_of_queues, GFP_KERNEL);
|
||||
hw_params(trans).max_txq_num, GFP_KERNEL);
|
||||
if (!priv->txq) {
|
||||
IWL_ERR(trans, "Not enough memory for txq\n");
|
||||
ret = ENOMEM;
|
||||
|
@ -652,7 +651,7 @@ static int iwl_nic_init(struct iwl_trans *trans)
|
|||
if (iwl_tx_init(trans))
|
||||
return -ENOMEM;
|
||||
|
||||
if (priv->cfg->base_params->shadow_reg_enable) {
|
||||
if (hw_params(trans).shadow_reg_enable) {
|
||||
/* enable shadow regs in HW */
|
||||
iwl_set_bit(bus(trans), CSR_MAC_SHADOW_REG_CTRL,
|
||||
0x800FFFFF);
|
||||
|
@ -717,9 +716,9 @@ static int iwl_trans_pcie_start_device(struct iwl_trans *trans)
|
|||
int ret;
|
||||
struct iwl_priv *priv = priv(trans);
|
||||
|
||||
priv->ucode_owner = IWL_OWNERSHIP_DRIVER;
|
||||
priv->shrd->ucode_owner = IWL_OWNERSHIP_DRIVER;
|
||||
|
||||
if ((priv->cfg->sku & EEPROM_SKU_CAP_AMT_ENABLE) &&
|
||||
if ((hw_params(priv).sku & EEPROM_SKU_CAP_AMT_ENABLE) &&
|
||||
iwl_trans_pcie_prepare_card_hw(trans)) {
|
||||
IWL_WARN(trans, "Exit HW not ready\n");
|
||||
return -EIO;
|
||||
|
@ -1131,7 +1130,7 @@ static int iwl_trans_pcie_tx(struct iwl_priv *priv, struct sk_buff *skb,
|
|||
|
||||
/* Tell device the write index *just past* this latest filled TFD */
|
||||
q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
|
||||
iwl_txq_update_write_ptr(priv, txq);
|
||||
iwl_txq_update_write_ptr(trans(priv), txq);
|
||||
|
||||
/*
|
||||
* At this point the frame is "transmitted" successfully
|
||||
|
@ -1142,7 +1141,7 @@ static int iwl_trans_pcie_tx(struct iwl_priv *priv, struct sk_buff *skb,
|
|||
if (iwl_queue_space(q) < q->high_mark) {
|
||||
if (wait_write_ptr) {
|
||||
txq->need_update = 1;
|
||||
iwl_txq_update_write_ptr(priv, txq);
|
||||
iwl_txq_update_write_ptr(trans(priv), txq);
|
||||
} else {
|
||||
iwl_stop_queue(priv, txq);
|
||||
}
|
||||
|
@ -1366,7 +1365,7 @@ static ssize_t iwl_dbgfs_traffic_log_read(struct file *file,
|
|||
struct iwl_rx_queue *rxq = &trans_pcie->rxq;
|
||||
char *buf;
|
||||
int bufsz = ((IWL_TRAFFIC_ENTRIES * IWL_TRAFFIC_ENTRY_SIZE * 64) * 2) +
|
||||
(priv->cfg->base_params->num_of_queues * 32 * 8) + 400;
|
||||
(hw_params(trans).max_txq_num * 32 * 8) + 400;
|
||||
const u8 *ptr;
|
||||
ssize_t ret;
|
||||
|
||||
|
@ -1468,8 +1467,7 @@ static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
|
|||
int pos = 0;
|
||||
int cnt;
|
||||
int ret;
|
||||
const size_t bufsz = sizeof(char) * 64 *
|
||||
priv->cfg->base_params->num_of_queues;
|
||||
const size_t bufsz = sizeof(char) * 64 * hw_params(trans).max_txq_num;
|
||||
|
||||
if (!priv->txq) {
|
||||
IWL_ERR(priv, "txq not ready\n");
|
||||
|
|
Loading…
Reference in a new issue