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[PATCH] ppc32: Allow ERPN for early serial to depend on CPU type

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The PowerPC 440SPe supports up to 16 GB of RAM, and therefore its IO registers
are at 0x4_xxxx_xxxx instead of being at 0x1_xxxx_xxxx like most other PPC 440
chips.  To allow for this, this patch moves the definition of the ERPN used
for mapping UART0 from being hard-coded in the head_44x.S assembly code to
being defined in ibm44x.h.

Signed-off-by: Roland Dreier <rolandd@cisco.com>
Signed-off-by: Matt Porter <mporter@kernel.crashing.org>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
This commit is contained in:
Roland Dreier 2005-11-07 00:58:11 -08:00 committed by Linus Torvalds
parent 2104da90a9
commit fcc188e7fd
2 changed files with 8 additions and 3 deletions
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4
arch/ppc/kernel/head_44x.S
View file

@ -190,8 +190,8 @@ skpinv: addi r4,r4,1 /* Increment */
/* xlat fields */
lis r4,UART0_PHYS_IO_BASE@h /* RPN depends on SoC */
#ifndef CONFIG_440EP
ori r4,r4,0x0001 /* ERPN is 1 for second 4GB page */
#ifdef UART0_PHYS_ERPN
ori r4,r4,UART0_PHYS_ERPN /* Add ERPN if above 4GB */
#endif
/* attrib fields */

7
include/asm-ppc/ibm44x.h
View file

@ -34,12 +34,17 @@
/* Lowest TLB slot consumed by the default pinned TLBs */
#define PPC44x_LOW_SLOT 63
/* LS 32-bits of UART0 physical address location for early serial text debug */
/*
* Least significant 32-bits and extended real page number (ERPN) of
* UART0 physical address location for early serial text debug
*/
#if defined(CONFIG_440SP)
#define UART0_PHYS_ERPN 1
#define UART0_PHYS_IO_BASE 0xf0000200
#elif defined(CONFIG_440EP)
#define UART0_PHYS_IO_BASE 0xe0000000
#else
#define UART0_PHYS_ERPN 1
#define UART0_PHYS_IO_BASE 0x40000200
#endif