fbdev: bfin-lq035q1-fb: respect new PPI mode platform field
This lets us support the new BF527-EZKIT V2.1 via platform resources tweaks only. Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org> Cc: Bryan Wu <cooloney@kernel.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
This commit is contained in:
Michael Hennerich
Linus Torvalds
parent
5815e5d36e
commit
fbd65e0ecd
1 changed files with 146 additions and 106 deletions
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@ -61,47 +61,13 @@
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#define LCD_X_RES 320 /* Horizontal Resolution */
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#define LCD_Y_RES 240 /* Vertical Resolution */
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#define DMA_BUS_SIZE 16
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#define U_LINE 4 /* Blanking Lines */
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#define USE_RGB565_16_BIT_PPI
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#ifdef USE_RGB565_16_BIT_PPI
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#define LCD_BPP 16 /* Bit Per Pixel */
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#define CLOCKS_PER_PIX 1
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#define CPLD_PIPELINE_DELAY_COR 0 /* NO CPLB */
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#endif
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/* Interface 16/18-bit TFT over an 8-bit wide PPI using a small Programmable Logic Device (CPLD)
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* http://blackfin.uclinux.org/gf/project/stamp/frs/?action=FrsReleaseBrowse&frs_package_id=165
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*/
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#ifdef USE_RGB565_8_BIT_PPI
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#define LCD_BPP 16 /* Bit Per Pixel */
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#define CLOCKS_PER_PIX 2
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#define CPLD_PIPELINE_DELAY_COR 3 /* RGB565 */
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#endif
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#ifdef USE_RGB888_8_BIT_PPI
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#define LCD_BPP 24 /* Bit Per Pixel */
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#define CLOCKS_PER_PIX 3
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#define CPLD_PIPELINE_DELAY_COR 5 /* RGB888 */
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#endif
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/*
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* HS and VS timing parameters (all in number of PPI clk ticks)
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*/
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#define U_LINE 4 /* Blanking Lines */
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#define H_ACTPIX (LCD_X_RES * CLOCKS_PER_PIX) /* active horizontal pixel */
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#define H_PERIOD (336 * CLOCKS_PER_PIX) /* HS period */
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#define H_PULSE (2 * CLOCKS_PER_PIX) /* HS pulse width */
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#define H_START (7 * CLOCKS_PER_PIX + CPLD_PIPELINE_DELAY_COR) /* first valid pixel */
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#define V_LINES (LCD_Y_RES + U_LINE) /* total vertical lines */
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#define V_PULSE (2 * CLOCKS_PER_PIX) /* VS pulse width (1-5 H_PERIODs) */
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#define V_PERIOD (H_PERIOD * V_LINES) /* VS period */
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#define ACTIVE_VIDEO_MEM_OFFSET ((U_LINE / 2) * LCD_X_RES * (LCD_BPP / 8))
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#define BFIN_LCD_NBR_PALETTE_ENTRIES 256
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@ -110,12 +76,6 @@
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#define PPI_PORT_CFG_01 0x10
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#define PPI_POLS_1 0x8000
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#if (CLOCKS_PER_PIX > 1)
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#define PPI_PMODE (DLEN_8 | PACK_EN)
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#else
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#define PPI_PMODE (DLEN_16)
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#endif
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#define LQ035_INDEX 0x74
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#define LQ035_DATA 0x76
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@ -139,6 +99,15 @@ struct bfin_lq035q1fb_info {
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int irq;
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spinlock_t lock; /* lock */
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u32 pseudo_pal[16];
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u32 lcd_bpp;
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u32 h_actpix;
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u32 h_period;
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u32 h_pulse;
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u32 h_start;
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u32 v_lines;
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u32 v_pulse;
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u32 v_period;
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};
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static int nocursor;
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@ -234,16 +203,69 @@ static int lq035q1_backlight(struct bfin_lq035q1fb_info *info, unsigned arg)
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return 0;
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}
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static int bfin_lq035q1_calc_timing(struct bfin_lq035q1fb_info *fbi)
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{
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unsigned long clocks_per_pix, cpld_pipeline_delay_cor;
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/*
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* Interface 16/18-bit TFT over an 8-bit wide PPI using a small
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* Programmable Logic Device (CPLD)
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* http://blackfin.uclinux.org/gf/project/stamp/frs/?action=FrsReleaseBrowse&frs_package_id=165
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*/
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switch (fbi->disp_info->ppi_mode) {
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case USE_RGB565_16_BIT_PPI:
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fbi->lcd_bpp = 16;
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clocks_per_pix = 1;
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cpld_pipeline_delay_cor = 0;
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break;
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case USE_RGB565_8_BIT_PPI:
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fbi->lcd_bpp = 16;
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clocks_per_pix = 2;
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cpld_pipeline_delay_cor = 3;
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break;
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case USE_RGB888_8_BIT_PPI:
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fbi->lcd_bpp = 24;
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clocks_per_pix = 3;
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cpld_pipeline_delay_cor = 5;
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break;
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default:
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return -EINVAL;
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}
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/*
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* HS and VS timing parameters (all in number of PPI clk ticks)
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*/
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fbi->h_actpix = (LCD_X_RES * clocks_per_pix); /* active horizontal pixel */
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fbi->h_period = (336 * clocks_per_pix); /* HS period */
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fbi->h_pulse = (2 * clocks_per_pix); /* HS pulse width */
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fbi->h_start = (7 * clocks_per_pix + cpld_pipeline_delay_cor); /* first valid pixel */
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fbi->v_lines = (LCD_Y_RES + U_LINE); /* total vertical lines */
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fbi->v_pulse = (2 * clocks_per_pix); /* VS pulse width (1-5 H_PERIODs) */
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fbi->v_period = (fbi->h_period * fbi->v_lines); /* VS period */
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return 0;
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}
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static void bfin_lq035q1_config_ppi(struct bfin_lq035q1fb_info *fbi)
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{
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bfin_write_PPI_DELAY(H_START);
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bfin_write_PPI_COUNT(H_ACTPIX - 1);
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bfin_write_PPI_FRAME(V_LINES);
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unsigned ppi_pmode;
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if (fbi->disp_info->ppi_mode == USE_RGB565_16_BIT_PPI)
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ppi_pmode = DLEN_16;
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else
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ppi_pmode = (DLEN_8 | PACK_EN);
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bfin_write_PPI_DELAY(fbi->h_start);
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bfin_write_PPI_COUNT(fbi->h_actpix - 1);
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bfin_write_PPI_FRAME(fbi->v_lines);
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bfin_write_PPI_CONTROL(PPI_TX_MODE | /* output mode , PORT_DIR */
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PPI_XFER_TYPE_11 | /* sync mode XFR_TYPE */
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PPI_PORT_CFG_01 | /* two frame sync PORT_CFG */
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PPI_PMODE | /* 8/16 bit data length / PACK_EN? */
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ppi_pmode | /* 8/16 bit data length / PACK_EN? */
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PPI_POLS_1); /* faling edge syncs POLS */
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}
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@ -272,19 +294,19 @@ static void bfin_lq035q1_stop_timers(void)
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}
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static void bfin_lq035q1_init_timers(void)
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static void bfin_lq035q1_init_timers(struct bfin_lq035q1fb_info *fbi)
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{
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bfin_lq035q1_stop_timers();
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set_gptimer_period(TIMER_HSYNC_id, H_PERIOD);
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set_gptimer_pwidth(TIMER_HSYNC_id, H_PULSE);
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set_gptimer_period(TIMER_HSYNC_id, fbi->h_period);
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set_gptimer_pwidth(TIMER_HSYNC_id, fbi->h_pulse);
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set_gptimer_config(TIMER_HSYNC_id, TIMER_MODE_PWM | TIMER_PERIOD_CNT |
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TIMER_TIN_SEL | TIMER_CLK_SEL|
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TIMER_EMU_RUN);
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set_gptimer_period(TIMER_VSYNC_id, V_PERIOD);
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set_gptimer_pwidth(TIMER_VSYNC_id, V_PULSE);
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set_gptimer_period(TIMER_VSYNC_id, fbi->v_period);
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set_gptimer_pwidth(TIMER_VSYNC_id, fbi->v_pulse);
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set_gptimer_config(TIMER_VSYNC_id, TIMER_MODE_PWM | TIMER_PERIOD_CNT |
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TIMER_TIN_SEL | TIMER_CLK_SEL |
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TIMER_EMU_RUN);
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@ -294,21 +316,21 @@ static void bfin_lq035q1_init_timers(void)
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static void bfin_lq035q1_config_dma(struct bfin_lq035q1fb_info *fbi)
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{
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set_dma_config(CH_PPI,
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set_bfin_dma_config(DIR_READ, DMA_FLOW_AUTO,
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INTR_DISABLE, DIMENSION_2D,
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DATA_SIZE_16,
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DMA_NOSYNC_KEEP_DMA_BUF));
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set_dma_x_count(CH_PPI, (LCD_X_RES * LCD_BPP) / DMA_BUS_SIZE);
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set_dma_x_count(CH_PPI, (LCD_X_RES * fbi->lcd_bpp) / DMA_BUS_SIZE);
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set_dma_x_modify(CH_PPI, DMA_BUS_SIZE / 8);
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set_dma_y_count(CH_PPI, V_LINES);
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set_dma_y_count(CH_PPI, fbi->v_lines);
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set_dma_y_modify(CH_PPI, DMA_BUS_SIZE / 8);
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set_dma_start_addr(CH_PPI, (unsigned long)fbi->fb_buffer);
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}
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#if (CLOCKS_PER_PIX == 1)
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static const u16 ppi0_req_16[] = {P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2,
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P_PPI0_D0, P_PPI0_D1, P_PPI0_D2,
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P_PPI0_D3, P_PPI0_D4, P_PPI0_D5,
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@ -316,22 +338,27 @@ static const u16 ppi0_req_16[] = {P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2,
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P_PPI0_D9, P_PPI0_D10, P_PPI0_D11,
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P_PPI0_D12, P_PPI0_D13, P_PPI0_D14,
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P_PPI0_D15, 0};
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#else
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static const u16 ppi0_req_16[] = {P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2,
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static const u16 ppi0_req_8[] = {P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2,
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P_PPI0_D0, P_PPI0_D1, P_PPI0_D2,
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P_PPI0_D3, P_PPI0_D4, P_PPI0_D5,
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P_PPI0_D6, P_PPI0_D7, 0};
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#endif
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static inline void bfin_lq035q1_free_ports(void)
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static inline void bfin_lq035q1_free_ports(unsigned ppi16)
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{
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peripheral_free_list(ppi0_req_16);
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if (ppi16)
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peripheral_free_list(ppi0_req_16);
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else
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peripheral_free_list(ppi0_req_8);
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if (ANOMALY_05000400)
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gpio_free(P_IDENT(P_PPI0_FS3));
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}
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static int __devinit bfin_lq035q1_request_ports(struct platform_device *pdev)
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static int __devinit bfin_lq035q1_request_ports(struct platform_device *pdev,
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unsigned ppi16)
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{
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int ret;
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/* ANOMALY_05000400 - PPI Does Not Start Properly In Specific Mode:
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* Drive PPI_FS3 Low
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*/
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@ -342,7 +369,12 @@ static int __devinit bfin_lq035q1_request_ports(struct platform_device *pdev)
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gpio_direction_output(P_IDENT(P_PPI0_FS3), 0);
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}
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if (peripheral_request_list(ppi0_req_16, DRIVER_NAME)) {
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if (ppi16)
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ret = peripheral_request_list(ppi0_req_16, DRIVER_NAME);
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else
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ret = peripheral_request_list(ppi0_req_8, DRIVER_NAME);
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if (ret) {
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dev_err(&pdev->dev, "requesting peripherals failed\n");
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return -EFAULT;
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}
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@ -364,7 +396,7 @@ static int bfin_lq035q1_fb_open(struct fb_info *info, int user)
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bfin_lq035q1_config_dma(fbi);
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bfin_lq035q1_config_ppi(fbi);
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bfin_lq035q1_init_timers();
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bfin_lq035q1_init_timers(fbi);
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/* start dma */
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enable_dma(CH_PPI);
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@ -402,12 +434,9 @@ static int bfin_lq035q1_fb_release(struct fb_info *info, int user)
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static int bfin_lq035q1_fb_check_var(struct fb_var_screeninfo *var,
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struct fb_info *info)
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{
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switch (var->bits_per_pixel) {
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#if (LCD_BPP == 24)
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case 24:/* TRUECOLOUR, 16m */
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#else
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case 16:/* DIRECTCOLOUR, 64k */
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#endif
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struct bfin_lq035q1fb_info *fbi = info->par;
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if (var->bits_per_pixel == fbi->lcd_bpp) {
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var->red.offset = info->var.red.offset;
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var->green.offset = info->var.green.offset;
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var->blue.offset = info->var.blue.offset;
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@ -420,8 +449,7 @@ static int bfin_lq035q1_fb_check_var(struct fb_var_screeninfo *var,
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var->red.msb_right = 0;
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var->green.msb_right = 0;
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var->blue.msb_right = 0;
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break;
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default:
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} else {
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pr_debug("%s: depth not supported: %u BPP\n", __func__,
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var->bits_per_pixel);
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return -EINVAL;
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@ -528,6 +556,7 @@ static int __devinit bfin_lq035q1_probe(struct platform_device *pdev)
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{
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struct bfin_lq035q1fb_info *info;
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struct fb_info *fbinfo;
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u32 active_video_mem_offset;
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int ret;
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ret = request_dma(CH_PPI, DRIVER_NAME"_CH_PPI");
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@ -550,6 +579,12 @@ static int __devinit bfin_lq035q1_probe(struct platform_device *pdev)
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platform_set_drvdata(pdev, fbinfo);
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ret = bfin_lq035q1_calc_timing(info);
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if (ret < 0) {
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dev_err(&pdev->dev, "Failed PPI Mode\n");
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goto out3;
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}
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strcpy(fbinfo->fix.id, DRIVER_NAME);
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fbinfo->fix.type = FB_TYPE_PACKED_PIXELS;
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@ -571,46 +606,48 @@ static int __devinit bfin_lq035q1_probe(struct platform_device *pdev)
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fbinfo->var.xres_virtual = LCD_X_RES;
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fbinfo->var.yres = LCD_Y_RES;
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fbinfo->var.yres_virtual = LCD_Y_RES;
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fbinfo->var.bits_per_pixel = LCD_BPP;
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fbinfo->var.bits_per_pixel = info->lcd_bpp;
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if (info->disp_info->mode & LQ035_BGR) {
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#if (LCD_BPP == 24)
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fbinfo->var.red.offset = 0;
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fbinfo->var.green.offset = 8;
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fbinfo->var.blue.offset = 16;
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#else
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fbinfo->var.red.offset = 0;
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fbinfo->var.green.offset = 5;
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fbinfo->var.blue.offset = 11;
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#endif
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if (info->lcd_bpp == 24) {
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fbinfo->var.red.offset = 0;
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fbinfo->var.green.offset = 8;
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fbinfo->var.blue.offset = 16;
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} else {
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fbinfo->var.red.offset = 0;
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fbinfo->var.green.offset = 5;
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fbinfo->var.blue.offset = 11;
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}
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} else {
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#if (LCD_BPP == 24)
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fbinfo->var.red.offset = 16;
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fbinfo->var.green.offset = 8;
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fbinfo->var.blue.offset = 0;
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#else
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fbinfo->var.red.offset = 11;
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fbinfo->var.green.offset = 5;
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fbinfo->var.blue.offset = 0;
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#endif
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if (info->lcd_bpp == 24) {
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fbinfo->var.red.offset = 16;
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fbinfo->var.green.offset = 8;
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fbinfo->var.blue.offset = 0;
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} else {
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fbinfo->var.red.offset = 11;
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fbinfo->var.green.offset = 5;
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fbinfo->var.blue.offset = 0;
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}
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}
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fbinfo->var.transp.offset = 0;
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#if (LCD_BPP == 24)
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fbinfo->var.red.length = 8;
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fbinfo->var.green.length = 8;
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fbinfo->var.blue.length = 8;
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#else
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fbinfo->var.red.length = 5;
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fbinfo->var.green.length = 6;
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fbinfo->var.blue.length = 5;
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#endif
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if (info->lcd_bpp == 24) {
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fbinfo->var.red.length = 8;
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fbinfo->var.green.length = 8;
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fbinfo->var.blue.length = 8;
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} else {
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fbinfo->var.red.length = 5;
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fbinfo->var.green.length = 6;
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fbinfo->var.blue.length = 5;
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}
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fbinfo->var.transp.length = 0;
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fbinfo->fix.smem_len = LCD_X_RES * LCD_Y_RES * LCD_BPP / 8
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+ ACTIVE_VIDEO_MEM_OFFSET;
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active_video_mem_offset = ((U_LINE / 2) * LCD_X_RES * (info->lcd_bpp / 8));
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fbinfo->fix.smem_len = LCD_X_RES * LCD_Y_RES * info->lcd_bpp / 8
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+ active_video_mem_offset;
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fbinfo->fix.line_length = fbinfo->var.xres_virtual *
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fbinfo->var.bits_per_pixel / 8;
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@ -629,8 +666,8 @@ static int __devinit bfin_lq035q1_probe(struct platform_device *pdev)
|
|||
goto out3;
|
||||
}
|
||||
|
||||
fbinfo->screen_base = (void *)info->fb_buffer + ACTIVE_VIDEO_MEM_OFFSET;
|
||||
fbinfo->fix.smem_start = (int)info->fb_buffer + ACTIVE_VIDEO_MEM_OFFSET;
|
||||
fbinfo->screen_base = (void *)info->fb_buffer + active_video_mem_offset;
|
||||
fbinfo->fix.smem_start = (int)info->fb_buffer + active_video_mem_offset;
|
||||
|
||||
fbinfo->fbops = &bfin_lq035q1_fb_ops;
|
||||
|
||||
|
|
@ -643,7 +680,8 @@ static int __devinit bfin_lq035q1_probe(struct platform_device *pdev)
|
|||
goto out4;
|
||||
}
|
||||
|
||||
ret = bfin_lq035q1_request_ports(pdev);
|
||||
ret = bfin_lq035q1_request_ports(pdev,
|
||||
info->disp_info->ppi_mode == USE_RGB565_16_BIT_PPI);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "couldn't request gpio port\n");
|
||||
goto out6;
|
||||
|
|
@ -693,7 +731,7 @@ static int __devinit bfin_lq035q1_probe(struct platform_device *pdev)
|
|||
}
|
||||
|
||||
dev_info(&pdev->dev, "%dx%d %d-bit RGB FrameBuffer initialized\n",
|
||||
LCD_X_RES, LCD_Y_RES, LCD_BPP);
|
||||
LCD_X_RES, LCD_Y_RES, info->lcd_bpp);
|
||||
|
||||
return 0;
|
||||
|
||||
|
|
@ -705,7 +743,8 @@ static int __devinit bfin_lq035q1_probe(struct platform_device *pdev)
|
|||
out8:
|
||||
free_irq(info->irq, info);
|
||||
out7:
|
||||
bfin_lq035q1_free_ports();
|
||||
bfin_lq035q1_free_ports(info->disp_info->ppi_mode ==
|
||||
USE_RGB565_16_BIT_PPI);
|
||||
out6:
|
||||
fb_dealloc_cmap(&fbinfo->cmap);
|
||||
out4:
|
||||
|
|
@ -742,7 +781,8 @@ static int __devexit bfin_lq035q1_remove(struct platform_device *pdev)
|
|||
|
||||
fb_dealloc_cmap(&fbinfo->cmap);
|
||||
|
||||
bfin_lq035q1_free_ports();
|
||||
bfin_lq035q1_free_ports(info->disp_info->ppi_mode ==
|
||||
USE_RGB565_16_BIT_PPI);
|
||||
|
||||
platform_set_drvdata(pdev, NULL);
|
||||
framebuffer_release(fbinfo);
|
||||
|
|
@ -781,7 +821,7 @@ static int bfin_lq035q1_resume(struct device *dev)
|
|||
|
||||
bfin_lq035q1_config_dma(info);
|
||||
bfin_lq035q1_config_ppi(info);
|
||||
bfin_lq035q1_init_timers();
|
||||
bfin_lq035q1_init_timers(info);
|
||||
|
||||
/* start dma */
|
||||
enable_dma(CH_PPI);
|
||||
|
|
|
|||
Loading…
Reference in a new issue