Disintegrate asm/system.h for Xtensa
Disintegrate asm/system.h for Xtensa. Signed-off-by: David Howells <dhowells@redhat.com> cc: Chris Zankel <chris@zankel.net>
This commit is contained in:
David Howells
parent
8978bfd228
commit
f9aa7e1882
15 changed files with 225 additions and 191 deletions
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@ -18,7 +18,7 @@
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#ifdef __KERNEL__
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#include <asm/processor.h>
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#include <asm/system.h>
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#include <asm/cmpxchg.h>
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#define ATOMIC_INIT(i) { (i) }
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29
arch/xtensa/include/asm/barrier.h
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29
arch/xtensa/include/asm/barrier.h
Normal file
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@ -0,0 +1,29 @@
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2001 - 2005 Tensilica Inc.
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*/
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#ifndef _XTENSA_SYSTEM_H
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#define _XTENSA_SYSTEM_H
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#define smp_read_barrier_depends() do { } while(0)
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#define read_barrier_depends() do { } while(0)
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#define mb() barrier()
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#define rmb() mb()
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#define wmb() mb()
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#ifdef CONFIG_SMP
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#error smp_* not defined
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#else
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#define smp_mb() barrier()
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#define smp_rmb() barrier()
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#define smp_wmb() barrier()
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#endif
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#define set_mb(var, value) do { var = value; mb(); } while (0)
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#endif /* _XTENSA_SYSTEM_H */
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@ -21,7 +21,6 @@
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#include <asm/processor.h>
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#include <asm/byteorder.h>
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#include <asm/system.h>
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#ifdef CONFIG_SMP
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# error SMP not supported on this architecture
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131
arch/xtensa/include/asm/cmpxchg.h
Normal file
131
arch/xtensa/include/asm/cmpxchg.h
Normal file
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@ -0,0 +1,131 @@
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/*
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* Atomic xchg and cmpxchg operations.
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2001 - 2005 Tensilica Inc.
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*/
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#ifndef _XTENSA_CMPXCHG_H
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#define _XTENSA_CMPXCHG_H
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#ifndef __ASSEMBLY__
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#include <linux/stringify.h>
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/*
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* cmpxchg
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*/
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static inline unsigned long
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__cmpxchg_u32(volatile int *p, int old, int new)
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{
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__asm__ __volatile__("rsil a15, "__stringify(LOCKLEVEL)"\n\t"
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"l32i %0, %1, 0 \n\t"
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"bne %0, %2, 1f \n\t"
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"s32i %3, %1, 0 \n\t"
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"1: \n\t"
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"wsr a15, "__stringify(PS)" \n\t"
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"rsync \n\t"
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: "=&a" (old)
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: "a" (p), "a" (old), "r" (new)
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: "a15", "memory");
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return old;
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}
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/* This function doesn't exist, so you'll get a linker error
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* if something tries to do an invalid cmpxchg(). */
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extern void __cmpxchg_called_with_bad_pointer(void);
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static __inline__ unsigned long
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__cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size)
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{
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switch (size) {
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case 4: return __cmpxchg_u32(ptr, old, new);
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default: __cmpxchg_called_with_bad_pointer();
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return old;
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}
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}
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#define cmpxchg(ptr,o,n) \
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({ __typeof__(*(ptr)) _o_ = (o); \
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__typeof__(*(ptr)) _n_ = (n); \
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(__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_, \
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(unsigned long)_n_, sizeof (*(ptr))); \
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})
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#include <asm-generic/cmpxchg-local.h>
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static inline unsigned long __cmpxchg_local(volatile void *ptr,
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unsigned long old,
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unsigned long new, int size)
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{
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switch (size) {
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case 4:
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return __cmpxchg_u32(ptr, old, new);
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default:
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return __cmpxchg_local_generic(ptr, old, new, size);
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}
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return old;
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}
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/*
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* cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make
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* them available.
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*/
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#define cmpxchg_local(ptr, o, n) \
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((__typeof__(*(ptr)))__cmpxchg_local_generic((ptr), (unsigned long)(o),\
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(unsigned long)(n), sizeof(*(ptr))))
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#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
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/*
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* xchg_u32
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*
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* Note that a15 is used here because the register allocation
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* done by the compiler is not guaranteed and a window overflow
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* may not occur between the rsil and wsr instructions. By using
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* a15 in the rsil, the machine is guaranteed to be in a state
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* where no register reference will cause an overflow.
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*/
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static inline unsigned long xchg_u32(volatile int * m, unsigned long val)
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{
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unsigned long tmp;
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__asm__ __volatile__("rsil a15, "__stringify(LOCKLEVEL)"\n\t"
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"l32i %0, %1, 0 \n\t"
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"s32i %2, %1, 0 \n\t"
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"wsr a15, "__stringify(PS)" \n\t"
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"rsync \n\t"
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: "=&a" (tmp)
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: "a" (m), "a" (val)
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: "a15", "memory");
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return tmp;
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}
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#define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
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/*
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* This only works if the compiler isn't horribly bad at optimizing.
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* gcc-2.5.8 reportedly can't handle this, but I define that one to
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* be dead anyway.
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*/
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extern void __xchg_called_with_bad_pointer(void);
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static __inline__ unsigned long
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__xchg(unsigned long x, volatile void * ptr, int size)
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{
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switch (size) {
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case 4:
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return xchg_u32(ptr, x);
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}
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__xchg_called_with_bad_pointer();
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return x;
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}
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#endif /* __ASSEMBLY__ */
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#endif /* _XTENSA_CMPXCHG_H */
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14
arch/xtensa/include/asm/exec.h
Normal file
14
arch/xtensa/include/asm/exec.h
Normal file
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@ -0,0 +1,14 @@
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2001 - 2005 Tensilica Inc.
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*/
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#ifndef _XTENSA_EXEC_H
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#define _XTENSA_EXEC_H
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#define arch_align_stack(x) (x)
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#endif /* _XTENSA_EXEC_H */
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@ -13,4 +13,6 @@
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#define COMMAND_LINE_SIZE 256
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extern void set_except_vector(int n, void *addr);
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#endif
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22
arch/xtensa/include/asm/switch_to.h
Normal file
22
arch/xtensa/include/asm/switch_to.h
Normal file
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@ -0,0 +1,22 @@
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2001 - 2005 Tensilica Inc.
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*/
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#ifndef _XTENSA_SWITCH_TO_H
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#define _XTENSA_SWITCH_TO_H
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/* * switch_to(n) should switch tasks to task nr n, first
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* checking that n isn't the current task, in which case it does nothing.
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*/
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extern void *_switch_to(void *last, void *next);
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#define switch_to(prev,next,last) \
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do { \
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(last) = _switch_to(prev, next); \
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} while(0)
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#endif /* _XTENSA_SWITCH_TO_H */
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@ -1,184 +1,5 @@
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/*
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* include/asm-xtensa/system.h
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2001 - 2005 Tensilica Inc.
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*/
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#ifndef _XTENSA_SYSTEM_H
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#define _XTENSA_SYSTEM_H
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#include <linux/stringify.h>
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#include <linux/irqflags.h>
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#include <asm/processor.h>
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#define smp_read_barrier_depends() do { } while(0)
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#define read_barrier_depends() do { } while(0)
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#define mb() barrier()
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#define rmb() mb()
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#define wmb() mb()
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#ifdef CONFIG_SMP
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#error smp_* not defined
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#else
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#define smp_mb() barrier()
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#define smp_rmb() barrier()
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#define smp_wmb() barrier()
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#endif
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#define set_mb(var, value) do { var = value; mb(); } while (0)
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#if !defined (__ASSEMBLY__)
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/* * switch_to(n) should switch tasks to task nr n, first
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* checking that n isn't the current task, in which case it does nothing.
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*/
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extern void *_switch_to(void *last, void *next);
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#endif /* __ASSEMBLY__ */
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#define switch_to(prev,next,last) \
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do { \
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(last) = _switch_to(prev, next); \
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} while(0)
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/*
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* cmpxchg
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*/
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static inline unsigned long
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__cmpxchg_u32(volatile int *p, int old, int new)
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{
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__asm__ __volatile__("rsil a15, "__stringify(LOCKLEVEL)"\n\t"
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"l32i %0, %1, 0 \n\t"
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"bne %0, %2, 1f \n\t"
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"s32i %3, %1, 0 \n\t"
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"1: \n\t"
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"wsr a15, "__stringify(PS)" \n\t"
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"rsync \n\t"
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: "=&a" (old)
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: "a" (p), "a" (old), "r" (new)
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: "a15", "memory");
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return old;
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}
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/* This function doesn't exist, so you'll get a linker error
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* if something tries to do an invalid cmpxchg(). */
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extern void __cmpxchg_called_with_bad_pointer(void);
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static __inline__ unsigned long
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__cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size)
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{
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switch (size) {
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case 4: return __cmpxchg_u32(ptr, old, new);
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default: __cmpxchg_called_with_bad_pointer();
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return old;
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}
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}
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#define cmpxchg(ptr,o,n) \
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({ __typeof__(*(ptr)) _o_ = (o); \
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__typeof__(*(ptr)) _n_ = (n); \
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(__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_, \
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(unsigned long)_n_, sizeof (*(ptr))); \
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})
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#include <asm-generic/cmpxchg-local.h>
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static inline unsigned long __cmpxchg_local(volatile void *ptr,
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unsigned long old,
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unsigned long new, int size)
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{
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switch (size) {
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case 4:
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return __cmpxchg_u32(ptr, old, new);
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default:
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return __cmpxchg_local_generic(ptr, old, new, size);
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}
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return old;
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}
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/*
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* cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make
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* them available.
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*/
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#define cmpxchg_local(ptr, o, n) \
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((__typeof__(*(ptr)))__cmpxchg_local_generic((ptr), (unsigned long)(o),\
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(unsigned long)(n), sizeof(*(ptr))))
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#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
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/*
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* xchg_u32
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*
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* Note that a15 is used here because the register allocation
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* done by the compiler is not guaranteed and a window overflow
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* may not occur between the rsil and wsr instructions. By using
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* a15 in the rsil, the machine is guaranteed to be in a state
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* where no register reference will cause an overflow.
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*/
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static inline unsigned long xchg_u32(volatile int * m, unsigned long val)
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{
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unsigned long tmp;
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__asm__ __volatile__("rsil a15, "__stringify(LOCKLEVEL)"\n\t"
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"l32i %0, %1, 0 \n\t"
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"s32i %2, %1, 0 \n\t"
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"wsr a15, "__stringify(PS)" \n\t"
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"rsync \n\t"
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: "=&a" (tmp)
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: "a" (m), "a" (val)
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: "a15", "memory");
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return tmp;
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}
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#define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
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/*
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* This only works if the compiler isn't horribly bad at optimizing.
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* gcc-2.5.8 reportedly can't handle this, but I define that one to
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* be dead anyway.
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*/
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extern void __xchg_called_with_bad_pointer(void);
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static __inline__ unsigned long
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__xchg(unsigned long x, volatile void * ptr, int size)
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{
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switch (size) {
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case 4:
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return xchg_u32(ptr, x);
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}
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__xchg_called_with_bad_pointer();
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return x;
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}
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extern void set_except_vector(int n, void *addr);
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static inline void spill_registers(void)
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{
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unsigned int a0, ps;
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__asm__ __volatile__ (
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"movi a14," __stringify (PS_EXCM_BIT) " | 1\n\t"
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"mov a12, a0\n\t"
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"rsr a13," __stringify(SAR) "\n\t"
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"xsr a14," __stringify(PS) "\n\t"
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"movi a0, _spill_registers\n\t"
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"rsync\n\t"
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"callx0 a0\n\t"
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"mov a0, a12\n\t"
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"wsr a13," __stringify(SAR) "\n\t"
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"wsr a14," __stringify(PS) "\n\t"
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:: "a" (&a0), "a" (&ps)
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: "a2", "a3", "a4", "a7", "a11", "a12", "a13", "a14", "a15", "memory");
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}
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#define arch_align_stack(x) (x)
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#endif /* _XTENSA_SYSTEM_H */
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/* FILE TO BE DELETED. DO NOT ADD STUFF HERE! */
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#include <asm/barrier.h>
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#include <asm/cmpxchg.h>
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#include <asm/exec.h>
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#include <asm/switch_to.h>
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@ -17,7 +17,9 @@
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#define _XTENSA_UACCESS_H
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#include <linux/errno.h>
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#ifndef __ASSEMBLY__
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#include <linux/prefetch.h>
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#endif
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#include <asm/types.h>
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#define VERIFY_READ 0
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@ -34,7 +34,6 @@
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#include <asm/pgtable.h>
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#include <asm/uaccess.h>
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#include <asm/system.h>
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#include <asm/io.h>
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#include <asm/processor.h>
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#include <asm/platform.h>
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@ -24,7 +24,6 @@
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#include <asm/pgtable.h>
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#include <asm/page.h>
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#include <asm/system.h>
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#include <asm/uaccess.h>
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#include <asm/ptrace.h>
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#include <asm/elf.h>
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@ -34,7 +34,6 @@
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# include <linux/seq_file.h>
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#endif
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#include <asm/system.h>
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#include <asm/bootparam.h>
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#include <asm/pgtable.h>
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#include <asm/processor.h>
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@ -381,6 +381,25 @@ static __always_inline unsigned long *stack_pointer(struct task_struct *task)
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return sp;
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}
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static inline void spill_registers(void)
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{
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unsigned int a0, ps;
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__asm__ __volatile__ (
|
||||
"movi a14," __stringify (PS_EXCM_BIT) " | 1\n\t"
|
||||
"mov a12, a0\n\t"
|
||||
"rsr a13," __stringify(SAR) "\n\t"
|
||||
"xsr a14," __stringify(PS) "\n\t"
|
||||
"movi a0, _spill_registers\n\t"
|
||||
"rsync\n\t"
|
||||
"callx0 a0\n\t"
|
||||
"mov a0, a12\n\t"
|
||||
"wsr a13," __stringify(SAR) "\n\t"
|
||||
"wsr a14," __stringify(PS) "\n\t"
|
||||
:: "a" (&a0), "a" (&ps)
|
||||
: "a2", "a3", "a4", "a7", "a11", "a12", "a13", "a14", "a15", "memory");
|
||||
}
|
||||
|
||||
void show_trace(struct task_struct *task, unsigned long *sp)
|
||||
{
|
||||
unsigned long a0, a1, pc;
|
||||
|
|
|
|||
|
|
@ -19,7 +19,6 @@
|
|||
#include <asm/cacheflush.h>
|
||||
#include <asm/hardirq.h>
|
||||
#include <asm/uaccess.h>
|
||||
#include <asm/system.h>
|
||||
#include <asm/pgalloc.h>
|
||||
|
||||
unsigned long asid_cache = ASID_USER_FIRST;
|
||||
|
|
|
|||
|
|
@ -18,7 +18,6 @@
|
|||
#include <asm/processor.h>
|
||||
#include <asm/mmu_context.h>
|
||||
#include <asm/tlbflush.h>
|
||||
#include <asm/system.h>
|
||||
#include <asm/cacheflush.h>
|
||||
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue