[SCSI] megaraid_sas: support for 1078 type controller added
This patch adds support for 1078 type controller (device id : 0x60). Signed-off-by: Sumant Patro <Sumant.Patro@lsil.com> Signed-off-by: James Bottomley <James.Bottomley@SteelEye.com>
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3 changed files with 140 additions and 18 deletions
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@ -1,3 +1,14 @@
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1 Release Date : Wed Feb 03 14:31:44 PST 2006 - Sumant Patro <Sumant.Patro@lsil.com>
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2 Current Version : 00.00.02.04
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3 Older Version : 00.00.02.04
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i. Support for 1078 type (ppc IOP) controller, device id : 0x60 added.
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During initialization, depending on the device id, the template members
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are initialized with function pointers specific to the ppc or
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xscale controllers.
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-Sumant Patro <Sumant.Patro@lsil.com>
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1 Release Date : Fri Feb 03 14:16:25 PST 2006 - Sumant Patro
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<Sumant.Patro@lsil.com>
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2 Current Version : 00.00.02.04
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@ -59,6 +59,12 @@ static struct pci_device_id megasas_pci_table[] = {
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PCI_ANY_ID,
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PCI_ANY_ID,
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},
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{
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PCI_VENDOR_ID_LSI_LOGIC,
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PCI_DEVICE_ID_LSI_SAS1078R, // ppc IOP
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PCI_ANY_ID,
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PCI_ANY_ID,
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},
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{
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PCI_VENDOR_ID_DELL,
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PCI_DEVICE_ID_DELL_PERC5, // xscale IOP
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@ -198,6 +204,86 @@ static struct megasas_instance_template megasas_instance_template_xscale = {
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* to xscale (deviceid : 1064R, PERC5) controllers
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*/
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/**
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* The following functions are defined for ppc (deviceid : 0x60)
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* controllers
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*/
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/**
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* megasas_enable_intr_ppc - Enables interrupts
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* @regs: MFI register set
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*/
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static inline void
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megasas_enable_intr_ppc(struct megasas_register_set __iomem * regs)
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{
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writel(0xFFFFFFFF, &(regs)->outbound_doorbell_clear);
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writel(~0x80000004, &(regs)->outbound_intr_mask);
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/* Dummy readl to force pci flush */
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readl(®s->outbound_intr_mask);
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}
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/**
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* megasas_read_fw_status_reg_ppc - returns the current FW status value
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* @regs: MFI register set
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*/
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static u32
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megasas_read_fw_status_reg_ppc(struct megasas_register_set __iomem * regs)
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{
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return readl(&(regs)->outbound_scratch_pad);
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}
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/**
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* megasas_clear_interrupt_ppc - Check & clear interrupt
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* @regs: MFI register set
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*/
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static int
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megasas_clear_intr_ppc(struct megasas_register_set __iomem * regs)
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{
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u32 status;
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/*
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* Check if it is our interrupt
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*/
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status = readl(®s->outbound_intr_status);
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if (!(status & MFI_REPLY_1078_MESSAGE_INTERRUPT)) {
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return 1;
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}
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/*
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* Clear the interrupt by writing back the same value
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*/
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writel(status, ®s->outbound_doorbell_clear);
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return 0;
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}
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/**
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* megasas_fire_cmd_ppc - Sends command to the FW
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* @frame_phys_addr : Physical address of cmd
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* @frame_count : Number of frames for the command
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* @regs : MFI register set
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*/
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static inline void
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megasas_fire_cmd_ppc(dma_addr_t frame_phys_addr, u32 frame_count, struct megasas_register_set __iomem *regs)
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{
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writel((frame_phys_addr | (frame_count<<1))|1,
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&(regs)->inbound_queue_port);
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}
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static struct megasas_instance_template megasas_instance_template_ppc = {
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.fire_cmd = megasas_fire_cmd_ppc,
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.enable_intr = megasas_enable_intr_ppc,
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.clear_intr = megasas_clear_intr_ppc,
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.read_fw_status_reg = megasas_read_fw_status_reg_ppc,
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};
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/**
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* This is the end of set of functions & definitions
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* specific to ppc (deviceid : 0x60) controllers
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*/
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/**
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* megasas_disable_intr - Disables interrupts
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* @regs: MFI register set
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@ -1607,7 +1693,17 @@ static int megasas_init_mfi(struct megasas_instance *instance)
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reg_set = instance->reg_set;
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instance->instancet = &megasas_instance_template_xscale;
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switch(instance->pdev->device)
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{
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case PCI_DEVICE_ID_LSI_SAS1078R:
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instance->instancet = &megasas_instance_template_ppc;
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break;
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case PCI_DEVICE_ID_LSI_SAS1064R:
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case PCI_DEVICE_ID_DELL_PERC5:
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default:
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instance->instancet = &megasas_instance_template_xscale;
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break;
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}
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/*
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* We expect the FW state to be READY
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@ -20,7 +20,7 @@
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*/
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#define MEGASAS_VERSION "00.00.02.04"
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#define MEGASAS_RELDATE "Feb 03, 2006"
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#define MEGASAS_EXT_VERSION "Fri Feb 03 14:16:25 PST 2006"
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#define MEGASAS_EXT_VERSION "Fri Feb 03 14:31:44 PST 2006"
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/*
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* =====================================
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* MegaRAID SAS MFI firmware definitions
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@ -553,31 +553,46 @@ struct megasas_ctrl_info {
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#define MFI_OB_INTR_STATUS_MASK 0x00000002
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#define MFI_POLL_TIMEOUT_SECS 10
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#define MFI_REPLY_1078_MESSAGE_INTERRUPT 0x80000000
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#define PCI_DEVICE_ID_LSI_SAS1078R 0x00000060
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struct megasas_register_set {
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u32 reserved_0[4]; /*0000h*/
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u32 reserved_0[4]; /*0000h */
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u32 inbound_msg_0; /*0010h*/
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u32 inbound_msg_1; /*0014h*/
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u32 outbound_msg_0; /*0018h*/
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u32 outbound_msg_1; /*001Ch*/
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u32 inbound_msg_0; /*0010h */
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u32 inbound_msg_1; /*0014h */
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u32 outbound_msg_0; /*0018h */
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u32 outbound_msg_1; /*001Ch */
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u32 inbound_doorbell; /*0020h*/
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u32 inbound_intr_status; /*0024h*/
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u32 inbound_intr_mask; /*0028h*/
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u32 inbound_doorbell; /*0020h */
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u32 inbound_intr_status; /*0024h */
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u32 inbound_intr_mask; /*0028h */
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u32 outbound_doorbell; /*002Ch*/
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u32 outbound_intr_status; /*0030h*/
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u32 outbound_intr_mask; /*0034h*/
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u32 outbound_doorbell; /*002Ch */
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u32 outbound_intr_status; /*0030h */
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u32 outbound_intr_mask; /*0034h */
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u32 reserved_1[2]; /*0038h*/
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u32 reserved_1[2]; /*0038h */
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u32 inbound_queue_port; /*0040h*/
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u32 outbound_queue_port; /*0044h*/
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u32 inbound_queue_port; /*0040h */
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u32 outbound_queue_port; /*0044h */
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u32 reserved_2[22]; /*0048h*/
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u32 reserved_2; /*004Ch */
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u32 outbound_doorbell_clear; /*00A0h*/
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u32 index_registers[1004]; /*0050h */
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u32 reserved_3[3]; /*00A4h*/
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u32 outbound_scratch_pad ; /*00B0h*/
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u32 reserved_4[3]; /*00B4h*/
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u32 inbound_low_queue_port ; /*00C0h*/
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u32 inbound_high_queue_port ; /*00C4h*/
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u32 reserved_5; /*00C8h*/
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u32 index_registers[820]; /*00CCh*/
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} __attribute__ ((packed));
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