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arm64: tegra: Add ethernet controller on Tegra194

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The Tegra194 contains the same ethernet controller as the Tegra186.
Add the device tree node for it, and correspondingly the PHY node
on the board device tree.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
This commit is contained in:
Mikko Perttunen 2018-06-20 15:54:06 +03:00 committed by Thierry Reding
parent ef633bfc21
commit f89b58ce71
2 changed files with 42 additions and 0 deletions
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20
arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi
View file

@ -27,6 +27,26 @@
};
cbb {
ethernet@2490000 {
status = "okay";
phy-reset-gpios = <&gpio TEGRA194_MAIN_GPIO(G, 5) GPIO_ACTIVE_LOW>;
phy-handle = <&phy>;
phy-mode = "rgmii";
mdio {
#address-cells = <1>;
#size-cells = <0>;
phy: phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x0>;
interrupt-parent = <&gpio>;
interrupts = <TEGRA194_MAIN_GPIO(G, 4) IRQ_TYPE_LEVEL_LOW>;
};
};
};
serial@3110000 {
status = "okay";
};

22
arch/arm64/boot/dts/nvidia/tegra194.dtsi
View file

@ -35,6 +35,28 @@
gpio-controller;
};
ethernet@2490000 {
compatible = "nvidia,tegra186-eqos",
"snps,dwc-qos-ethernet-4.10";
reg = <0x02490000 0x10000>;
interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA194_CLK_AXI_CBB>,
<&bpmp TEGRA194_CLK_EQOS_AXI>,
<&bpmp TEGRA194_CLK_EQOS_RX>,
<&bpmp TEGRA194_CLK_EQOS_TX>,
<&bpmp TEGRA194_CLK_EQOS_PTP_REF>;
clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref";
resets = <&bpmp TEGRA194_RESET_EQOS>;
reset-names = "eqos";
status = "disabled";
snps,write-requests = <1>;
snps,read-requests = <3>;
snps,burst-map = <0x7>;
snps,txpbl = <16>;
snps,rxpbl = <8>;
};
uarta: serial@3100000 {
compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
reg = <0x03100000 0x40>;