[MIPS] rbtx4938: Convert SPI codes to use generic SPI drivers
Use rtc-rs5c348 and at25 spi protocol driver and spi_txx9 spi controller driver instead of platform dependent codes. This patch also removes dependencies to old RTC interfaces such as rtc_mips_get_time, etc. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Atsushi Nemoto
Ralf Baechle
parent
3896b05418
commit
f74cf6ff99
10 changed files with 226 additions and 702 deletions
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@ -966,8 +966,20 @@ CONFIG_LEGACY_PTY_COUNT=256
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#
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# SPI support
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#
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# CONFIG_SPI is not set
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# CONFIG_SPI_MASTER is not set
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CONFIG_SPI=y
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CONFIG_SPI_MASTER=y
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#
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# SPI Master Controller Drivers
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#
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# CONFIG_SPI_BITBANG is not set
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CONFIG_SPI_TXX9=y
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#
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# SPI Protocol Masters
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#
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CONFIG_SPI_AT25=y
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# CONFIG_SPI_SPIDEV is not set
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#
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# Dallas's 1-wire bus
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@ -1207,7 +1219,43 @@ CONFIG_USB_MON=y
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#
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# Real Time Clock
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#
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# CONFIG_RTC_CLASS is not set
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CONFIG_RTC_LIB=y
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CONFIG_RTC_CLASS=y
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CONFIG_RTC_HCTOSYS=y
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CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
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# CONFIG_RTC_DEBUG is not set
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#
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# RTC interfaces
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#
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CONFIG_RTC_INTF_SYSFS=y
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CONFIG_RTC_INTF_PROC=y
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CONFIG_RTC_INTF_DEV=y
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CONFIG_RTC_INTF_DEV_UIE_EMUL=y
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# CONFIG_RTC_DRV_TEST is not set
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#
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# I2C RTC drivers
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#
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#
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# SPI RTC drivers
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#
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CONFIG_RTC_DRV_RS5C348=y
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# CONFIG_RTC_DRV_MAX6902 is not set
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#
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# Platform RTC drivers
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#
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# CONFIG_RTC_DRV_CMOS is not set
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# CONFIG_RTC_DRV_DS1553 is not set
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# CONFIG_RTC_DRV_DS1742 is not set
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# CONFIG_RTC_DRV_M48T86 is not set
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# CONFIG_RTC_DRV_V3020 is not set
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#
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# on-CPU RTC drivers
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#
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#
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# DMA Engine support
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@ -6,6 +6,6 @@
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# unless it's something special (ie not a .c file).
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#
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obj-y += prom.o setup.o irq.o rtc_rx5c348.o
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obj-y += prom.o setup.o irq.o
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obj-$(CONFIG_KGDB) += dbgio.o
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@ -1,192 +0,0 @@
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/*
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* RTC routines for RICOH Rx5C348 SPI chip.
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* Copyright (C) 2000-2001 Toshiba Corporation
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*
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* 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
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* terms of the GNU General Public License version 2. This program is
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* licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*
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* Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/string.h>
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#include <linux/rtc.h>
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#include <linux/time.h>
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#include <linux/bcd.h>
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#include <asm/time.h>
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#include <asm/tx4938/spi.h>
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#define EPOCH 2000
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/* registers */
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#define Rx5C348_REG_SECOND 0
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#define Rx5C348_REG_MINUTE 1
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#define Rx5C348_REG_HOUR 2
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#define Rx5C348_REG_WEEK 3
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#define Rx5C348_REG_DAY 4
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#define Rx5C348_REG_MONTH 5
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#define Rx5C348_REG_YEAR 6
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#define Rx5C348_REG_ADJUST 7
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#define Rx5C348_REG_ALARM_W_MIN 8
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#define Rx5C348_REG_ALARM_W_HOUR 9
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#define Rx5C348_REG_ALARM_W_WEEK 10
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#define Rx5C348_REG_ALARM_D_MIN 11
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#define Rx5C348_REG_ALARM_D_HOUR 12
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#define Rx5C348_REG_CTL1 14
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#define Rx5C348_REG_CTL2 15
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/* register bits */
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#define Rx5C348_BIT_PM 0x20 /* REG_HOUR */
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#define Rx5C348_BIT_Y2K 0x80 /* REG_MONTH */
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#define Rx5C348_BIT_24H 0x20 /* REG_CTL1 */
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#define Rx5C348_BIT_XSTP 0x10 /* REG_CTL2 */
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/* commands */
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#define Rx5C348_CMD_W(addr) (((addr) << 4) | 0x08) /* single write */
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#define Rx5C348_CMD_R(addr) (((addr) << 4) | 0x0c) /* single read */
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#define Rx5C348_CMD_MW(addr) (((addr) << 4) | 0x00) /* burst write */
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#define Rx5C348_CMD_MR(addr) (((addr) << 4) | 0x04) /* burst read */
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static struct spi_dev_desc srtc_dev_desc = {
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.baud = 1000000, /* 1.0Mbps @ Vdd 2.0V */
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.tcss = 31,
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.tcsh = 1,
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.tcsr = 62,
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/* 31us for Tcss (62us for Tcsr) is required for carry operation) */
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.byteorder = 1, /* MSB-First */
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.polarity = 0, /* High-Active */
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.phase = 1, /* Shift-Then-Sample */
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};
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static int srtc_chipid;
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static int srtc_24h;
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static inline int
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spi_rtc_io(unsigned char *inbuf, unsigned char *outbuf, unsigned int count)
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{
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unsigned char *inbufs[1], *outbufs[1];
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unsigned int incounts[2], outcounts[2];
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inbufs[0] = inbuf;
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incounts[0] = count;
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incounts[1] = 0;
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outbufs[0] = outbuf;
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outcounts[0] = count;
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outcounts[1] = 0;
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return txx9_spi_io(srtc_chipid, &srtc_dev_desc,
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inbufs, incounts, outbufs, outcounts, 0);
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}
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/* RTC-dependent code for time.c */
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static int
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rtc_rx5c348_set_time(unsigned long t)
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{
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unsigned char inbuf[8];
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struct rtc_time tm;
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u8 year, month, day, hour, minute, second, century;
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/* convert */
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to_tm(t, &tm);
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year = tm.tm_year % 100;
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month = tm.tm_mon+1; /* tm_mon starts from 0 to 11 */
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day = tm.tm_mday;
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hour = tm.tm_hour;
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minute = tm.tm_min;
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second = tm.tm_sec;
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century = tm.tm_year / 100;
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inbuf[0] = Rx5C348_CMD_MW(Rx5C348_REG_SECOND);
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BIN_TO_BCD(second);
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inbuf[1] = second;
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BIN_TO_BCD(minute);
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inbuf[2] = minute;
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if (srtc_24h) {
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BIN_TO_BCD(hour);
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inbuf[3] = hour;
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} else {
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/* hour 0 is AM12, noon is PM12 */
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inbuf[3] = 0;
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if (hour >= 12)
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inbuf[3] = Rx5C348_BIT_PM;
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hour = (hour + 11) % 12 + 1;
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BIN_TO_BCD(hour);
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inbuf[3] |= hour;
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}
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inbuf[4] = 0; /* ignore week */
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BIN_TO_BCD(day);
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inbuf[5] = day;
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BIN_TO_BCD(month);
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inbuf[6] = month;
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if (century >= 20)
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inbuf[6] |= Rx5C348_BIT_Y2K;
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BIN_TO_BCD(year);
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inbuf[7] = year;
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/* write in one transfer to avoid data inconsistency */
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return spi_rtc_io(inbuf, NULL, 8);
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}
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static unsigned long
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rtc_rx5c348_get_time(void)
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{
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unsigned char inbuf[8], outbuf[8];
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unsigned int year, month, day, hour, minute, second;
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inbuf[0] = Rx5C348_CMD_MR(Rx5C348_REG_SECOND);
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memset(inbuf + 1, 0, 7);
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/* read in one transfer to avoid data inconsistency */
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if (spi_rtc_io(inbuf, outbuf, 8))
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return 0;
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second = outbuf[1];
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BCD_TO_BIN(second);
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minute = outbuf[2];
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BCD_TO_BIN(minute);
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if (srtc_24h) {
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hour = outbuf[3];
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BCD_TO_BIN(hour);
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} else {
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hour = outbuf[3] & ~Rx5C348_BIT_PM;
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BCD_TO_BIN(hour);
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hour %= 12;
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if (outbuf[3] & Rx5C348_BIT_PM)
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hour += 12;
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}
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day = outbuf[5];
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BCD_TO_BIN(day);
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month = outbuf[6] & ~Rx5C348_BIT_Y2K;
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BCD_TO_BIN(month);
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year = outbuf[7];
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BCD_TO_BIN(year);
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year += EPOCH;
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return mktime(year, month, day, hour, minute, second);
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}
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void __init
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rtc_rx5c348_init(int chipid)
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{
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unsigned char inbuf[2], outbuf[2];
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srtc_chipid = chipid;
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/* turn on RTC if it is not on */
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inbuf[0] = Rx5C348_CMD_R(Rx5C348_REG_CTL2);
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inbuf[1] = 0;
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spi_rtc_io(inbuf, outbuf, 2);
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if (outbuf[1] & Rx5C348_BIT_XSTP) {
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inbuf[0] = Rx5C348_CMD_W(Rx5C348_REG_CTL2);
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inbuf[1] = 0;
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spi_rtc_io(inbuf, NULL, 2);
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}
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inbuf[0] = Rx5C348_CMD_R(Rx5C348_REG_CTL1);
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inbuf[1] = 0;
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spi_rtc_io(inbuf, outbuf, 2);
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if (outbuf[1] & Rx5C348_BIT_24H)
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srtc_24h = 1;
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/* set the function pointers */
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rtc_mips_get_time = rtc_rx5c348_get_time;
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rtc_mips_set_time = rtc_rx5c348_set_time;
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}
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@ -6,4 +6,4 @@
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# unless it's something special (ie not a .c file).
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#
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obj-y += prom.o setup.o irq.o spi_eeprom.o spi_txx9.o
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obj-y += prom.o setup.o irq.o spi_eeprom.o
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@ -165,8 +165,6 @@ toshiba_rbtx4938_irq_ioc_disable(unsigned int irq)
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TX4938_RD08(TOSHIBA_RBTX4938_IOC_INTR_ENAB);
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}
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extern void __init txx9_spi_irqinit(int irc_irq);
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void __init arch_init_irq(void)
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{
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extern void tx4938_irq_init(void);
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@ -185,9 +183,5 @@ void __init arch_init_irq(void)
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/* Onboard 10M Ether: High Active */
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TX4938_WR(TX4938_MKA(TX4938_IRC_IRDM0), 0x00000040);
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if (tx4938_ccfgptr->pcfg & TX4938_PCFG_SPI_SEL) {
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txx9_spi_irqinit(RBTX4938_IRQ_IRC_SPI);
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}
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wbflush();
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}
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@ -14,13 +14,13 @@
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#include <linux/init.h>
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#include <linux/types.h>
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#include <linux/ioport.h>
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#include <linux/proc_fs.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/console.h>
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#include <linux/pci.h>
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#include <linux/pm.h>
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#include <linux/platform_device.h>
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#include <linux/clk.h>
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#include <asm/wbflush.h>
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#include <asm/reboot.h>
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@ -29,13 +29,15 @@
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#include <asm/uaccess.h>
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#include <asm/io.h>
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#include <asm/bootinfo.h>
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#include <asm/gpio.h>
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#include <asm/tx4938/rbtx4938.h>
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#ifdef CONFIG_SERIAL_TXX9
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#include <linux/tty.h>
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#include <linux/serial.h>
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#include <linux/serial_core.h>
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#endif
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#include <linux/spi/spi.h>
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#include <asm/tx4938/spi.h>
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#include <asm/gpio.h>
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extern void rbtx4938_time_init(void) __init;
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extern char * __init prom_getcmdline(void);
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@ -575,44 +577,33 @@ arch_initcall(tx4938_pcibios_init);
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#define SEEPROM3_CS 1 /* IOC */
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#define SRTC_CS 2 /* IOC */
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static int rbtx4938_spi_cs_func(int chipid, int on)
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#ifdef CONFIG_PCI
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static unsigned char rbtx4938_ethaddr[17];
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static int __init rbtx4938_ethaddr_init(void)
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{
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unsigned char bit;
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switch (chipid) {
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case RBTX4938_SEEPROM1_CHIPID:
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if (on)
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tx4938_pioptr->dout &= ~(1 << SEEPROM1_CS);
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else
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tx4938_pioptr->dout |= (1 << SEEPROM1_CS);
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return 0;
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break;
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case RBTX4938_SEEPROM2_CHIPID:
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bit = (1 << SEEPROM2_CS);
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break;
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case RBTX4938_SEEPROM3_CHIPID:
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bit = (1 << SEEPROM3_CS);
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break;
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case RBTX4938_SRTC_CHIPID:
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bit = (1 << SRTC_CS);
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break;
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default:
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return -ENODEV;
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unsigned char sum;
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int i;
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/* 0-3: "MAC\0", 4-9:eth0, 10-15:eth1, 16:sum */
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if (spi_eeprom_read(SEEPROM1_CS, 0,
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rbtx4938_ethaddr, sizeof(rbtx4938_ethaddr)))
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printk(KERN_ERR "seeprom: read error.\n");
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else {
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unsigned char *dat = rbtx4938_ethaddr;
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if (strcmp(dat, "MAC") != 0)
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printk(KERN_WARNING "seeprom: bad signature.\n");
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for (i = 0, sum = 0; i < sizeof(dat); i++)
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sum += dat[i];
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if (sum)
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printk(KERN_WARNING "seeprom: bad checksum.\n");
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}
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/* bit1,2,4 are low active, bit3 is high active */
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*rbtx4938_spics_ptr =
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(*rbtx4938_spics_ptr & ~bit) |
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((on ? (bit ^ 0x0b) : ~(bit ^ 0x0b)) & bit);
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return 0;
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}
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#ifdef CONFIG_PCI
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extern int spi_eeprom_read(int chipid, int address, unsigned char *buf, int len);
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device_initcall(rbtx4938_ethaddr_init);
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int rbtx4938_get_tx4938_ethaddr(struct pci_dev *dev, unsigned char *addr)
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{
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struct pci_controller *channel = (struct pci_controller *)dev->bus->sysdata;
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static unsigned char dat[17];
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static int read_dat = 0;
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int ch = 0;
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if (channel != &tx4938_pci_controller[1])
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@ -628,29 +619,11 @@ int rbtx4938_get_tx4938_ethaddr(struct pci_dev *dev, unsigned char *addr)
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default:
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return -ENODEV;
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}
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if (!read_dat) {
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unsigned char sum;
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int i;
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read_dat = 1;
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/* 0-3: "MAC\0", 4-9:eth0, 10-15:eth1, 16:sum */
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if (spi_eeprom_read(RBTX4938_SEEPROM1_CHIPID,
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0, dat, sizeof(dat))) {
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printk(KERN_ERR "seeprom: read error.\n");
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} else {
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if (strcmp(dat, "MAC") != 0)
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printk(KERN_WARNING "seeprom: bad signature.\n");
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for (i = 0, sum = 0; i < sizeof(dat); i++)
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sum += dat[i];
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if (sum)
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printk(KERN_WARNING "seeprom: bad checksum.\n");
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}
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}
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memcpy(addr, &dat[4 + 6 * ch], 6);
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memcpy(addr, &rbtx4938_ethaddr[4 + 6 * ch], 6);
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return 0;
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}
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#endif /* CONFIG_PCI */
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extern void __init txx9_spi_init(unsigned long base, int (*cs_func)(int chipid, int on));
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static void __init rbtx4938_spi_setup(void)
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{
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/* set SPI_SEL */
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@ -658,7 +631,6 @@ static void __init rbtx4938_spi_setup(void)
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/* chip selects for SPI devices */
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tx4938_pioptr->dout |= (1 << SEEPROM1_CS);
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tx4938_pioptr->dir |= (1 << SEEPROM1_CS);
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txx9_spi_init(TX4938_SPI_REG, rbtx4938_spi_cs_func);
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}
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static struct resource rbtx4938_fpga_resource;
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@ -897,10 +869,8 @@ void tx4938_report_pcic_status(void)
|
|||
/* We use onchip r4k counter or TMR timer as our system wide timer
|
||||
* interrupt running at 100HZ. */
|
||||
|
||||
extern void __init rtc_rx5c348_init(int chipid);
|
||||
void __init rbtx4938_time_init(void)
|
||||
{
|
||||
rtc_rx5c348_init(RBTX4938_SRTC_CHIPID);
|
||||
mips_hpt_frequency = txx9_cpu_clock / 2;
|
||||
}
|
||||
|
||||
|
|
@ -1017,29 +987,6 @@ void __init toshiba_rbtx4938_setup(void)
|
|||
*rbtx4938_dipsw_ptr, *rbtx4938_bdipsw_ptr);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PROC_FS
|
||||
extern void spi_eeprom_proc_create(struct proc_dir_entry *dir, int chipid);
|
||||
static int __init tx4938_spi_proc_setup(void)
|
||||
{
|
||||
struct proc_dir_entry *tx4938_spi_eeprom_dir;
|
||||
|
||||
tx4938_spi_eeprom_dir = proc_mkdir("spi_eeprom", 0);
|
||||
|
||||
if (!tx4938_spi_eeprom_dir)
|
||||
return -ENOMEM;
|
||||
|
||||
/* don't allow user access to RBTX4938_SEEPROM1_CHIPID
|
||||
* as it contains eth0 and eth1 MAC addresses
|
||||
*/
|
||||
spi_eeprom_proc_create(tx4938_spi_eeprom_dir, RBTX4938_SEEPROM2_CHIPID);
|
||||
spi_eeprom_proc_create(tx4938_spi_eeprom_dir, RBTX4938_SEEPROM3_CHIPID);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
__initcall(tx4938_spi_proc_setup);
|
||||
#endif
|
||||
|
||||
static int __init rbtx4938_ne_init(void)
|
||||
{
|
||||
struct resource res[] = {
|
||||
|
|
@ -1161,3 +1108,73 @@ void gpio_set_value(unsigned gpio, int value)
|
|||
else
|
||||
rbtx4938_spi_gpio_set(gpio, value);
|
||||
}
|
||||
|
||||
/* SPI support */
|
||||
|
||||
static void __init txx9_spi_init(unsigned long base, int irq)
|
||||
{
|
||||
struct resource res[] = {
|
||||
{
|
||||
.start = base,
|
||||
.end = base + 0x20 - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
.parent = &tx4938_reg_resource,
|
||||
}, {
|
||||
.start = irq,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
platform_device_register_simple("txx9spi", 0,
|
||||
res, ARRAY_SIZE(res));
|
||||
}
|
||||
|
||||
static int __init rbtx4938_spi_init(void)
|
||||
{
|
||||
struct spi_board_info srtc_info = {
|
||||
.modalias = "rs5c348",
|
||||
.max_speed_hz = 1000000, /* 1.0Mbps @ Vdd 2.0V */
|
||||
.bus_num = 0,
|
||||
.chip_select = 16 + SRTC_CS,
|
||||
/* Mode 1 (High-Active, Shift-Then-Sample), High Avtive CS */
|
||||
.mode = SPI_MODE_1 | SPI_CS_HIGH,
|
||||
};
|
||||
spi_register_board_info(&srtc_info, 1);
|
||||
spi_eeprom_register(SEEPROM1_CS);
|
||||
spi_eeprom_register(16 + SEEPROM2_CS);
|
||||
spi_eeprom_register(16 + SEEPROM3_CS);
|
||||
txx9_spi_init(TX4938_SPI_REG & 0xfffffffffULL, RBTX4938_IRQ_IRC_SPI);
|
||||
return 0;
|
||||
}
|
||||
arch_initcall(rbtx4938_spi_init);
|
||||
|
||||
/* Minimum CLK support */
|
||||
|
||||
struct clk *clk_get(struct device *dev, const char *id)
|
||||
{
|
||||
if (!strcmp(id, "spi-baseclk"))
|
||||
return (struct clk *)(txx9_gbus_clock / 2 / 4);
|
||||
return ERR_PTR(-ENOENT);
|
||||
}
|
||||
EXPORT_SYMBOL(clk_get);
|
||||
|
||||
int clk_enable(struct clk *clk)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL(clk_enable);
|
||||
|
||||
void clk_disable(struct clk *clk)
|
||||
{
|
||||
}
|
||||
EXPORT_SYMBOL(clk_disable);
|
||||
|
||||
unsigned long clk_get_rate(struct clk *clk)
|
||||
{
|
||||
return (unsigned long)clk;
|
||||
}
|
||||
EXPORT_SYMBOL(clk_get_rate);
|
||||
|
||||
void clk_put(struct clk *clk)
|
||||
{
|
||||
}
|
||||
EXPORT_SYMBOL(clk_put);
|
||||
|
|
|
|||
|
|
@ -10,209 +10,90 @@
|
|||
* Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
|
||||
*/
|
||||
#include <linux/init.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/proc_fs.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/spi/spi.h>
|
||||
#include <linux/spi/eeprom.h>
|
||||
#include <asm/tx4938/spi.h>
|
||||
#include <asm/tx4938/tx4938.h>
|
||||
|
||||
/* ATMEL 250x0 instructions */
|
||||
#define ATMEL_WREN 0x06
|
||||
#define ATMEL_WRDI 0x04
|
||||
#define ATMEL_RDSR 0x05
|
||||
#define ATMEL_WRSR 0x01
|
||||
#define ATMEL_READ 0x03
|
||||
#define ATMEL_WRITE 0x02
|
||||
#define AT250X0_PAGE_SIZE 8
|
||||
|
||||
#define ATMEL_SR_BSY 0x01
|
||||
#define ATMEL_SR_WEN 0x02
|
||||
#define ATMEL_SR_BP0 0x04
|
||||
#define ATMEL_SR_BP1 0x08
|
||||
/* register board information for at25 driver */
|
||||
int __init spi_eeprom_register(int chipid)
|
||||
{
|
||||
static struct spi_eeprom eeprom = {
|
||||
.name = "at250x0",
|
||||
.byte_len = 128,
|
||||
.page_size = AT250X0_PAGE_SIZE,
|
||||
.flags = EE_ADDR1,
|
||||
};
|
||||
struct spi_board_info info = {
|
||||
.modalias = "at25",
|
||||
.max_speed_hz = 1500000, /* 1.5Mbps */
|
||||
.bus_num = 0,
|
||||
.chip_select = chipid,
|
||||
.platform_data = &eeprom,
|
||||
/* Mode 0: High-Active, Sample-Then-Shift */
|
||||
};
|
||||
|
||||
DEFINE_SPINLOCK(spi_eeprom_lock);
|
||||
return spi_register_board_info(&info, 1);
|
||||
}
|
||||
|
||||
static struct spi_dev_desc seeprom_dev_desc = {
|
||||
.baud = 1500000, /* 1.5Mbps */
|
||||
.tcss = 1,
|
||||
.tcsh = 1,
|
||||
.tcsr = 1,
|
||||
.byteorder = 1, /* MSB-First */
|
||||
.polarity = 0, /* High-Active */
|
||||
.phase = 0, /* Sample-Then-Shift */
|
||||
/* simple temporary spi driver to provide early access to seeprom. */
|
||||
|
||||
static struct read_param {
|
||||
int chipid;
|
||||
int address;
|
||||
unsigned char *buf;
|
||||
int len;
|
||||
} *read_param;
|
||||
|
||||
static int __init early_seeprom_probe(struct spi_device *spi)
|
||||
{
|
||||
int stat = 0;
|
||||
u8 cmd[2];
|
||||
int len = read_param->len;
|
||||
char *buf = read_param->buf;
|
||||
int address = read_param->address;
|
||||
|
||||
dev_info(&spi->dev, "spiclk %u KHz.\n",
|
||||
(spi->max_speed_hz + 500) / 1000);
|
||||
if (read_param->chipid != spi->chip_select)
|
||||
return -ENODEV;
|
||||
while (len > 0) {
|
||||
/* spi_write_then_read can only work with small chunk */
|
||||
int c = len < AT250X0_PAGE_SIZE ? len : AT250X0_PAGE_SIZE;
|
||||
cmd[0] = 0x03; /* AT25_READ */
|
||||
cmd[1] = address;
|
||||
stat = spi_write_then_read(spi, cmd, sizeof(cmd), buf, c);
|
||||
buf += c;
|
||||
len -= c;
|
||||
address += c;
|
||||
}
|
||||
return stat;
|
||||
}
|
||||
|
||||
static struct spi_driver early_seeprom_driver __initdata = {
|
||||
.driver = {
|
||||
.name = "at25",
|
||||
.owner = THIS_MODULE,
|
||||
},
|
||||
.probe = early_seeprom_probe,
|
||||
};
|
||||
static inline int
|
||||
spi_eeprom_io(int chipid,
|
||||
unsigned char **inbufs, unsigned int *incounts,
|
||||
unsigned char **outbufs, unsigned int *outcounts)
|
||||
|
||||
int __init spi_eeprom_read(int chipid, int address,
|
||||
unsigned char *buf, int len)
|
||||
{
|
||||
return txx9_spi_io(chipid, &seeprom_dev_desc,
|
||||
inbufs, incounts, outbufs, outcounts, 0);
|
||||
int ret;
|
||||
struct read_param param = {
|
||||
.chipid = chipid,
|
||||
.address = address,
|
||||
.buf = buf,
|
||||
.len = len
|
||||
};
|
||||
|
||||
read_param = ¶m;
|
||||
ret = spi_register_driver(&early_seeprom_driver);
|
||||
if (!ret)
|
||||
spi_unregister_driver(&early_seeprom_driver);
|
||||
return ret;
|
||||
}
|
||||
|
||||
int spi_eeprom_write_enable(int chipid, int enable)
|
||||
{
|
||||
unsigned char inbuf[1];
|
||||
unsigned char *inbufs[1];
|
||||
unsigned int incounts[2];
|
||||
unsigned long flags;
|
||||
int stat;
|
||||
inbuf[0] = enable ? ATMEL_WREN : ATMEL_WRDI;
|
||||
inbufs[0] = inbuf;
|
||||
incounts[0] = sizeof(inbuf);
|
||||
incounts[1] = 0;
|
||||
spin_lock_irqsave(&spi_eeprom_lock, flags);
|
||||
stat = spi_eeprom_io(chipid, inbufs, incounts, NULL, NULL);
|
||||
spin_unlock_irqrestore(&spi_eeprom_lock, flags);
|
||||
return stat;
|
||||
}
|
||||
|
||||
static int spi_eeprom_read_status_nolock(int chipid)
|
||||
{
|
||||
unsigned char inbuf[2], outbuf[2];
|
||||
unsigned char *inbufs[1], *outbufs[1];
|
||||
unsigned int incounts[2], outcounts[2];
|
||||
int stat;
|
||||
inbuf[0] = ATMEL_RDSR;
|
||||
inbuf[1] = 0;
|
||||
inbufs[0] = inbuf;
|
||||
incounts[0] = sizeof(inbuf);
|
||||
incounts[1] = 0;
|
||||
outbufs[0] = outbuf;
|
||||
outcounts[0] = sizeof(outbuf);
|
||||
outcounts[1] = 0;
|
||||
stat = spi_eeprom_io(chipid, inbufs, incounts, outbufs, outcounts);
|
||||
if (stat < 0)
|
||||
return stat;
|
||||
return outbuf[1];
|
||||
}
|
||||
|
||||
int spi_eeprom_read_status(int chipid)
|
||||
{
|
||||
unsigned long flags;
|
||||
int stat;
|
||||
spin_lock_irqsave(&spi_eeprom_lock, flags);
|
||||
stat = spi_eeprom_read_status_nolock(chipid);
|
||||
spin_unlock_irqrestore(&spi_eeprom_lock, flags);
|
||||
return stat;
|
||||
}
|
||||
|
||||
int spi_eeprom_read(int chipid, int address, unsigned char *buf, int len)
|
||||
{
|
||||
unsigned char inbuf[2];
|
||||
unsigned char *inbufs[2], *outbufs[2];
|
||||
unsigned int incounts[2], outcounts[3];
|
||||
unsigned long flags;
|
||||
int stat;
|
||||
inbuf[0] = ATMEL_READ;
|
||||
inbuf[1] = address;
|
||||
inbufs[0] = inbuf;
|
||||
inbufs[1] = NULL;
|
||||
incounts[0] = sizeof(inbuf);
|
||||
incounts[1] = 0;
|
||||
outbufs[0] = NULL;
|
||||
outbufs[1] = buf;
|
||||
outcounts[0] = 2;
|
||||
outcounts[1] = len;
|
||||
outcounts[2] = 0;
|
||||
spin_lock_irqsave(&spi_eeprom_lock, flags);
|
||||
stat = spi_eeprom_io(chipid, inbufs, incounts, outbufs, outcounts);
|
||||
spin_unlock_irqrestore(&spi_eeprom_lock, flags);
|
||||
return stat;
|
||||
}
|
||||
|
||||
int spi_eeprom_write(int chipid, int address, unsigned char *buf, int len)
|
||||
{
|
||||
unsigned char inbuf[2];
|
||||
unsigned char *inbufs[2];
|
||||
unsigned int incounts[3];
|
||||
unsigned long flags;
|
||||
int i, stat;
|
||||
|
||||
if (address / 8 != (address + len - 1) / 8)
|
||||
return -EINVAL;
|
||||
stat = spi_eeprom_write_enable(chipid, 1);
|
||||
if (stat < 0)
|
||||
return stat;
|
||||
stat = spi_eeprom_read_status(chipid);
|
||||
if (stat < 0)
|
||||
return stat;
|
||||
if (!(stat & ATMEL_SR_WEN))
|
||||
return -EPERM;
|
||||
|
||||
inbuf[0] = ATMEL_WRITE;
|
||||
inbuf[1] = address;
|
||||
inbufs[0] = inbuf;
|
||||
inbufs[1] = buf;
|
||||
incounts[0] = sizeof(inbuf);
|
||||
incounts[1] = len;
|
||||
incounts[2] = 0;
|
||||
spin_lock_irqsave(&spi_eeprom_lock, flags);
|
||||
stat = spi_eeprom_io(chipid, inbufs, incounts, NULL, NULL);
|
||||
if (stat < 0)
|
||||
goto unlock_return;
|
||||
|
||||
/* write start. max 10ms */
|
||||
for (i = 10; i > 0; i--) {
|
||||
int stat = spi_eeprom_read_status_nolock(chipid);
|
||||
if (stat < 0)
|
||||
goto unlock_return;
|
||||
if (!(stat & ATMEL_SR_BSY))
|
||||
break;
|
||||
mdelay(1);
|
||||
}
|
||||
spin_unlock_irqrestore(&spi_eeprom_lock, flags);
|
||||
if (i == 0)
|
||||
return -EIO;
|
||||
return len;
|
||||
unlock_return:
|
||||
spin_unlock_irqrestore(&spi_eeprom_lock, flags);
|
||||
return stat;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PROC_FS
|
||||
#define MAX_SIZE 0x80 /* for ATMEL 25010 */
|
||||
static int spi_eeprom_read_proc(char *page, char **start, off_t off,
|
||||
int count, int *eof, void *data)
|
||||
{
|
||||
unsigned int size = MAX_SIZE;
|
||||
if (spi_eeprom_read((int)data, 0, (unsigned char *)page, size) < 0)
|
||||
size = 0;
|
||||
return size;
|
||||
}
|
||||
|
||||
static int spi_eeprom_write_proc(struct file *file, const char *buffer,
|
||||
unsigned long count, void *data)
|
||||
{
|
||||
unsigned int size = MAX_SIZE;
|
||||
int i;
|
||||
if (file->f_pos >= size)
|
||||
return -EIO;
|
||||
if (file->f_pos + count > size)
|
||||
count = size - file->f_pos;
|
||||
for (i = 0; i < count; i += 8) {
|
||||
int len = count - i < 8 ? count - i : 8;
|
||||
if (spi_eeprom_write((int)data, file->f_pos,
|
||||
(unsigned char *)buffer, len) < 0) {
|
||||
count = -EIO;
|
||||
break;
|
||||
}
|
||||
buffer += len;
|
||||
file->f_pos += len;
|
||||
}
|
||||
return count;
|
||||
}
|
||||
|
||||
__init void spi_eeprom_proc_create(struct proc_dir_entry *dir, int chipid)
|
||||
{
|
||||
struct proc_dir_entry *entry;
|
||||
char name[128];
|
||||
sprintf(name, "seeprom-%d", chipid);
|
||||
entry = create_proc_entry(name, 0600, dir);
|
||||
if (entry) {
|
||||
entry->read_proc = spi_eeprom_read_proc;
|
||||
entry->write_proc = spi_eeprom_write_proc;
|
||||
entry->data = (void *)chipid;
|
||||
}
|
||||
}
|
||||
#endif /* CONFIG_PROC_FS */
|
||||
|
|
|
|||
|
|
@ -1,164 +0,0 @@
|
|||
/*
|
||||
* linux/arch/mips/tx4938/toshiba_rbtx4938/spi_txx9.c
|
||||
* Copyright (C) 2000-2001 Toshiba Corporation
|
||||
*
|
||||
* 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
|
||||
* terms of the GNU General Public License version 2. This program is
|
||||
* licensed "as is" without any warranty of any kind, whether express
|
||||
* or implied.
|
||||
*
|
||||
* Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
|
||||
*/
|
||||
#include <linux/init.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/sched.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/wait.h>
|
||||
#include <asm/tx4938/spi.h>
|
||||
#include <asm/tx4938/tx4938.h>
|
||||
|
||||
static int (*txx9_spi_cs_func)(int chipid, int on);
|
||||
static DEFINE_SPINLOCK(txx9_spi_lock);
|
||||
|
||||
extern unsigned int txx9_gbus_clock;
|
||||
|
||||
#define SPI_FIFO_SIZE 4
|
||||
|
||||
void __init txx9_spi_init(unsigned long base, int (*cs_func)(int chipid, int on))
|
||||
{
|
||||
txx9_spi_cs_func = cs_func;
|
||||
/* enter config mode */
|
||||
tx4938_spiptr->mcr = TXx9_SPMCR_CONFIG | TXx9_SPMCR_BCLR;
|
||||
}
|
||||
|
||||
static DECLARE_WAIT_QUEUE_HEAD(txx9_spi_wait);
|
||||
|
||||
static irqreturn_t txx9_spi_interrupt(int irq, void *dev_id)
|
||||
{
|
||||
/* disable rx intr */
|
||||
tx4938_spiptr->cr0 &= ~TXx9_SPCR0_RBSIE;
|
||||
wake_up(&txx9_spi_wait);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static struct irqaction txx9_spi_action = {
|
||||
.handler = txx9_spi_interrupt,
|
||||
.name = "spi",
|
||||
};
|
||||
|
||||
void __init txx9_spi_irqinit(int irc_irq)
|
||||
{
|
||||
setup_irq(irc_irq, &txx9_spi_action);
|
||||
}
|
||||
|
||||
int txx9_spi_io(int chipid, struct spi_dev_desc *desc,
|
||||
unsigned char **inbufs, unsigned int *incounts,
|
||||
unsigned char **outbufs, unsigned int *outcounts,
|
||||
int cansleep)
|
||||
{
|
||||
unsigned int incount, outcount;
|
||||
unsigned char *inp, *outp;
|
||||
int ret;
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&txx9_spi_lock, flags);
|
||||
if ((tx4938_spiptr->mcr & TXx9_SPMCR_OPMODE) == TXx9_SPMCR_ACTIVE) {
|
||||
spin_unlock_irqrestore(&txx9_spi_lock, flags);
|
||||
return -EBUSY;
|
||||
}
|
||||
/* enter config mode */
|
||||
tx4938_spiptr->mcr = TXx9_SPMCR_CONFIG | TXx9_SPMCR_BCLR;
|
||||
tx4938_spiptr->cr0 =
|
||||
(desc->byteorder ? TXx9_SPCR0_SBOS : 0) |
|
||||
(desc->polarity ? TXx9_SPCR0_SPOL : 0) |
|
||||
(desc->phase ? TXx9_SPCR0_SPHA : 0) |
|
||||
0x08;
|
||||
tx4938_spiptr->cr1 =
|
||||
(((TXX9_IMCLK + desc->baud) / (2 * desc->baud) - 1) << 8) |
|
||||
0x08 /* 8 bit only */;
|
||||
/* enter active mode */
|
||||
tx4938_spiptr->mcr = TXx9_SPMCR_ACTIVE;
|
||||
spin_unlock_irqrestore(&txx9_spi_lock, flags);
|
||||
|
||||
/* CS ON */
|
||||
if ((ret = txx9_spi_cs_func(chipid, 1)) < 0) {
|
||||
spin_unlock_irqrestore(&txx9_spi_lock, flags);
|
||||
return ret;
|
||||
}
|
||||
udelay(desc->tcss);
|
||||
|
||||
/* do scatter IO */
|
||||
inp = inbufs ? *inbufs : NULL;
|
||||
outp = outbufs ? *outbufs : NULL;
|
||||
incount = 0;
|
||||
outcount = 0;
|
||||
while (1) {
|
||||
unsigned char data;
|
||||
unsigned int count;
|
||||
int i;
|
||||
if (!incount) {
|
||||
incount = incounts ? *incounts++ : 0;
|
||||
inp = (incount && inbufs) ? *inbufs++ : NULL;
|
||||
}
|
||||
if (!outcount) {
|
||||
outcount = outcounts ? *outcounts++ : 0;
|
||||
outp = (outcount && outbufs) ? *outbufs++ : NULL;
|
||||
}
|
||||
if (!inp && !outp)
|
||||
break;
|
||||
count = SPI_FIFO_SIZE;
|
||||
if (incount)
|
||||
count = min(count, incount);
|
||||
if (outcount)
|
||||
count = min(count, outcount);
|
||||
|
||||
/* now tx must be idle... */
|
||||
while (!(tx4938_spiptr->sr & TXx9_SPSR_SIDLE))
|
||||
;
|
||||
|
||||
tx4938_spiptr->cr0 =
|
||||
(tx4938_spiptr->cr0 & ~TXx9_SPCR0_RXIFL_MASK) |
|
||||
((count - 1) << 12);
|
||||
if (cansleep) {
|
||||
/* enable rx intr */
|
||||
tx4938_spiptr->cr0 |= TXx9_SPCR0_RBSIE;
|
||||
}
|
||||
/* send */
|
||||
for (i = 0; i < count; i++)
|
||||
tx4938_spiptr->dr = inp ? *inp++ : 0;
|
||||
/* wait all rx data */
|
||||
if (cansleep) {
|
||||
wait_event(txx9_spi_wait,
|
||||
tx4938_spiptr->sr & TXx9_SPSR_SRRDY);
|
||||
} else {
|
||||
while (!(tx4938_spiptr->sr & TXx9_SPSR_RBSI))
|
||||
;
|
||||
}
|
||||
/* receive */
|
||||
for (i = 0; i < count; i++) {
|
||||
data = tx4938_spiptr->dr;
|
||||
if (outp)
|
||||
*outp++ = data;
|
||||
}
|
||||
if (incount)
|
||||
incount -= count;
|
||||
if (outcount)
|
||||
outcount -= count;
|
||||
}
|
||||
|
||||
/* CS OFF */
|
||||
udelay(desc->tcsh);
|
||||
txx9_spi_cs_func(chipid, 0);
|
||||
udelay(desc->tcsr);
|
||||
|
||||
spin_lock_irqsave(&txx9_spi_lock, flags);
|
||||
/* enter config mode */
|
||||
tx4938_spiptr->mcr = TXx9_SPMCR_CONFIG | TXx9_SPMCR_BCLR;
|
||||
spin_unlock_irqrestore(&txx9_spi_lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -105,12 +105,6 @@
|
|||
#define rbtx4938_pcireset_ptr \
|
||||
((volatile unsigned char *)RBTX4938_PCIRESET_ADDR)
|
||||
|
||||
/* SPI */
|
||||
#define RBTX4938_SEEPROM1_CHIPID 0
|
||||
#define RBTX4938_SEEPROM2_CHIPID 1
|
||||
#define RBTX4938_SEEPROM3_CHIPID 2
|
||||
#define RBTX4938_SRTC_CHIPID 3
|
||||
|
||||
/*
|
||||
* IRQ mappings
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -14,61 +14,7 @@
|
|||
#ifndef __ASM_TX_BOARDS_TX4938_SPI_H
|
||||
#define __ASM_TX_BOARDS_TX4938_SPI_H
|
||||
|
||||
/* SPI */
|
||||
struct spi_dev_desc {
|
||||
unsigned int baud;
|
||||
unsigned short tcss, tcsh, tcsr; /* CS setup/hold/recovery time */
|
||||
unsigned int byteorder:1; /* 0:LSB-First, 1:MSB-First */
|
||||
unsigned int polarity:1; /* 0:High-Active */
|
||||
unsigned int phase:1; /* 0:Sample-Then-Shift */
|
||||
};
|
||||
|
||||
extern void txx9_spi_init(unsigned long base, int (*cs_func)(int chipid, int on)) __init;
|
||||
extern void txx9_spi_irqinit(int irc_irq) __init;
|
||||
extern int txx9_spi_io(int chipid, struct spi_dev_desc *desc,
|
||||
unsigned char **inbufs, unsigned int *incounts,
|
||||
unsigned char **outbufs, unsigned int *outcounts,
|
||||
int cansleep);
|
||||
extern int spi_eeprom_write_enable(int chipid, int enable);
|
||||
extern int spi_eeprom_read_status(int chipid);
|
||||
extern int spi_eeprom_register(int chipid);
|
||||
extern int spi_eeprom_read(int chipid, int address, unsigned char *buf, int len);
|
||||
extern int spi_eeprom_write(int chipid, int address, unsigned char *buf, int len);
|
||||
extern void spi_eeprom_proc_create(struct proc_dir_entry *dir, int chipid) __init;
|
||||
|
||||
#define TXX9_IMCLK (txx9_gbus_clock / 2)
|
||||
|
||||
/*
|
||||
* SPI
|
||||
*/
|
||||
|
||||
/* SPMCR : SPI Master Control */
|
||||
#define TXx9_SPMCR_OPMODE 0xc0
|
||||
#define TXx9_SPMCR_CONFIG 0x40
|
||||
#define TXx9_SPMCR_ACTIVE 0x80
|
||||
#define TXx9_SPMCR_SPSTP 0x02
|
||||
#define TXx9_SPMCR_BCLR 0x01
|
||||
|
||||
/* SPCR0 : SPI Status */
|
||||
#define TXx9_SPCR0_TXIFL_MASK 0xc000
|
||||
#define TXx9_SPCR0_RXIFL_MASK 0x3000
|
||||
#define TXx9_SPCR0_SIDIE 0x0800
|
||||
#define TXx9_SPCR0_SOEIE 0x0400
|
||||
#define TXx9_SPCR0_RBSIE 0x0200
|
||||
#define TXx9_SPCR0_TBSIE 0x0100
|
||||
#define TXx9_SPCR0_IFSPSE 0x0010
|
||||
#define TXx9_SPCR0_SBOS 0x0004
|
||||
#define TXx9_SPCR0_SPHA 0x0002
|
||||
#define TXx9_SPCR0_SPOL 0x0001
|
||||
|
||||
/* SPSR : SPI Status */
|
||||
#define TXx9_SPSR_TBSI 0x8000
|
||||
#define TXx9_SPSR_RBSI 0x4000
|
||||
#define TXx9_SPSR_TBS_MASK 0x3800
|
||||
#define TXx9_SPSR_RBS_MASK 0x0700
|
||||
#define TXx9_SPSR_SPOE 0x0080
|
||||
#define TXx9_SPSR_IFSD 0x0008
|
||||
#define TXx9_SPSR_SIDLE 0x0004
|
||||
#define TXx9_SPSR_STRDY 0x0002
|
||||
#define TXx9_SPSR_SRRDY 0x0001
|
||||
|
||||
#endif /* __ASM_TX_BOARDS_TX4938_SPI_H */
|
||||
|
|
|
|||
Loading…
Reference in a new issue