ARM: tegra: skip SCU and PL310 code when CPU is not Cortex-A9
For supporting single image on all Tegra series, we need to skip some HW support code for Cortex-A9 only. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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2 changed files with 23 additions and 9 deletions
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@ -106,9 +106,11 @@ ENTRY(tegra_shut_off_mmu)
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isb
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#ifdef CONFIG_CACHE_L2X0
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/* Disable L2 cache */
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mov32 r4, TEGRA_ARM_PERIF_BASE + 0x3000
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mov r5, #0
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str r5, [r4, #L2X0_CTRL]
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check_cpu_part_num 0xc09, r9, r10
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movweq r4, #:lower16:(TEGRA_ARM_PERIF_BASE + 0x3000)
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movteq r4, #:upper16:(TEGRA_ARM_PERIF_BASE + 0x3000)
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moveq r5, #0
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streq r5, [r4, #L2X0_CTRL]
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#endif
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mov pc, r0
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ENDPROC(tegra_shut_off_mmu)
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@ -70,19 +70,31 @@
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movt \reg, #:upper16:\val
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.endm
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/* Marco to check CPU part num */
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.macro check_cpu_part_num part_num, tmp1, tmp2
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mrc p15, 0, \tmp1, c0, c0, 0
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ubfx \tmp1, \tmp1, #4, #12
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mov32 \tmp2, \part_num
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cmp \tmp1, \tmp2
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.endm
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/* Macro to exit SMP coherency. */
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.macro exit_smp, tmp1, tmp2
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mrc p15, 0, \tmp1, c1, c0, 1 @ ACTLR
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bic \tmp1, \tmp1, #(1<<6) | (1<<0) @ clear ACTLR.SMP | ACTLR.FW
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mcr p15, 0, \tmp1, c1, c0, 1 @ ACTLR
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isb
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cpu_id \tmp1
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mov \tmp1, \tmp1, lsl #2
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mov \tmp2, #0xf
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mov \tmp2, \tmp2, lsl \tmp1
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mov32 \tmp1, TEGRA_ARM_PERIF_VIRT + 0xC
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str \tmp2, [\tmp1] @ invalidate SCU tags for CPU
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#ifdef CONFIG_HAVE_ARM_SCU
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check_cpu_part_num 0xc09, \tmp1, \tmp2
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mrceq p15, 0, \tmp1, c0, c0, 5
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andeq \tmp1, \tmp1, #0xF
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moveq \tmp1, \tmp1, lsl #2
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moveq \tmp2, #0xf
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moveq \tmp2, \tmp2, lsl \tmp1
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ldreq \tmp1, =(TEGRA_ARM_PERIF_VIRT + 0xC)
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streq \tmp2, [\tmp1] @ invalidate SCU tags for CPU
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dsb
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#endif
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.endm
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/* Macro to check Tegra revision */
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