Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/linville/wireless-next into for-davem
This commit is contained in:
commit
f647a52e15
222 changed files with 4988 additions and 4261 deletions
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@ -8563,12 +8563,11 @@ S: Maintained
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|||
F: sound/soc/codecs/twl4030*
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||||
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||||
TI WILINK WIRELESS DRIVERS
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M: Luciano Coelho <luca@coelho.fi>
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L: linux-wireless@vger.kernel.org
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W: http://wireless.kernel.org/en/users/Drivers/wl12xx
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W: http://wireless.kernel.org/en/users/Drivers/wl1251
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T: git git://git.kernel.org/pub/scm/linux/kernel/git/luca/wl12xx.git
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S: Maintained
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S: Orphan
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F: drivers/net/wireless/ti/
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F: include/linux/wl12xx.h
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@ -269,7 +269,7 @@ static SIMPLE_DEV_PM_OPS(bcma_pm_ops, bcma_host_pci_suspend,
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#endif /* CONFIG_PM_SLEEP */
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static DEFINE_PCI_DEVICE_TABLE(bcma_pci_bridge_tbl) = {
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static const struct pci_device_id bcma_pci_bridge_tbl[] = {
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{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x0576) },
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{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4313) },
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{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 43224) },
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@ -83,6 +83,7 @@ static const struct usb_device_id ath3k_table[] = {
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{ USB_DEVICE(0x04CA, 0x3005) },
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{ USB_DEVICE(0x04CA, 0x3006) },
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{ USB_DEVICE(0x04CA, 0x3008) },
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{ USB_DEVICE(0x04CA, 0x300b) },
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{ USB_DEVICE(0x13d3, 0x3362) },
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{ USB_DEVICE(0x0CF3, 0xE004) },
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{ USB_DEVICE(0x0CF3, 0xE005) },
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@ -96,6 +97,7 @@ static const struct usb_device_id ath3k_table[] = {
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{ USB_DEVICE(0x13d3, 0x3402) },
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{ USB_DEVICE(0x0cf3, 0x3121) },
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{ USB_DEVICE(0x0cf3, 0xe003) },
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{ USB_DEVICE(0x0489, 0xe05f) },
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/* Atheros AR5BBU12 with sflash firmware */
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{ USB_DEVICE(0x0489, 0xE02C) },
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@ -125,6 +127,7 @@ static const struct usb_device_id ath3k_blist_tbl[] = {
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{ USB_DEVICE(0x04ca, 0x3005), .driver_info = BTUSB_ATH3012 },
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{ USB_DEVICE(0x04ca, 0x3006), .driver_info = BTUSB_ATH3012 },
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{ USB_DEVICE(0x04ca, 0x3008), .driver_info = BTUSB_ATH3012 },
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{ USB_DEVICE(0x04ca, 0x300b), .driver_info = BTUSB_ATH3012 },
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{ USB_DEVICE(0x13d3, 0x3362), .driver_info = BTUSB_ATH3012 },
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{ USB_DEVICE(0x0cf3, 0xe004), .driver_info = BTUSB_ATH3012 },
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{ USB_DEVICE(0x0cf3, 0xe005), .driver_info = BTUSB_ATH3012 },
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@ -138,6 +141,7 @@ static const struct usb_device_id ath3k_blist_tbl[] = {
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{ USB_DEVICE(0x13d3, 0x3402), .driver_info = BTUSB_ATH3012 },
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{ USB_DEVICE(0x0cf3, 0x3121), .driver_info = BTUSB_ATH3012 },
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{ USB_DEVICE(0x0cf3, 0xe003), .driver_info = BTUSB_ATH3012 },
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{ USB_DEVICE(0x0489, 0xe05f), .driver_info = BTUSB_ATH3012 },
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/* Atheros AR5BBU22 with sflash firmware */
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{ USB_DEVICE(0x0489, 0xE03C), .driver_info = BTUSB_ATH3012 },
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@ -23,8 +23,6 @@
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#include <linux/bitops.h>
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#include <linux/slab.h>
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#include <net/bluetooth/bluetooth.h>
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#include <linux/ctype.h>
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#include <linux/firmware.h>
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#define BTM_HEADER_LEN 4
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#define BTM_UPLD_SIZE 2312
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@ -43,8 +41,6 @@ struct btmrvl_thread {
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struct btmrvl_device {
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void *card;
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struct hci_dev *hcidev;
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struct device *dev;
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const char *cal_data;
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u8 dev_type;
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@ -90,12 +86,12 @@ struct btmrvl_private {
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#define MRVL_VENDOR_PKT 0xFE
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/* Bluetooth commands */
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#define BT_CMD_AUTO_SLEEP_MODE 0x23
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#define BT_CMD_HOST_SLEEP_CONFIG 0x59
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#define BT_CMD_HOST_SLEEP_ENABLE 0x5A
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#define BT_CMD_MODULE_CFG_REQ 0x5B
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#define BT_CMD_LOAD_CONFIG_DATA 0x61
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/* Vendor specific Bluetooth commands */
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#define BT_CMD_AUTO_SLEEP_MODE 0xFC23
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#define BT_CMD_HOST_SLEEP_CONFIG 0xFC59
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#define BT_CMD_HOST_SLEEP_ENABLE 0xFC5A
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#define BT_CMD_MODULE_CFG_REQ 0xFC5B
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#define BT_CMD_LOAD_CONFIG_DATA 0xFC61
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/* Sub-commands: Module Bringup/Shutdown Request/Response */
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#define MODULE_BRINGUP_REQ 0xF1
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@ -104,6 +100,11 @@ struct btmrvl_private {
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#define MODULE_SHUTDOWN_REQ 0xF2
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/* Vendor specific Bluetooth events */
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#define BT_EVENT_AUTO_SLEEP_MODE 0x23
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#define BT_EVENT_HOST_SLEEP_CONFIG 0x59
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#define BT_EVENT_HOST_SLEEP_ENABLE 0x5A
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#define BT_EVENT_MODULE_CFG_REQ 0x5B
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#define BT_EVENT_POWER_STATE 0x20
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/* Bluetooth Power States */
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@ -111,8 +112,6 @@ struct btmrvl_private {
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#define BT_PS_DISABLE 0x03
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#define BT_PS_SLEEP 0x01
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#define OGF 0x3F
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/* Host Sleep states */
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#define HS_ACTIVATED 0x01
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#define HS_DEACTIVATED 0x00
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@ -121,7 +120,7 @@ struct btmrvl_private {
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#define PS_SLEEP 0x01
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#define PS_AWAKE 0x00
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#define BT_CMD_DATA_SIZE 32
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#define BT_CAL_HDR_LEN 4
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#define BT_CAL_DATA_SIZE 28
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struct btmrvl_event {
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@ -19,7 +19,7 @@
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**/
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#include <linux/module.h>
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#include <linux/of.h>
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#include <net/bluetooth/bluetooth.h>
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#include <net/bluetooth/hci_core.h>
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@ -50,12 +50,10 @@ bool btmrvl_check_evtpkt(struct btmrvl_private *priv, struct sk_buff *skb)
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if (hdr->evt == HCI_EV_CMD_COMPLETE) {
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struct hci_ev_cmd_complete *ec;
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u16 opcode, ocf, ogf;
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u16 opcode;
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ec = (void *) (skb->data + HCI_EVENT_HDR_SIZE);
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opcode = __le16_to_cpu(ec->opcode);
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ocf = hci_opcode_ocf(opcode);
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ogf = hci_opcode_ogf(opcode);
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if (priv->btmrvl_dev.sendcmdflag) {
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priv->btmrvl_dev.sendcmdflag = false;
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@ -63,9 +61,8 @@ bool btmrvl_check_evtpkt(struct btmrvl_private *priv, struct sk_buff *skb)
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wake_up_interruptible(&priv->adapter->cmd_wait_q);
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}
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if (ogf == OGF) {
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BT_DBG("vendor event skipped: ogf 0x%4.4x ocf 0x%4.4x",
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ogf, ocf);
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if (hci_opcode_ogf(opcode) == 0x3F) {
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BT_DBG("vendor event skipped: opcode=%#4.4x", opcode);
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kfree_skb(skb);
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return false;
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}
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@ -89,7 +86,7 @@ int btmrvl_process_event(struct btmrvl_private *priv, struct sk_buff *skb)
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}
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switch (event->data[0]) {
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case BT_CMD_AUTO_SLEEP_MODE:
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case BT_EVENT_AUTO_SLEEP_MODE:
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if (!event->data[2]) {
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if (event->data[1] == BT_PS_ENABLE)
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adapter->psmode = 1;
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@ -102,7 +99,7 @@ int btmrvl_process_event(struct btmrvl_private *priv, struct sk_buff *skb)
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}
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break;
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case BT_CMD_HOST_SLEEP_CONFIG:
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case BT_EVENT_HOST_SLEEP_CONFIG:
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if (!event->data[3])
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BT_DBG("gpio=%x, gap=%x", event->data[1],
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event->data[2]);
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@ -110,7 +107,7 @@ int btmrvl_process_event(struct btmrvl_private *priv, struct sk_buff *skb)
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BT_DBG("HSCFG command failed");
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break;
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case BT_CMD_HOST_SLEEP_ENABLE:
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case BT_EVENT_HOST_SLEEP_ENABLE:
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if (!event->data[1]) {
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adapter->hs_state = HS_ACTIVATED;
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if (adapter->psmode)
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@ -121,7 +118,7 @@ int btmrvl_process_event(struct btmrvl_private *priv, struct sk_buff *skb)
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}
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break;
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case BT_CMD_MODULE_CFG_REQ:
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case BT_EVENT_MODULE_CFG_REQ:
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if (priv->btmrvl_dev.sendcmdflag &&
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event->data[1] == MODULE_BRINGUP_REQ) {
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BT_DBG("EVENT:%s",
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@ -166,7 +163,7 @@ int btmrvl_process_event(struct btmrvl_private *priv, struct sk_buff *skb)
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}
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EXPORT_SYMBOL_GPL(btmrvl_process_event);
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static int btmrvl_send_sync_cmd(struct btmrvl_private *priv, u16 cmd_no,
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static int btmrvl_send_sync_cmd(struct btmrvl_private *priv, u16 opcode,
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const void *param, u8 len)
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{
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struct sk_buff *skb;
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@ -179,7 +176,7 @@ static int btmrvl_send_sync_cmd(struct btmrvl_private *priv, u16 cmd_no,
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}
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hdr = (struct hci_command_hdr *)skb_put(skb, HCI_COMMAND_HDR_SIZE);
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hdr->opcode = cpu_to_le16(hci_opcode_pack(OGF, cmd_no));
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hdr->opcode = cpu_to_le16(opcode);
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hdr->plen = len;
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if (len)
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@ -417,127 +414,62 @@ static int btmrvl_open(struct hci_dev *hdev)
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return 0;
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}
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/*
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* This function parses provided calibration data input. It should contain
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* hex bytes separated by space or new line character. Here is an example.
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* 00 1C 01 37 FF FF FF FF 02 04 7F 01
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* CE BA 00 00 00 2D C6 C0 00 00 00 00
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* 00 F0 00 00
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*/
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static int btmrvl_parse_cal_cfg(const u8 *src, u32 len, u8 *dst, u32 dst_size)
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static int btmrvl_download_cal_data(struct btmrvl_private *priv,
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u8 *data, int len)
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{
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const u8 *s = src;
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u8 *d = dst;
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int ret;
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u8 tmp[3];
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tmp[2] = '\0';
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while ((s - src) <= len - 2) {
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if (isspace(*s)) {
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s++;
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continue;
|
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}
|
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|
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if (isxdigit(*s)) {
|
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if ((d - dst) >= dst_size) {
|
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BT_ERR("calibration data file too big!!!");
|
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return -EINVAL;
|
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}
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|
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memcpy(tmp, s, 2);
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|
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ret = kstrtou8(tmp, 16, d++);
|
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if (ret < 0)
|
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return ret;
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|
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s += 2;
|
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} else {
|
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return -EINVAL;
|
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}
|
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}
|
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if (d == dst)
|
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return -EINVAL;
|
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|
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return 0;
|
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}
|
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|
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static int btmrvl_load_cal_data(struct btmrvl_private *priv,
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u8 *config_data)
|
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{
|
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int i, ret;
|
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u8 data[BT_CMD_DATA_SIZE];
|
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|
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data[0] = 0x00;
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data[1] = 0x00;
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data[2] = 0x00;
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data[3] = BT_CMD_DATA_SIZE - 4;
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|
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/* Swap cal-data bytes. Each four bytes are swapped. Considering 4
|
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* byte SDIO header offset, mapping of input and output bytes will be
|
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* {3, 2, 1, 0} -> {0+4, 1+4, 2+4, 3+4},
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* {7, 6, 5, 4} -> {4+4, 5+4, 6+4, 7+4} */
|
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for (i = 4; i < BT_CMD_DATA_SIZE; i++)
|
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data[i] = config_data[(i / 4) * 8 - 1 - i];
|
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data[3] = len;
|
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|
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print_hex_dump_bytes("Calibration data: ",
|
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DUMP_PREFIX_OFFSET, data, BT_CMD_DATA_SIZE);
|
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DUMP_PREFIX_OFFSET, data, BT_CAL_HDR_LEN + len);
|
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|
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ret = btmrvl_send_sync_cmd(priv, BT_CMD_LOAD_CONFIG_DATA, data,
|
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BT_CMD_DATA_SIZE);
|
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BT_CAL_HDR_LEN + len);
|
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if (ret)
|
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BT_ERR("Failed to download caibration data\n");
|
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|
||||
return 0;
|
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}
|
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|
||||
static int
|
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btmrvl_process_cal_cfg(struct btmrvl_private *priv, u8 *data, u32 size)
|
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static int btmrvl_cal_data_dt(struct btmrvl_private *priv)
|
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{
|
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u8 cal_data[BT_CAL_DATA_SIZE];
|
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struct device_node *dt_node;
|
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u8 cal_data[BT_CAL_HDR_LEN + BT_CAL_DATA_SIZE];
|
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const char name[] = "btmrvl_caldata";
|
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const char property[] = "btmrvl,caldata";
|
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int ret;
|
||||
|
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ret = btmrvl_parse_cal_cfg(data, size, cal_data, sizeof(cal_data));
|
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dt_node = of_find_node_by_name(NULL, name);
|
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if (!dt_node)
|
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return -ENODEV;
|
||||
|
||||
ret = of_property_read_u8_array(dt_node, property,
|
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cal_data + BT_CAL_HDR_LEN,
|
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BT_CAL_DATA_SIZE);
|
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if (ret)
|
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return ret;
|
||||
|
||||
ret = btmrvl_load_cal_data(priv, cal_data);
|
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BT_DBG("Use cal data from device tree");
|
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ret = btmrvl_download_cal_data(priv, cal_data, BT_CAL_DATA_SIZE);
|
||||
if (ret) {
|
||||
BT_ERR("Fail to load calibrate data");
|
||||
BT_ERR("Fail to download calibrate data");
|
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return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int btmrvl_cal_data_config(struct btmrvl_private *priv)
|
||||
{
|
||||
const struct firmware *cfg;
|
||||
int ret;
|
||||
const char *cal_data = priv->btmrvl_dev.cal_data;
|
||||
|
||||
if (!cal_data)
|
||||
return 0;
|
||||
|
||||
ret = request_firmware(&cfg, cal_data, priv->btmrvl_dev.dev);
|
||||
if (ret < 0) {
|
||||
BT_DBG("Failed to get %s file, skipping cal data download",
|
||||
cal_data);
|
||||
return 0;
|
||||
}
|
||||
|
||||
ret = btmrvl_process_cal_cfg(priv, (u8 *)cfg->data, cfg->size);
|
||||
release_firmware(cfg);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int btmrvl_setup(struct hci_dev *hdev)
|
||||
{
|
||||
struct btmrvl_private *priv = hci_get_drvdata(hdev);
|
||||
|
||||
btmrvl_send_module_cfg_cmd(priv, MODULE_BRINGUP_REQ);
|
||||
|
||||
if (btmrvl_cal_data_config(priv))
|
||||
BT_ERR("Set cal data failed");
|
||||
btmrvl_cal_data_dt(priv);
|
||||
|
||||
priv->btmrvl_dev.psmode = 1;
|
||||
btmrvl_enable_ps(priv);
|
||||
|
|
|
@ -18,6 +18,7 @@
|
|||
* this warranty disclaimer.
|
||||
**/
|
||||
|
||||
#include <linux/firmware.h>
|
||||
#include <linux/slab.h>
|
||||
|
||||
#include <linux/mmc/sdio_ids.h>
|
||||
|
@ -101,7 +102,6 @@ static const struct btmrvl_sdio_card_reg btmrvl_reg_88xx = {
|
|||
static const struct btmrvl_sdio_device btmrvl_sdio_sd8688 = {
|
||||
.helper = "mrvl/sd8688_helper.bin",
|
||||
.firmware = "mrvl/sd8688.bin",
|
||||
.cal_data = NULL,
|
||||
.reg = &btmrvl_reg_8688,
|
||||
.sd_blksz_fw_dl = 64,
|
||||
};
|
||||
|
@ -109,7 +109,6 @@ static const struct btmrvl_sdio_device btmrvl_sdio_sd8688 = {
|
|||
static const struct btmrvl_sdio_device btmrvl_sdio_sd8787 = {
|
||||
.helper = NULL,
|
||||
.firmware = "mrvl/sd8787_uapsta.bin",
|
||||
.cal_data = NULL,
|
||||
.reg = &btmrvl_reg_87xx,
|
||||
.sd_blksz_fw_dl = 256,
|
||||
};
|
||||
|
@ -117,7 +116,6 @@ static const struct btmrvl_sdio_device btmrvl_sdio_sd8787 = {
|
|||
static const struct btmrvl_sdio_device btmrvl_sdio_sd8797 = {
|
||||
.helper = NULL,
|
||||
.firmware = "mrvl/sd8797_uapsta.bin",
|
||||
.cal_data = "mrvl/sd8797_caldata.conf",
|
||||
.reg = &btmrvl_reg_87xx,
|
||||
.sd_blksz_fw_dl = 256,
|
||||
};
|
||||
|
@ -125,7 +123,6 @@ static const struct btmrvl_sdio_device btmrvl_sdio_sd8797 = {
|
|||
static const struct btmrvl_sdio_device btmrvl_sdio_sd8897 = {
|
||||
.helper = NULL,
|
||||
.firmware = "mrvl/sd8897_uapsta.bin",
|
||||
.cal_data = NULL,
|
||||
.reg = &btmrvl_reg_88xx,
|
||||
.sd_blksz_fw_dl = 256,
|
||||
};
|
||||
|
@ -1007,7 +1004,6 @@ static int btmrvl_sdio_probe(struct sdio_func *func,
|
|||
struct btmrvl_sdio_device *data = (void *) id->driver_data;
|
||||
card->helper = data->helper;
|
||||
card->firmware = data->firmware;
|
||||
card->cal_data = data->cal_data;
|
||||
card->reg = data->reg;
|
||||
card->sd_blksz_fw_dl = data->sd_blksz_fw_dl;
|
||||
}
|
||||
|
@ -1036,8 +1032,6 @@ static int btmrvl_sdio_probe(struct sdio_func *func,
|
|||
}
|
||||
|
||||
card->priv = priv;
|
||||
priv->btmrvl_dev.dev = &card->func->dev;
|
||||
priv->btmrvl_dev.cal_data = card->cal_data;
|
||||
|
||||
/* Initialize the interface specific function pointers */
|
||||
priv->hw_host_to_card = btmrvl_sdio_host_to_card;
|
||||
|
@ -1220,5 +1214,4 @@ MODULE_FIRMWARE("mrvl/sd8688_helper.bin");
|
|||
MODULE_FIRMWARE("mrvl/sd8688.bin");
|
||||
MODULE_FIRMWARE("mrvl/sd8787_uapsta.bin");
|
||||
MODULE_FIRMWARE("mrvl/sd8797_uapsta.bin");
|
||||
MODULE_FIRMWARE("mrvl/sd8797_caldata.conf");
|
||||
MODULE_FIRMWARE("mrvl/sd8897_uapsta.bin");
|
||||
|
|
|
@ -85,7 +85,6 @@ struct btmrvl_sdio_card {
|
|||
u32 ioport;
|
||||
const char *helper;
|
||||
const char *firmware;
|
||||
const char *cal_data;
|
||||
const struct btmrvl_sdio_card_reg *reg;
|
||||
u16 sd_blksz_fw_dl;
|
||||
u8 rx_unit;
|
||||
|
@ -95,7 +94,6 @@ struct btmrvl_sdio_card {
|
|||
struct btmrvl_sdio_device {
|
||||
const char *helper;
|
||||
const char *firmware;
|
||||
const char *cal_data;
|
||||
const struct btmrvl_sdio_card_reg *reg;
|
||||
u16 sd_blksz_fw_dl;
|
||||
};
|
||||
|
|
|
@ -150,6 +150,7 @@ static const struct usb_device_id blacklist_table[] = {
|
|||
{ USB_DEVICE(0x04ca, 0x3005), .driver_info = BTUSB_ATH3012 },
|
||||
{ USB_DEVICE(0x04ca, 0x3006), .driver_info = BTUSB_ATH3012 },
|
||||
{ USB_DEVICE(0x04ca, 0x3008), .driver_info = BTUSB_ATH3012 },
|
||||
{ USB_DEVICE(0x04ca, 0x300b), .driver_info = BTUSB_ATH3012 },
|
||||
{ USB_DEVICE(0x13d3, 0x3362), .driver_info = BTUSB_ATH3012 },
|
||||
{ USB_DEVICE(0x0cf3, 0xe004), .driver_info = BTUSB_ATH3012 },
|
||||
{ USB_DEVICE(0x0cf3, 0xe005), .driver_info = BTUSB_ATH3012 },
|
||||
|
@ -163,6 +164,7 @@ static const struct usb_device_id blacklist_table[] = {
|
|||
{ USB_DEVICE(0x13d3, 0x3402), .driver_info = BTUSB_ATH3012 },
|
||||
{ USB_DEVICE(0x0cf3, 0x3121), .driver_info = BTUSB_ATH3012 },
|
||||
{ USB_DEVICE(0x0cf3, 0xe003), .driver_info = BTUSB_ATH3012 },
|
||||
{ USB_DEVICE(0x0489, 0xe05f), .driver_info = BTUSB_ATH3012 },
|
||||
|
||||
/* Atheros AR5BBU12 with sflash firmware */
|
||||
{ USB_DEVICE(0x0489, 0xe02c), .driver_info = BTUSB_IGNORE },
|
||||
|
@ -223,6 +225,7 @@ static const struct usb_device_id blacklist_table[] = {
|
|||
|
||||
/* Intel Bluetooth device */
|
||||
{ USB_DEVICE(0x8087, 0x07dc), .driver_info = BTUSB_INTEL },
|
||||
{ USB_DEVICE(0x8087, 0x0a2a), .driver_info = BTUSB_INTEL },
|
||||
|
||||
{ } /* Terminating entry */
|
||||
};
|
||||
|
@ -1435,8 +1438,10 @@ static int btusb_probe(struct usb_interface *intf,
|
|||
if (id->driver_info & BTUSB_BCM92035)
|
||||
hdev->setup = btusb_setup_bcm92035;
|
||||
|
||||
if (id->driver_info & BTUSB_INTEL)
|
||||
if (id->driver_info & BTUSB_INTEL) {
|
||||
usb_enable_autosuspend(data->udev);
|
||||
hdev->setup = btusb_setup_intel;
|
||||
}
|
||||
|
||||
/* Interface numbers are hardcoded in the specification */
|
||||
data->isoc = usb_ifnum_to_if(data->udev, 1);
|
||||
|
|
|
@ -243,6 +243,16 @@ static inline void ath10k_ce_error_intr_enable(struct ath10k *ar,
|
|||
misc_ie_addr | CE_ERROR_MASK);
|
||||
}
|
||||
|
||||
static inline void ath10k_ce_error_intr_disable(struct ath10k *ar,
|
||||
u32 ce_ctrl_addr)
|
||||
{
|
||||
u32 misc_ie_addr = ath10k_pci_read32(ar,
|
||||
ce_ctrl_addr + MISC_IE_ADDRESS);
|
||||
|
||||
ath10k_pci_write32(ar, ce_ctrl_addr + MISC_IE_ADDRESS,
|
||||
misc_ie_addr & ~CE_ERROR_MASK);
|
||||
}
|
||||
|
||||
static inline void ath10k_ce_engine_int_status_clear(struct ath10k *ar,
|
||||
u32 ce_ctrl_addr,
|
||||
unsigned int mask)
|
||||
|
@ -731,7 +741,6 @@ void ath10k_ce_per_engine_service(struct ath10k *ar, unsigned int ce_id)
|
|||
|
||||
void ath10k_ce_per_engine_service_any(struct ath10k *ar)
|
||||
{
|
||||
struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
|
||||
int ce_id, ret;
|
||||
u32 intr_summary;
|
||||
|
||||
|
@ -741,7 +750,7 @@ void ath10k_ce_per_engine_service_any(struct ath10k *ar)
|
|||
|
||||
intr_summary = CE_INTERRUPT_SUMMARY(ar);
|
||||
|
||||
for (ce_id = 0; intr_summary && (ce_id < ar_pci->ce_count); ce_id++) {
|
||||
for (ce_id = 0; intr_summary && (ce_id < CE_COUNT); ce_id++) {
|
||||
if (intr_summary & (1 << ce_id))
|
||||
intr_summary &= ~(1 << ce_id);
|
||||
else
|
||||
|
@ -783,22 +792,25 @@ static void ath10k_ce_per_engine_handler_adjust(struct ath10k_ce_pipe *ce_state,
|
|||
ath10k_pci_sleep(ar);
|
||||
}
|
||||
|
||||
void ath10k_ce_disable_interrupts(struct ath10k *ar)
|
||||
int ath10k_ce_disable_interrupts(struct ath10k *ar)
|
||||
{
|
||||
struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
|
||||
int ce_id, ret;
|
||||
|
||||
ret = ath10k_pci_wake(ar);
|
||||
if (ret)
|
||||
return;
|
||||
return ret;
|
||||
|
||||
for (ce_id = 0; ce_id < ar_pci->ce_count; ce_id++) {
|
||||
struct ath10k_ce_pipe *ce_state = &ar_pci->ce_states[ce_id];
|
||||
u32 ctrl_addr = ce_state->ctrl_addr;
|
||||
for (ce_id = 0; ce_id < CE_COUNT; ce_id++) {
|
||||
u32 ctrl_addr = ath10k_ce_base_address(ce_id);
|
||||
|
||||
ath10k_ce_copy_complete_intr_disable(ar, ctrl_addr);
|
||||
ath10k_ce_error_intr_disable(ar, ctrl_addr);
|
||||
ath10k_ce_watermark_intr_disable(ar, ctrl_addr);
|
||||
}
|
||||
|
||||
ath10k_pci_sleep(ar);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void ath10k_ce_send_cb_register(struct ath10k_ce_pipe *ce_state,
|
||||
|
@ -1047,9 +1059,19 @@ struct ath10k_ce_pipe *ath10k_ce_init(struct ath10k *ar,
|
|||
const struct ce_attr *attr)
|
||||
{
|
||||
struct ath10k_ce_pipe *ce_state;
|
||||
u32 ctrl_addr = ath10k_ce_base_address(ce_id);
|
||||
int ret;
|
||||
|
||||
/*
|
||||
* Make sure there's enough CE ringbuffer entries for HTT TX to avoid
|
||||
* additional TX locking checks.
|
||||
*
|
||||
* For the lack of a better place do the check here.
|
||||
*/
|
||||
BUILD_BUG_ON(TARGET_NUM_MSDU_DESC >
|
||||
(CE_HTT_H2T_MSG_SRC_NENTRIES - 1));
|
||||
BUILD_BUG_ON(TARGET_10X_NUM_MSDU_DESC >
|
||||
(CE_HTT_H2T_MSG_SRC_NENTRIES - 1));
|
||||
|
||||
ret = ath10k_pci_wake(ar);
|
||||
if (ret)
|
||||
return NULL;
|
||||
|
@ -1057,7 +1079,7 @@ struct ath10k_ce_pipe *ath10k_ce_init(struct ath10k *ar,
|
|||
ce_state = ath10k_ce_init_state(ar, ce_id, attr);
|
||||
if (!ce_state) {
|
||||
ath10k_err("Failed to initialize CE state for ID: %d\n", ce_id);
|
||||
return NULL;
|
||||
goto out;
|
||||
}
|
||||
|
||||
if (attr->src_nentries) {
|
||||
|
@ -1066,7 +1088,8 @@ struct ath10k_ce_pipe *ath10k_ce_init(struct ath10k *ar,
|
|||
ath10k_err("Failed to initialize CE src ring for ID: %d (%d)\n",
|
||||
ce_id, ret);
|
||||
ath10k_ce_deinit(ce_state);
|
||||
return NULL;
|
||||
ce_state = NULL;
|
||||
goto out;
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -1076,15 +1099,13 @@ struct ath10k_ce_pipe *ath10k_ce_init(struct ath10k *ar,
|
|||
ath10k_err("Failed to initialize CE dest ring for ID: %d (%d)\n",
|
||||
ce_id, ret);
|
||||
ath10k_ce_deinit(ce_state);
|
||||
return NULL;
|
||||
ce_state = NULL;
|
||||
goto out;
|
||||
}
|
||||
}
|
||||
|
||||
/* Enable CE error interrupts */
|
||||
ath10k_ce_error_intr_enable(ar, ctrl_addr);
|
||||
|
||||
out:
|
||||
ath10k_pci_sleep(ar);
|
||||
|
||||
return ce_state;
|
||||
}
|
||||
|
||||
|
|
|
@ -234,7 +234,7 @@ void ath10k_ce_deinit(struct ath10k_ce_pipe *ce_state);
|
|||
/*==================CE Interrupt Handlers====================*/
|
||||
void ath10k_ce_per_engine_service_any(struct ath10k *ar);
|
||||
void ath10k_ce_per_engine_service(struct ath10k *ar, unsigned int ce_id);
|
||||
void ath10k_ce_disable_interrupts(struct ath10k *ar);
|
||||
int ath10k_ce_disable_interrupts(struct ath10k *ar);
|
||||
|
||||
/* ce_attr.flags values */
|
||||
/* Use NonSnooping PCIe accesses? */
|
||||
|
|
|
@ -597,10 +597,8 @@ static int ath10k_init_uart(struct ath10k *ar)
|
|||
return ret;
|
||||
}
|
||||
|
||||
if (!uart_print) {
|
||||
ath10k_info("UART prints disabled\n");
|
||||
if (!uart_print)
|
||||
return 0;
|
||||
}
|
||||
|
||||
ret = ath10k_bmi_write32(ar, hi_dbg_uart_txpin, 7);
|
||||
if (ret) {
|
||||
|
@ -645,8 +643,8 @@ static int ath10k_init_hw_params(struct ath10k *ar)
|
|||
|
||||
ar->hw_params = *hw_params;
|
||||
|
||||
ath10k_info("Hardware name %s version 0x%x\n",
|
||||
ar->hw_params.name, ar->target_version);
|
||||
ath10k_dbg(ATH10K_DBG_BOOT, "Hardware name %s version 0x%x\n",
|
||||
ar->hw_params.name, ar->target_version);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
@ -664,7 +662,8 @@ static void ath10k_core_restart(struct work_struct *work)
|
|||
ieee80211_restart_hw(ar->hw);
|
||||
break;
|
||||
case ATH10K_STATE_OFF:
|
||||
/* this can happen if driver is being unloaded */
|
||||
/* this can happen if driver is being unloaded
|
||||
* or if the crash happens during FW probing */
|
||||
ath10k_warn("cannot restart a device that hasn't been started\n");
|
||||
break;
|
||||
case ATH10K_STATE_RESTARTING:
|
||||
|
@ -737,8 +736,6 @@ EXPORT_SYMBOL(ath10k_core_create);
|
|||
|
||||
void ath10k_core_destroy(struct ath10k *ar)
|
||||
{
|
||||
ath10k_debug_destroy(ar);
|
||||
|
||||
flush_workqueue(ar->workqueue);
|
||||
destroy_workqueue(ar->workqueue);
|
||||
|
||||
|
@ -786,21 +783,30 @@ int ath10k_core_start(struct ath10k *ar)
|
|||
goto err;
|
||||
}
|
||||
|
||||
status = ath10k_htc_wait_target(&ar->htc);
|
||||
if (status)
|
||||
status = ath10k_hif_start(ar);
|
||||
if (status) {
|
||||
ath10k_err("could not start HIF: %d\n", status);
|
||||
goto err_wmi_detach;
|
||||
}
|
||||
|
||||
status = ath10k_htc_wait_target(&ar->htc);
|
||||
if (status) {
|
||||
ath10k_err("failed to connect to HTC: %d\n", status);
|
||||
goto err_hif_stop;
|
||||
}
|
||||
|
||||
status = ath10k_htt_attach(ar);
|
||||
if (status) {
|
||||
ath10k_err("could not attach htt (%d)\n", status);
|
||||
goto err_wmi_detach;
|
||||
goto err_hif_stop;
|
||||
}
|
||||
|
||||
status = ath10k_init_connect_htc(ar);
|
||||
if (status)
|
||||
goto err_htt_detach;
|
||||
|
||||
ath10k_info("firmware %s booted\n", ar->hw->wiphy->fw_version);
|
||||
ath10k_dbg(ATH10K_DBG_BOOT, "firmware %s booted\n",
|
||||
ar->hw->wiphy->fw_version);
|
||||
|
||||
status = ath10k_wmi_cmd_init(ar);
|
||||
if (status) {
|
||||
|
@ -826,12 +832,23 @@ int ath10k_core_start(struct ath10k *ar)
|
|||
ar->free_vdev_map = (1 << TARGET_NUM_VDEVS) - 1;
|
||||
INIT_LIST_HEAD(&ar->arvifs);
|
||||
|
||||
if (!test_bit(ATH10K_FLAG_FIRST_BOOT_DONE, &ar->dev_flags))
|
||||
ath10k_info("%s (0x%x) fw %s api %d htt %d.%d\n",
|
||||
ar->hw_params.name, ar->target_version,
|
||||
ar->hw->wiphy->fw_version, ar->fw_api,
|
||||
ar->htt.target_version_major,
|
||||
ar->htt.target_version_minor);
|
||||
|
||||
__set_bit(ATH10K_FLAG_FIRST_BOOT_DONE, &ar->dev_flags);
|
||||
|
||||
return 0;
|
||||
|
||||
err_disconnect_htc:
|
||||
ath10k_htc_stop(&ar->htc);
|
||||
err_htt_detach:
|
||||
ath10k_htt_detach(&ar->htt);
|
||||
err_hif_stop:
|
||||
ath10k_hif_stop(ar);
|
||||
err_wmi_detach:
|
||||
ath10k_wmi_detach(ar);
|
||||
err:
|
||||
|
@ -985,6 +1002,8 @@ void ath10k_core_unregister(struct ath10k *ar)
|
|||
ath10k_mac_unregister(ar);
|
||||
|
||||
ath10k_core_free_firmware_files(ar);
|
||||
|
||||
ath10k_debug_destroy(ar);
|
||||
}
|
||||
EXPORT_SYMBOL(ath10k_core_unregister);
|
||||
|
||||
|
|
|
@ -30,6 +30,7 @@
|
|||
#include "wmi.h"
|
||||
#include "../ath.h"
|
||||
#include "../regd.h"
|
||||
#include "../dfs_pattern_detector.h"
|
||||
|
||||
#define MS(_v, _f) (((_v) & _f##_MASK) >> _f##_LSB)
|
||||
#define SM(_v, _f) (((_v) << _f##_LSB) & _f##_MASK)
|
||||
|
@ -43,7 +44,7 @@
|
|||
/* Antenna noise floor */
|
||||
#define ATH10K_DEFAULT_NOISE_FLOOR -95
|
||||
|
||||
#define ATH10K_MAX_NUM_MGMT_PENDING 16
|
||||
#define ATH10K_MAX_NUM_MGMT_PENDING 128
|
||||
|
||||
struct ath10k;
|
||||
|
||||
|
@ -192,6 +193,14 @@ struct ath10k_target_stats {
|
|||
|
||||
};
|
||||
|
||||
struct ath10k_dfs_stats {
|
||||
u32 phy_errors;
|
||||
u32 pulses_total;
|
||||
u32 pulses_detected;
|
||||
u32 pulses_discarded;
|
||||
u32 radar_detected;
|
||||
};
|
||||
|
||||
#define ATH10K_MAX_NUM_PEER_IDS (1 << 11) /* htt rx_desc limit */
|
||||
|
||||
struct ath10k_peer {
|
||||
|
@ -261,6 +270,8 @@ struct ath10k_debug {
|
|||
|
||||
unsigned long htt_stats_mask;
|
||||
struct delayed_work htt_stats_dwork;
|
||||
struct ath10k_dfs_stats dfs_stats;
|
||||
struct ath_dfs_pool_stats dfs_pool_stats;
|
||||
};
|
||||
|
||||
enum ath10k_state {
|
||||
|
@ -299,6 +310,12 @@ enum ath10k_fw_features {
|
|||
ATH10K_FW_FEATURE_COUNT,
|
||||
};
|
||||
|
||||
enum ath10k_dev_flags {
|
||||
/* Indicates that ath10k device is during CAC phase of DFS */
|
||||
ATH10K_CAC_RUNNING,
|
||||
ATH10K_FLAG_FIRST_BOOT_DONE,
|
||||
};
|
||||
|
||||
struct ath10k {
|
||||
struct ath_common ath_common;
|
||||
struct ieee80211_hw *hw;
|
||||
|
@ -392,6 +409,8 @@ struct ath10k {
|
|||
bool monitor_enabled;
|
||||
bool monitor_present;
|
||||
unsigned int filter_flags;
|
||||
unsigned long dev_flags;
|
||||
u32 dfs_block_radar_events;
|
||||
|
||||
struct wmi_pdev_set_wmm_params_arg wmm_params;
|
||||
struct completion install_key_done;
|
||||
|
@ -428,6 +447,8 @@ struct ath10k {
|
|||
u32 survey_last_cycle_count;
|
||||
struct survey_info survey[ATH10K_NUM_CHANS];
|
||||
|
||||
struct dfs_pattern_detector *dfs_detector;
|
||||
|
||||
#ifdef CONFIG_ATH10K_DEBUGFS
|
||||
struct ath10k_debug debug;
|
||||
#endif
|
||||
|
|
|
@ -639,6 +639,86 @@ void ath10k_debug_stop(struct ath10k *ar)
|
|||
cancel_delayed_work(&ar->debug.htt_stats_dwork);
|
||||
}
|
||||
|
||||
static ssize_t ath10k_write_simulate_radar(struct file *file,
|
||||
const char __user *user_buf,
|
||||
size_t count, loff_t *ppos)
|
||||
{
|
||||
struct ath10k *ar = file->private_data;
|
||||
|
||||
ieee80211_radar_detected(ar->hw);
|
||||
|
||||
return count;
|
||||
}
|
||||
|
||||
static const struct file_operations fops_simulate_radar = {
|
||||
.write = ath10k_write_simulate_radar,
|
||||
.open = simple_open,
|
||||
.owner = THIS_MODULE,
|
||||
.llseek = default_llseek,
|
||||
};
|
||||
|
||||
#define ATH10K_DFS_STAT(s, p) (\
|
||||
len += scnprintf(buf + len, size - len, "%-28s : %10u\n", s, \
|
||||
ar->debug.dfs_stats.p))
|
||||
|
||||
#define ATH10K_DFS_POOL_STAT(s, p) (\
|
||||
len += scnprintf(buf + len, size - len, "%-28s : %10u\n", s, \
|
||||
ar->debug.dfs_pool_stats.p))
|
||||
|
||||
static ssize_t ath10k_read_dfs_stats(struct file *file, char __user *user_buf,
|
||||
size_t count, loff_t *ppos)
|
||||
{
|
||||
int retval = 0, len = 0;
|
||||
const int size = 8000;
|
||||
struct ath10k *ar = file->private_data;
|
||||
char *buf;
|
||||
|
||||
buf = kzalloc(size, GFP_KERNEL);
|
||||
if (buf == NULL)
|
||||
return -ENOMEM;
|
||||
|
||||
if (!ar->dfs_detector) {
|
||||
len += scnprintf(buf + len, size - len, "DFS not enabled\n");
|
||||
goto exit;
|
||||
}
|
||||
|
||||
ar->debug.dfs_pool_stats =
|
||||
ar->dfs_detector->get_stats(ar->dfs_detector);
|
||||
|
||||
len += scnprintf(buf + len, size - len, "Pulse detector statistics:\n");
|
||||
|
||||
ATH10K_DFS_STAT("reported phy errors", phy_errors);
|
||||
ATH10K_DFS_STAT("pulse events reported", pulses_total);
|
||||
ATH10K_DFS_STAT("DFS pulses detected", pulses_detected);
|
||||
ATH10K_DFS_STAT("DFS pulses discarded", pulses_discarded);
|
||||
ATH10K_DFS_STAT("Radars detected", radar_detected);
|
||||
|
||||
len += scnprintf(buf + len, size - len, "Global Pool statistics:\n");
|
||||
ATH10K_DFS_POOL_STAT("Pool references", pool_reference);
|
||||
ATH10K_DFS_POOL_STAT("Pulses allocated", pulse_allocated);
|
||||
ATH10K_DFS_POOL_STAT("Pulses alloc error", pulse_alloc_error);
|
||||
ATH10K_DFS_POOL_STAT("Pulses in use", pulse_used);
|
||||
ATH10K_DFS_POOL_STAT("Seqs. allocated", pseq_allocated);
|
||||
ATH10K_DFS_POOL_STAT("Seqs. alloc error", pseq_alloc_error);
|
||||
ATH10K_DFS_POOL_STAT("Seqs. in use", pseq_used);
|
||||
|
||||
exit:
|
||||
if (len > size)
|
||||
len = size;
|
||||
|
||||
retval = simple_read_from_buffer(user_buf, count, ppos, buf, len);
|
||||
kfree(buf);
|
||||
|
||||
return retval;
|
||||
}
|
||||
|
||||
static const struct file_operations fops_dfs_stats = {
|
||||
.read = ath10k_read_dfs_stats,
|
||||
.open = simple_open,
|
||||
.owner = THIS_MODULE,
|
||||
.llseek = default_llseek,
|
||||
};
|
||||
|
||||
int ath10k_debug_create(struct ath10k *ar)
|
||||
{
|
||||
ar->debug.debugfs_phy = debugfs_create_dir("ath10k",
|
||||
|
@ -667,6 +747,20 @@ int ath10k_debug_create(struct ath10k *ar)
|
|||
debugfs_create_file("htt_stats_mask", S_IRUSR, ar->debug.debugfs_phy,
|
||||
ar, &fops_htt_stats_mask);
|
||||
|
||||
if (config_enabled(CONFIG_ATH10K_DFS_CERTIFIED)) {
|
||||
debugfs_create_file("dfs_simulate_radar", S_IWUSR,
|
||||
ar->debug.debugfs_phy, ar,
|
||||
&fops_simulate_radar);
|
||||
|
||||
debugfs_create_bool("dfs_block_radar_events", S_IWUSR,
|
||||
ar->debug.debugfs_phy,
|
||||
&ar->dfs_block_radar_events);
|
||||
|
||||
debugfs_create_file("dfs_stats", S_IRUSR,
|
||||
ar->debug.debugfs_phy, ar,
|
||||
&fops_dfs_stats);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
@ -33,6 +33,7 @@ enum ath10k_debug_mask {
|
|||
ATH10K_DBG_MGMT = 0x00000100,
|
||||
ATH10K_DBG_DATA = 0x00000200,
|
||||
ATH10K_DBG_BMI = 0x00000400,
|
||||
ATH10K_DBG_REGULATORY = 0x00000800,
|
||||
ATH10K_DBG_ANY = 0xffffffff,
|
||||
};
|
||||
|
||||
|
@ -53,6 +54,8 @@ void ath10k_debug_read_service_map(struct ath10k *ar,
|
|||
void ath10k_debug_read_target_stats(struct ath10k *ar,
|
||||
struct wmi_stats_event *ev);
|
||||
|
||||
#define ATH10K_DFS_STAT_INC(ar, c) (ar->debug.dfs_stats.c++)
|
||||
|
||||
#else
|
||||
static inline int ath10k_debug_start(struct ath10k *ar)
|
||||
{
|
||||
|
@ -82,6 +85,9 @@ static inline void ath10k_debug_read_target_stats(struct ath10k *ar,
|
|||
struct wmi_stats_event *ev)
|
||||
{
|
||||
}
|
||||
|
||||
#define ATH10K_DFS_STAT_INC(ar, c) do { } while (0)
|
||||
|
||||
#endif /* CONFIG_ATH10K_DEBUGFS */
|
||||
|
||||
#ifdef CONFIG_ATH10K_DEBUG
|
||||
|
|
|
@ -191,6 +191,11 @@ static int ath10k_htc_tx_completion_handler(struct ath10k *ar,
|
|||
struct ath10k_htc *htc = &ar->htc;
|
||||
struct ath10k_htc_ep *ep = &htc->endpoint[eid];
|
||||
|
||||
if (!skb) {
|
||||
ath10k_warn("invalid sk_buff completion - NULL pointer. firmware crashed?\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
ath10k_htc_notify_tx_completion(ep, skb);
|
||||
/* the skb now belongs to the completion handler */
|
||||
|
||||
|
@ -534,14 +539,6 @@ int ath10k_htc_wait_target(struct ath10k_htc *htc)
|
|||
u16 credit_count;
|
||||
u16 credit_size;
|
||||
|
||||
reinit_completion(&htc->ctl_resp);
|
||||
|
||||
status = ath10k_hif_start(htc->ar);
|
||||
if (status) {
|
||||
ath10k_err("could not start HIF (%d)\n", status);
|
||||
goto err_start;
|
||||
}
|
||||
|
||||
status = wait_for_completion_timeout(&htc->ctl_resp,
|
||||
ATH10K_HTC_WAIT_TIMEOUT_HZ);
|
||||
if (status <= 0) {
|
||||
|
@ -549,15 +546,13 @@ int ath10k_htc_wait_target(struct ath10k_htc *htc)
|
|||
status = -ETIMEDOUT;
|
||||
|
||||
ath10k_err("ctl_resp never came in (%d)\n", status);
|
||||
goto err_target;
|
||||
return status;
|
||||
}
|
||||
|
||||
if (htc->control_resp_len < sizeof(msg->hdr) + sizeof(msg->ready)) {
|
||||
ath10k_err("Invalid HTC ready msg len:%d\n",
|
||||
htc->control_resp_len);
|
||||
|
||||
status = -ECOMM;
|
||||
goto err_target;
|
||||
return -ECOMM;
|
||||
}
|
||||
|
||||
msg = (struct ath10k_htc_msg *)htc->control_resp_buffer;
|
||||
|
@ -567,8 +562,7 @@ int ath10k_htc_wait_target(struct ath10k_htc *htc)
|
|||
|
||||
if (message_id != ATH10K_HTC_MSG_READY_ID) {
|
||||
ath10k_err("Invalid HTC ready msg: 0x%x\n", message_id);
|
||||
status = -ECOMM;
|
||||
goto err_target;
|
||||
return -ECOMM;
|
||||
}
|
||||
|
||||
htc->total_transmit_credits = credit_count;
|
||||
|
@ -581,9 +575,8 @@ int ath10k_htc_wait_target(struct ath10k_htc *htc)
|
|||
|
||||
if ((htc->total_transmit_credits == 0) ||
|
||||
(htc->target_credit_size == 0)) {
|
||||
status = -ECOMM;
|
||||
ath10k_err("Invalid credit size received\n");
|
||||
goto err_target;
|
||||
return -ECOMM;
|
||||
}
|
||||
|
||||
ath10k_htc_setup_target_buffer_assignments(htc);
|
||||
|
@ -600,14 +593,10 @@ int ath10k_htc_wait_target(struct ath10k_htc *htc)
|
|||
status = ath10k_htc_connect_service(htc, &conn_req, &conn_resp);
|
||||
if (status) {
|
||||
ath10k_err("could not connect to htc service (%d)\n", status);
|
||||
goto err_target;
|
||||
return status;
|
||||
}
|
||||
|
||||
return 0;
|
||||
err_target:
|
||||
ath10k_hif_stop(htc->ar);
|
||||
err_start:
|
||||
return status;
|
||||
}
|
||||
|
||||
int ath10k_htc_connect_service(struct ath10k_htc *htc,
|
||||
|
|
|
@ -104,8 +104,8 @@ int ath10k_htt_attach(struct ath10k *ar)
|
|||
|
||||
static int ath10k_htt_verify_version(struct ath10k_htt *htt)
|
||||
{
|
||||
ath10k_info("htt target version %d.%d\n",
|
||||
htt->target_version_major, htt->target_version_minor);
|
||||
ath10k_dbg(ATH10K_DBG_BOOT, "htt target version %d.%d\n",
|
||||
htt->target_version_major, htt->target_version_minor);
|
||||
|
||||
if (htt->target_version_major != 2 &&
|
||||
htt->target_version_major != 3) {
|
||||
|
|
|
@ -1182,6 +1182,7 @@ struct htt_rx_info {
|
|||
u32 info2;
|
||||
} rate;
|
||||
bool fcs_err;
|
||||
bool amsdu_more;
|
||||
};
|
||||
|
||||
struct ath10k_htt {
|
||||
|
|
|
@ -659,23 +659,6 @@ static void ath10k_htt_rx_amsdu(struct ath10k_htt *htt,
|
|||
memcpy(hdr_buf, hdr, hdr_len);
|
||||
hdr = (struct ieee80211_hdr *)hdr_buf;
|
||||
|
||||
/* FIXME: Hopefully this is a temporary measure.
|
||||
*
|
||||
* Reporting individual A-MSDU subframes means each reported frame
|
||||
* shares the same sequence number.
|
||||
*
|
||||
* mac80211 drops frames it recognizes as duplicates, i.e.
|
||||
* retransmission flag is set and sequence number matches sequence
|
||||
* number from a previous frame (as per IEEE 802.11-2012: 9.3.2.10
|
||||
* "Duplicate detection and recovery")
|
||||
*
|
||||
* To avoid frames being dropped clear retransmission flag for all
|
||||
* received A-MSDUs.
|
||||
*
|
||||
* Worst case: actual duplicate frames will be reported but this should
|
||||
* still be handled gracefully by other OSI/ISO layers. */
|
||||
hdr->frame_control &= cpu_to_le16(~IEEE80211_FCTL_RETRY);
|
||||
|
||||
first = skb;
|
||||
while (skb) {
|
||||
void *decap_hdr;
|
||||
|
@ -746,6 +729,9 @@ static void ath10k_htt_rx_amsdu(struct ath10k_htt *htt,
|
|||
skb = skb->next;
|
||||
info->skb->next = NULL;
|
||||
|
||||
if (skb)
|
||||
info->amsdu_more = true;
|
||||
|
||||
ath10k_process_rx(htt->ar, info);
|
||||
}
|
||||
|
||||
|
@ -959,6 +945,11 @@ static void ath10k_htt_rx_handler(struct ath10k_htt *htt,
|
|||
continue;
|
||||
}
|
||||
|
||||
if (test_bit(ATH10K_CAC_RUNNING, &htt->ar->dev_flags)) {
|
||||
ath10k_htt_rx_free_msdu_chain(msdu_head);
|
||||
continue;
|
||||
}
|
||||
|
||||
/* FIXME: we do not support chaining yet.
|
||||
* this needs investigation */
|
||||
if (msdu_chaining) {
|
||||
|
|
|
@ -85,16 +85,13 @@ void ath10k_htt_tx_free_msdu_id(struct ath10k_htt *htt, u16 msdu_id)
|
|||
|
||||
int ath10k_htt_tx_attach(struct ath10k_htt *htt)
|
||||
{
|
||||
u8 pipe;
|
||||
|
||||
spin_lock_init(&htt->tx_lock);
|
||||
init_waitqueue_head(&htt->empty_tx_wq);
|
||||
|
||||
/* At the beginning free queue number should hint us the maximum
|
||||
* queue length */
|
||||
pipe = htt->ar->htc.endpoint[htt->eid].ul_pipe_id;
|
||||
htt->max_num_pending_tx = ath10k_hif_get_free_queue_number(htt->ar,
|
||||
pipe);
|
||||
if (test_bit(ATH10K_FW_FEATURE_WMI_10X, htt->ar->fw_features))
|
||||
htt->max_num_pending_tx = TARGET_10X_NUM_MSDU_DESC;
|
||||
else
|
||||
htt->max_num_pending_tx = TARGET_NUM_MSDU_DESC;
|
||||
|
||||
ath10k_dbg(ATH10K_DBG_BOOT, "htt tx max num pending tx %d\n",
|
||||
htt->max_num_pending_tx);
|
||||
|
|
|
@ -269,6 +269,7 @@ enum ath10k_mcast2ucast_mode {
|
|||
#define CORE_CTRL_CPU_INTR_MASK 0x00002000
|
||||
#define CORE_CTRL_ADDRESS 0x0000
|
||||
#define PCIE_INTR_ENABLE_ADDRESS 0x0008
|
||||
#define PCIE_INTR_CAUSE_ADDRESS 0x000c
|
||||
#define PCIE_INTR_CLR_ADDRESS 0x0014
|
||||
#define SCRATCH_3_ADDRESS 0x0030
|
||||
|
||||
|
|
|
@ -322,12 +322,16 @@ static int ath10k_peer_create(struct ath10k *ar, u32 vdev_id, const u8 *addr)
|
|||
lockdep_assert_held(&ar->conf_mutex);
|
||||
|
||||
ret = ath10k_wmi_peer_create(ar, vdev_id, addr);
|
||||
if (ret)
|
||||
if (ret) {
|
||||
ath10k_warn("Failed to create wmi peer: %i\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = ath10k_wait_for_peer_created(ar, vdev_id, addr);
|
||||
if (ret)
|
||||
if (ret) {
|
||||
ath10k_warn("Failed to wait for created wmi peer: %i\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
@ -450,15 +454,19 @@ static int ath10k_vdev_start(struct ath10k_vif *arvif)
|
|||
|
||||
arg.channel.mode = chan_to_phymode(&conf->chandef);
|
||||
|
||||
arg.channel.min_power = channel->max_power * 3;
|
||||
arg.channel.max_power = channel->max_power * 4;
|
||||
arg.channel.max_reg_power = channel->max_reg_power * 4;
|
||||
arg.channel.max_antenna_gain = channel->max_antenna_gain;
|
||||
arg.channel.min_power = 0;
|
||||
arg.channel.max_power = channel->max_power * 2;
|
||||
arg.channel.max_reg_power = channel->max_reg_power * 2;
|
||||
arg.channel.max_antenna_gain = channel->max_antenna_gain * 2;
|
||||
|
||||
if (arvif->vdev_type == WMI_VDEV_TYPE_AP) {
|
||||
arg.ssid = arvif->u.ap.ssid;
|
||||
arg.ssid_len = arvif->u.ap.ssid_len;
|
||||
arg.hidden_ssid = arvif->u.ap.hidden_ssid;
|
||||
|
||||
/* For now allow DFS for AP mode */
|
||||
arg.channel.chan_radar =
|
||||
!!(channel->flags & IEEE80211_CHAN_RADAR);
|
||||
} else if (arvif->vdev_type == WMI_VDEV_TYPE_IBSS) {
|
||||
arg.ssid = arvif->vif->bss_conf.ssid;
|
||||
arg.ssid_len = arvif->vif->bss_conf.ssid_len;
|
||||
|
@ -516,6 +524,11 @@ static int ath10k_monitor_start(struct ath10k *ar, int vdev_id)
|
|||
|
||||
lockdep_assert_held(&ar->conf_mutex);
|
||||
|
||||
if (!ar->monitor_present) {
|
||||
ath10k_warn("mac montor stop -- monitor is not present\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
arg.vdev_id = vdev_id;
|
||||
arg.channel.freq = channel->center_freq;
|
||||
arg.channel.band_center_freq1 = ar->hw->conf.chandef.center_freq1;
|
||||
|
@ -523,11 +536,13 @@ static int ath10k_monitor_start(struct ath10k *ar, int vdev_id)
|
|||
/* TODO setup this dynamically, what in case we
|
||||
don't have any vifs? */
|
||||
arg.channel.mode = chan_to_phymode(&ar->hw->conf.chandef);
|
||||
arg.channel.chan_radar =
|
||||
!!(channel->flags & IEEE80211_CHAN_RADAR);
|
||||
|
||||
arg.channel.min_power = channel->max_power * 3;
|
||||
arg.channel.max_power = channel->max_power * 4;
|
||||
arg.channel.max_reg_power = channel->max_reg_power * 4;
|
||||
arg.channel.max_antenna_gain = channel->max_antenna_gain;
|
||||
arg.channel.min_power = 0;
|
||||
arg.channel.max_power = channel->max_power * 2;
|
||||
arg.channel.max_reg_power = channel->max_reg_power * 2;
|
||||
arg.channel.max_antenna_gain = channel->max_antenna_gain * 2;
|
||||
|
||||
ret = ath10k_wmi_vdev_start(ar, &arg);
|
||||
if (ret) {
|
||||
|
@ -566,6 +581,16 @@ static int ath10k_monitor_stop(struct ath10k *ar)
|
|||
|
||||
lockdep_assert_held(&ar->conf_mutex);
|
||||
|
||||
if (!ar->monitor_present) {
|
||||
ath10k_warn("mac montor stop -- monitor is not present\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (!ar->monitor_enabled) {
|
||||
ath10k_warn("mac montor stop -- monitor is not enabled\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
ret = ath10k_wmi_vdev_down(ar, ar->monitor_vdev_id);
|
||||
if (ret)
|
||||
ath10k_warn("Monitor vdev down failed: %d\n", ret);
|
||||
|
@ -647,6 +672,107 @@ static int ath10k_monitor_destroy(struct ath10k *ar)
|
|||
return ret;
|
||||
}
|
||||
|
||||
static int ath10k_start_cac(struct ath10k *ar)
|
||||
{
|
||||
int ret;
|
||||
|
||||
lockdep_assert_held(&ar->conf_mutex);
|
||||
|
||||
set_bit(ATH10K_CAC_RUNNING, &ar->dev_flags);
|
||||
|
||||
ret = ath10k_monitor_create(ar);
|
||||
if (ret) {
|
||||
clear_bit(ATH10K_CAC_RUNNING, &ar->dev_flags);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = ath10k_monitor_start(ar, ar->monitor_vdev_id);
|
||||
if (ret) {
|
||||
clear_bit(ATH10K_CAC_RUNNING, &ar->dev_flags);
|
||||
ath10k_monitor_destroy(ar);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ath10k_dbg(ATH10K_DBG_MAC, "mac cac start monitor vdev %d\n",
|
||||
ar->monitor_vdev_id);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int ath10k_stop_cac(struct ath10k *ar)
|
||||
{
|
||||
lockdep_assert_held(&ar->conf_mutex);
|
||||
|
||||
/* CAC is not running - do nothing */
|
||||
if (!test_bit(ATH10K_CAC_RUNNING, &ar->dev_flags))
|
||||
return 0;
|
||||
|
||||
ath10k_monitor_stop(ar);
|
||||
ath10k_monitor_destroy(ar);
|
||||
clear_bit(ATH10K_CAC_RUNNING, &ar->dev_flags);
|
||||
|
||||
ath10k_dbg(ATH10K_DBG_MAC, "mac cac finished\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const char *ath10k_dfs_state(enum nl80211_dfs_state dfs_state)
|
||||
{
|
||||
switch (dfs_state) {
|
||||
case NL80211_DFS_USABLE:
|
||||
return "USABLE";
|
||||
case NL80211_DFS_UNAVAILABLE:
|
||||
return "UNAVAILABLE";
|
||||
case NL80211_DFS_AVAILABLE:
|
||||
return "AVAILABLE";
|
||||
default:
|
||||
WARN_ON(1);
|
||||
return "bug";
|
||||
}
|
||||
}
|
||||
|
||||
static void ath10k_config_radar_detection(struct ath10k *ar)
|
||||
{
|
||||
struct ieee80211_channel *chan = ar->hw->conf.chandef.chan;
|
||||
bool radar = ar->hw->conf.radar_enabled;
|
||||
bool chan_radar = !!(chan->flags & IEEE80211_CHAN_RADAR);
|
||||
enum nl80211_dfs_state dfs_state = chan->dfs_state;
|
||||
int ret;
|
||||
|
||||
lockdep_assert_held(&ar->conf_mutex);
|
||||
|
||||
ath10k_dbg(ATH10K_DBG_MAC,
|
||||
"mac radar config update: chan %dMHz radar %d chan radar %d chan state %s\n",
|
||||
chan->center_freq, radar, chan_radar,
|
||||
ath10k_dfs_state(dfs_state));
|
||||
|
||||
/*
|
||||
* It's safe to call it even if CAC is not started.
|
||||
* This call here guarantees changing channel, etc. will stop CAC.
|
||||
*/
|
||||
ath10k_stop_cac(ar);
|
||||
|
||||
if (!radar)
|
||||
return;
|
||||
|
||||
if (!chan_radar)
|
||||
return;
|
||||
|
||||
if (dfs_state != NL80211_DFS_USABLE)
|
||||
return;
|
||||
|
||||
ret = ath10k_start_cac(ar);
|
||||
if (ret) {
|
||||
/*
|
||||
* Not possible to start CAC on current channel so starting
|
||||
* radiation is not allowed, make this channel DFS_UNAVAILABLE
|
||||
* by indicating that radar was detected.
|
||||
*/
|
||||
ath10k_warn("failed to start CAC (%d)\n", ret);
|
||||
ieee80211_radar_detected(ar->hw);
|
||||
}
|
||||
}
|
||||
|
||||
static void ath10k_control_beaconing(struct ath10k_vif *arvif,
|
||||
struct ieee80211_bss_conf *info)
|
||||
{
|
||||
|
@ -1356,14 +1482,17 @@ static int ath10k_update_channel_list(struct ath10k *ar)
|
|||
ch->ht40plus =
|
||||
!(channel->flags & IEEE80211_CHAN_NO_HT40PLUS);
|
||||
|
||||
ch->chan_radar =
|
||||
!!(channel->flags & IEEE80211_CHAN_RADAR);
|
||||
|
||||
passive = channel->flags & IEEE80211_CHAN_NO_IR;
|
||||
ch->passive = passive;
|
||||
|
||||
ch->freq = channel->center_freq;
|
||||
ch->min_power = channel->max_power * 3;
|
||||
ch->max_power = channel->max_power * 4;
|
||||
ch->max_reg_power = channel->max_reg_power * 4;
|
||||
ch->max_antenna_gain = channel->max_antenna_gain;
|
||||
ch->min_power = 0;
|
||||
ch->max_power = channel->max_power * 2;
|
||||
ch->max_reg_power = channel->max_reg_power * 2;
|
||||
ch->max_antenna_gain = channel->max_antenna_gain * 2;
|
||||
ch->reg_class_id = 0; /* FIXME */
|
||||
|
||||
/* FIXME: why use only legacy modes, why not any
|
||||
|
@ -1423,9 +1552,20 @@ static void ath10k_reg_notifier(struct wiphy *wiphy,
|
|||
{
|
||||
struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
|
||||
struct ath10k *ar = hw->priv;
|
||||
bool result;
|
||||
|
||||
ath_reg_notifier_apply(wiphy, request, &ar->ath_common.regulatory);
|
||||
|
||||
if (config_enabled(CONFIG_ATH10K_DFS_CERTIFIED) && ar->dfs_detector) {
|
||||
ath10k_dbg(ATH10K_DBG_REGULATORY, "dfs region 0x%x\n",
|
||||
request->dfs_region);
|
||||
result = ar->dfs_detector->set_dfs_domain(ar->dfs_detector,
|
||||
request->dfs_region);
|
||||
if (!result)
|
||||
ath10k_warn("dfs region 0x%X not supported, will trigger radar for every pulse\n",
|
||||
request->dfs_region);
|
||||
}
|
||||
|
||||
mutex_lock(&ar->conf_mutex);
|
||||
if (ar->state == ATH10K_STATE_ON)
|
||||
ath10k_regd_update(ar);
|
||||
|
@ -1714,8 +1854,10 @@ void ath10k_mgmt_over_wmi_tx_work(struct work_struct *work)
|
|||
break;
|
||||
|
||||
ret = ath10k_wmi_mgmt_tx(ar, skb);
|
||||
if (ret)
|
||||
if (ret) {
|
||||
ath10k_warn("wmi mgmt_tx failed (%d)\n", ret);
|
||||
ieee80211_free_txskb(ar->hw, skb);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -1889,6 +2031,7 @@ void ath10k_halt(struct ath10k *ar)
|
|||
{
|
||||
lockdep_assert_held(&ar->conf_mutex);
|
||||
|
||||
ath10k_stop_cac(ar);
|
||||
del_timer_sync(&ar->scan.timeout);
|
||||
ath10k_offchan_tx_purge(ar);
|
||||
ath10k_mgmt_over_wmi_tx_purge(ar);
|
||||
|
@ -1943,7 +2086,7 @@ static int ath10k_start(struct ieee80211_hw *hw)
|
|||
ath10k_warn("could not enable WMI_PDEV_PARAM_PMF_QOS (%d)\n",
|
||||
ret);
|
||||
|
||||
ret = ath10k_wmi_pdev_set_param(ar, ar->wmi.pdev_param->dynamic_bw, 0);
|
||||
ret = ath10k_wmi_pdev_set_param(ar, ar->wmi.pdev_param->dynamic_bw, 1);
|
||||
if (ret)
|
||||
ath10k_warn("could not init WMI_PDEV_PARAM_DYNAMIC_BW (%d)\n",
|
||||
ret);
|
||||
|
@ -1998,15 +2141,40 @@ static int ath10k_config(struct ieee80211_hw *hw, u32 changed)
|
|||
struct ath10k *ar = hw->priv;
|
||||
struct ieee80211_conf *conf = &hw->conf;
|
||||
int ret = 0;
|
||||
u32 param;
|
||||
|
||||
mutex_lock(&ar->conf_mutex);
|
||||
|
||||
if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
|
||||
ath10k_dbg(ATH10K_DBG_MAC, "mac config channel %d mhz\n",
|
||||
conf->chandef.chan->center_freq);
|
||||
ath10k_dbg(ATH10K_DBG_MAC,
|
||||
"mac config channel %d mhz flags 0x%x\n",
|
||||
conf->chandef.chan->center_freq,
|
||||
conf->chandef.chan->flags);
|
||||
|
||||
spin_lock_bh(&ar->data_lock);
|
||||
ar->rx_channel = conf->chandef.chan;
|
||||
spin_unlock_bh(&ar->data_lock);
|
||||
|
||||
ath10k_config_radar_detection(ar);
|
||||
}
|
||||
|
||||
if (changed & IEEE80211_CONF_CHANGE_POWER) {
|
||||
ath10k_dbg(ATH10K_DBG_MAC, "mac config power %d\n",
|
||||
hw->conf.power_level);
|
||||
|
||||
param = ar->wmi.pdev_param->txpower_limit2g;
|
||||
ret = ath10k_wmi_pdev_set_param(ar, param,
|
||||
hw->conf.power_level * 2);
|
||||
if (ret)
|
||||
ath10k_warn("mac failed to set 2g txpower %d (%d)\n",
|
||||
hw->conf.power_level, ret);
|
||||
|
||||
param = ar->wmi.pdev_param->txpower_limit5g;
|
||||
ret = ath10k_wmi_pdev_set_param(ar, param,
|
||||
hw->conf.power_level * 2);
|
||||
if (ret)
|
||||
ath10k_warn("mac failed to set 5g txpower %d (%d)\n",
|
||||
hw->conf.power_level, ret);
|
||||
}
|
||||
|
||||
if (changed & IEEE80211_CONF_CHANGE_PS)
|
||||
|
@ -2049,6 +2217,7 @@ static int ath10k_add_interface(struct ieee80211_hw *hw,
|
|||
arvif->vif = vif;
|
||||
|
||||
INIT_WORK(&arvif->wep_key_work, ath10k_tx_wep_key_work);
|
||||
INIT_LIST_HEAD(&arvif->list);
|
||||
|
||||
if ((vif->type == NL80211_IFTYPE_MONITOR) && ar->monitor_present) {
|
||||
ath10k_warn("Only one monitor interface allowed\n");
|
||||
|
@ -2265,8 +2434,14 @@ static void ath10k_configure_filter(struct ieee80211_hw *hw,
|
|||
*total_flags &= SUPPORTED_FILTERS;
|
||||
ar->filter_flags = *total_flags;
|
||||
|
||||
/* Monitor must not be started if it wasn't created first.
|
||||
* Promiscuous mode may be started on a non-monitor interface - in
|
||||
* such case the monitor vdev is not created so starting the
|
||||
* monitor makes no sense. Since ath10k uses no special RX filters
|
||||
* (only BSS filter in STA mode) there's no need for any special
|
||||
* action here. */
|
||||
if ((ar->filter_flags & FIF_PROMISC_IN_BSS) &&
|
||||
!ar->monitor_enabled) {
|
||||
!ar->monitor_enabled && ar->monitor_present) {
|
||||
ath10k_dbg(ATH10K_DBG_MAC, "mac monitor %d start\n",
|
||||
ar->monitor_vdev_id);
|
||||
|
||||
|
@ -2274,7 +2449,7 @@ static void ath10k_configure_filter(struct ieee80211_hw *hw,
|
|||
if (ret)
|
||||
ath10k_warn("Unable to start monitor mode\n");
|
||||
} else if (!(ar->filter_flags & FIF_PROMISC_IN_BSS) &&
|
||||
ar->monitor_enabled) {
|
||||
ar->monitor_enabled && ar->monitor_present) {
|
||||
ath10k_dbg(ATH10K_DBG_MAC, "mac monitor %d stop\n",
|
||||
ar->monitor_vdev_id);
|
||||
|
||||
|
@ -2360,8 +2535,8 @@ static void ath10k_bss_info_changed(struct ieee80211_hw *hw,
|
|||
ret = ath10k_peer_create(ar, arvif->vdev_id,
|
||||
info->bssid);
|
||||
if (ret)
|
||||
ath10k_warn("Failed to add peer: %pM for VDEV: %d\n",
|
||||
info->bssid, arvif->vdev_id);
|
||||
ath10k_warn("Failed to add peer %pM for vdev %d when changin bssid: %i\n",
|
||||
info->bssid, arvif->vdev_id, ret);
|
||||
|
||||
if (vif->type == NL80211_IFTYPE_STATION) {
|
||||
/*
|
||||
|
@ -2542,6 +2717,44 @@ static void ath10k_cancel_hw_scan(struct ieee80211_hw *hw,
|
|||
mutex_unlock(&ar->conf_mutex);
|
||||
}
|
||||
|
||||
static void ath10k_set_key_h_def_keyidx(struct ath10k *ar,
|
||||
struct ath10k_vif *arvif,
|
||||
enum set_key_cmd cmd,
|
||||
struct ieee80211_key_conf *key)
|
||||
{
|
||||
u32 vdev_param = arvif->ar->wmi.vdev_param->def_keyid;
|
||||
int ret;
|
||||
|
||||
/* 10.1 firmware branch requires default key index to be set to group
|
||||
* key index after installing it. Otherwise FW/HW Txes corrupted
|
||||
* frames with multi-vif APs. This is not required for main firmware
|
||||
* branch (e.g. 636).
|
||||
*
|
||||
* FIXME: This has been tested only in AP. It remains unknown if this
|
||||
* is required for multi-vif STA interfaces on 10.1 */
|
||||
|
||||
if (arvif->vdev_type != WMI_VDEV_TYPE_AP)
|
||||
return;
|
||||
|
||||
if (key->cipher == WLAN_CIPHER_SUITE_WEP40)
|
||||
return;
|
||||
|
||||
if (key->cipher == WLAN_CIPHER_SUITE_WEP104)
|
||||
return;
|
||||
|
||||
if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE)
|
||||
return;
|
||||
|
||||
if (cmd != SET_KEY)
|
||||
return;
|
||||
|
||||
ret = ath10k_wmi_vdev_set_param(ar, arvif->vdev_id, vdev_param,
|
||||
key->keyidx);
|
||||
if (ret)
|
||||
ath10k_warn("failed to set group key as default key: %d\n",
|
||||
ret);
|
||||
}
|
||||
|
||||
static int ath10k_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
|
||||
struct ieee80211_vif *vif, struct ieee80211_sta *sta,
|
||||
struct ieee80211_key_conf *key)
|
||||
|
@ -2603,6 +2816,8 @@ static int ath10k_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
|
|||
goto exit;
|
||||
}
|
||||
|
||||
ath10k_set_key_h_def_keyidx(ar, arvif, cmd, key);
|
||||
|
||||
spin_lock_bh(&ar->data_lock);
|
||||
peer = ath10k_peer_find(ar, arvif->vdev_id, peer_addr);
|
||||
if (peer && cmd == SET_KEY)
|
||||
|
@ -2643,8 +2858,8 @@ static int ath10k_sta_state(struct ieee80211_hw *hw,
|
|||
|
||||
ret = ath10k_peer_create(ar, arvif->vdev_id, sta->addr);
|
||||
if (ret)
|
||||
ath10k_warn("Failed to add peer: %pM for VDEV: %d\n",
|
||||
sta->addr, arvif->vdev_id);
|
||||
ath10k_warn("Failed to add peer %pM for vdev %d when adding a new sta: %i\n",
|
||||
sta->addr, arvif->vdev_id, ret);
|
||||
} else if ((old_state == IEEE80211_STA_NONE &&
|
||||
new_state == IEEE80211_STA_NOTEXIST)) {
|
||||
/*
|
||||
|
@ -3249,12 +3464,36 @@ static const struct ieee80211_iface_limit ath10k_if_limits[] = {
|
|||
},
|
||||
};
|
||||
|
||||
static const struct ieee80211_iface_combination ath10k_if_comb = {
|
||||
.limits = ath10k_if_limits,
|
||||
.n_limits = ARRAY_SIZE(ath10k_if_limits),
|
||||
.max_interfaces = 8,
|
||||
.num_different_channels = 1,
|
||||
.beacon_int_infra_match = true,
|
||||
#ifdef CONFIG_ATH10K_DFS_CERTIFIED
|
||||
static const struct ieee80211_iface_limit ath10k_if_dfs_limits[] = {
|
||||
{
|
||||
.max = 8,
|
||||
.types = BIT(NL80211_IFTYPE_AP)
|
||||
},
|
||||
};
|
||||
#endif
|
||||
|
||||
static const struct ieee80211_iface_combination ath10k_if_comb[] = {
|
||||
{
|
||||
.limits = ath10k_if_limits,
|
||||
.n_limits = ARRAY_SIZE(ath10k_if_limits),
|
||||
.max_interfaces = 8,
|
||||
.num_different_channels = 1,
|
||||
.beacon_int_infra_match = true,
|
||||
},
|
||||
#ifdef CONFIG_ATH10K_DFS_CERTIFIED
|
||||
{
|
||||
.limits = ath10k_if_dfs_limits,
|
||||
.n_limits = ARRAY_SIZE(ath10k_if_dfs_limits),
|
||||
.max_interfaces = 8,
|
||||
.num_different_channels = 1,
|
||||
.beacon_int_infra_match = true,
|
||||
.radar_detect_widths = BIT(NL80211_CHAN_WIDTH_20_NOHT) |
|
||||
BIT(NL80211_CHAN_WIDTH_20) |
|
||||
BIT(NL80211_CHAN_WIDTH_40) |
|
||||
BIT(NL80211_CHAN_WIDTH_80),
|
||||
}
|
||||
#endif
|
||||
};
|
||||
|
||||
static struct ieee80211_sta_vht_cap ath10k_create_vht_cap(struct ath10k *ar)
|
||||
|
@ -3478,11 +3717,21 @@ int ath10k_mac_register(struct ath10k *ar)
|
|||
*/
|
||||
ar->hw->queues = 4;
|
||||
|
||||
ar->hw->wiphy->iface_combinations = &ath10k_if_comb;
|
||||
ar->hw->wiphy->n_iface_combinations = 1;
|
||||
ar->hw->wiphy->iface_combinations = ath10k_if_comb;
|
||||
ar->hw->wiphy->n_iface_combinations = ARRAY_SIZE(ath10k_if_comb);
|
||||
|
||||
ar->hw->netdev_features = NETIF_F_HW_CSUM;
|
||||
|
||||
if (config_enabled(CONFIG_ATH10K_DFS_CERTIFIED)) {
|
||||
/* Init ath dfs pattern detector */
|
||||
ar->ath_common.debug_mask = ATH_DBG_DFS;
|
||||
ar->dfs_detector = dfs_pattern_detector_init(&ar->ath_common,
|
||||
NL80211_DFS_UNSET);
|
||||
|
||||
if (!ar->dfs_detector)
|
||||
ath10k_warn("dfs pattern detector init failed\n");
|
||||
}
|
||||
|
||||
ret = ath_regd_init(&ar->ath_common.regulatory, ar->hw->wiphy,
|
||||
ath10k_reg_notifier);
|
||||
if (ret) {
|
||||
|
@ -3518,6 +3767,9 @@ void ath10k_mac_unregister(struct ath10k *ar)
|
|||
{
|
||||
ieee80211_unregister_hw(ar->hw);
|
||||
|
||||
if (config_enabled(CONFIG_ATH10K_DFS_CERTIFIED) && ar->dfs_detector)
|
||||
ar->dfs_detector->exit(ar->dfs_detector);
|
||||
|
||||
kfree(ar->mac.sbands[IEEE80211_BAND_2GHZ].channels);
|
||||
kfree(ar->mac.sbands[IEEE80211_BAND_5GHZ].channels);
|
||||
|
||||
|
|
File diff suppressed because it is too large
Load diff
|
@ -198,9 +198,7 @@ struct ath10k_pci {
|
|||
|
||||
struct tasklet_struct intr_tq;
|
||||
struct tasklet_struct msi_fw_err;
|
||||
|
||||
/* Number of Copy Engines supported */
|
||||
unsigned int ce_count;
|
||||
struct tasklet_struct early_irq_tasklet;
|
||||
|
||||
int started;
|
||||
|
||||
|
@ -318,6 +316,16 @@ static inline u32 ath10k_pci_read32(struct ath10k *ar, u32 offset)
|
|||
return ioread32(ar_pci->mem + offset);
|
||||
}
|
||||
|
||||
static inline u32 ath10k_pci_soc_read32(struct ath10k *ar, u32 addr)
|
||||
{
|
||||
return ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS + addr);
|
||||
}
|
||||
|
||||
static inline void ath10k_pci_soc_write32(struct ath10k *ar, u32 addr, u32 val)
|
||||
{
|
||||
ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + addr, val);
|
||||
}
|
||||
|
||||
int ath10k_do_pci_wake(struct ath10k *ar);
|
||||
void ath10k_do_pci_sleep(struct ath10k *ar);
|
||||
|
||||
|
|
|
@ -75,6 +75,7 @@ void ath10k_txrx_tx_unref(struct ath10k_htt *htt,
|
|||
ath10k_report_offchan_tx(htt->ar, msdu);
|
||||
|
||||
info = IEEE80211_SKB_CB(msdu);
|
||||
memset(&info->status, 0, sizeof(info->status));
|
||||
|
||||
if (tx_done->discard) {
|
||||
ieee80211_free_txskb(htt->ar->hw, msdu);
|
||||
|
@ -183,7 +184,7 @@ static void process_rx_rates(struct ath10k *ar, struct htt_rx_info *info,
|
|||
/* VHT-SIG-A1 in info 1, VHT-SIG-A2 in info2
|
||||
TODO check this */
|
||||
mcs = (info2 >> 4) & 0x0F;
|
||||
nss = (info1 >> 10) & 0x07;
|
||||
nss = ((info1 >> 10) & 0x07) + 1;
|
||||
bw = info1 & 3;
|
||||
sgi = info2 & 1;
|
||||
|
||||
|
@ -236,6 +237,9 @@ void ath10k_process_rx(struct ath10k *ar, struct htt_rx_info *info)
|
|||
if (info->fcs_err)
|
||||
status->flag |= RX_FLAG_FAILED_FCS_CRC;
|
||||
|
||||
if (info->amsdu_more)
|
||||
status->flag |= RX_FLAG_AMSDU_MORE;
|
||||
|
||||
status->signal = info->signal;
|
||||
|
||||
spin_lock_bh(&ar->data_lock);
|
||||
|
|
|
@ -674,10 +674,8 @@ int ath10k_wmi_mgmt_tx(struct ath10k *ar, struct sk_buff *skb)
|
|||
|
||||
/* Send the management frame buffer to the target */
|
||||
ret = ath10k_wmi_cmd_send(ar, wmi_skb, ar->wmi.cmd->mgmt_tx_cmdid);
|
||||
if (ret) {
|
||||
dev_kfree_skb_any(skb);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* TODO: report tx status to mac80211 - temporary just ACK */
|
||||
info->flags |= IEEE80211_TX_STAT_ACK;
|
||||
|
@ -909,6 +907,11 @@ static int ath10k_wmi_event_mgmt_rx(struct ath10k *ar, struct sk_buff *skb)
|
|||
ath10k_dbg(ATH10K_DBG_MGMT,
|
||||
"event mgmt rx status %08x\n", rx_status);
|
||||
|
||||
if (test_bit(ATH10K_CAC_RUNNING, &ar->dev_flags)) {
|
||||
dev_kfree_skb(skb);
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (rx_status & WMI_RX_STATUS_ERR_DECRYPT) {
|
||||
dev_kfree_skb(skb);
|
||||
return 0;
|
||||
|
@ -1383,9 +1386,259 @@ static void ath10k_wmi_event_tbttoffset_update(struct ath10k *ar,
|
|||
ath10k_dbg(ATH10K_DBG_WMI, "WMI_TBTTOFFSET_UPDATE_EVENTID\n");
|
||||
}
|
||||
|
||||
static void ath10k_dfs_radar_report(struct ath10k *ar,
|
||||
struct wmi_single_phyerr_rx_event *event,
|
||||
struct phyerr_radar_report *rr,
|
||||
u64 tsf)
|
||||
{
|
||||
u32 reg0, reg1, tsf32l;
|
||||
struct pulse_event pe;
|
||||
u64 tsf64;
|
||||
u8 rssi, width;
|
||||
|
||||
reg0 = __le32_to_cpu(rr->reg0);
|
||||
reg1 = __le32_to_cpu(rr->reg1);
|
||||
|
||||
ath10k_dbg(ATH10K_DBG_REGULATORY,
|
||||
"wmi phyerr radar report chirp %d max_width %d agc_total_gain %d pulse_delta_diff %d\n",
|
||||
MS(reg0, RADAR_REPORT_REG0_PULSE_IS_CHIRP),
|
||||
MS(reg0, RADAR_REPORT_REG0_PULSE_IS_MAX_WIDTH),
|
||||
MS(reg0, RADAR_REPORT_REG0_AGC_TOTAL_GAIN),
|
||||
MS(reg0, RADAR_REPORT_REG0_PULSE_DELTA_DIFF));
|
||||
ath10k_dbg(ATH10K_DBG_REGULATORY,
|
||||
"wmi phyerr radar report pulse_delta_pean %d pulse_sidx %d fft_valid %d agc_mb_gain %d subchan_mask %d\n",
|
||||
MS(reg0, RADAR_REPORT_REG0_PULSE_DELTA_PEAK),
|
||||
MS(reg0, RADAR_REPORT_REG0_PULSE_SIDX),
|
||||
MS(reg1, RADAR_REPORT_REG1_PULSE_SRCH_FFT_VALID),
|
||||
MS(reg1, RADAR_REPORT_REG1_PULSE_AGC_MB_GAIN),
|
||||
MS(reg1, RADAR_REPORT_REG1_PULSE_SUBCHAN_MASK));
|
||||
ath10k_dbg(ATH10K_DBG_REGULATORY,
|
||||
"wmi phyerr radar report pulse_tsf_offset 0x%X pulse_dur: %d\n",
|
||||
MS(reg1, RADAR_REPORT_REG1_PULSE_TSF_OFFSET),
|
||||
MS(reg1, RADAR_REPORT_REG1_PULSE_DUR));
|
||||
|
||||
if (!ar->dfs_detector)
|
||||
return;
|
||||
|
||||
/* report event to DFS pattern detector */
|
||||
tsf32l = __le32_to_cpu(event->hdr.tsf_timestamp);
|
||||
tsf64 = tsf & (~0xFFFFFFFFULL);
|
||||
tsf64 |= tsf32l;
|
||||
|
||||
width = MS(reg1, RADAR_REPORT_REG1_PULSE_DUR);
|
||||
rssi = event->hdr.rssi_combined;
|
||||
|
||||
/* hardware store this as 8 bit signed value,
|
||||
* set to zero if negative number
|
||||
*/
|
||||
if (rssi & 0x80)
|
||||
rssi = 0;
|
||||
|
||||
pe.ts = tsf64;
|
||||
pe.freq = ar->hw->conf.chandef.chan->center_freq;
|
||||
pe.width = width;
|
||||
pe.rssi = rssi;
|
||||
|
||||
ath10k_dbg(ATH10K_DBG_REGULATORY,
|
||||
"dfs add pulse freq: %d, width: %d, rssi %d, tsf: %llX\n",
|
||||
pe.freq, pe.width, pe.rssi, pe.ts);
|
||||
|
||||
ATH10K_DFS_STAT_INC(ar, pulses_detected);
|
||||
|
||||
if (!ar->dfs_detector->add_pulse(ar->dfs_detector, &pe)) {
|
||||
ath10k_dbg(ATH10K_DBG_REGULATORY,
|
||||
"dfs no pulse pattern detected, yet\n");
|
||||
return;
|
||||
}
|
||||
|
||||
ath10k_dbg(ATH10K_DBG_REGULATORY, "dfs radar detected\n");
|
||||
ATH10K_DFS_STAT_INC(ar, radar_detected);
|
||||
|
||||
/* Control radar events reporting in debugfs file
|
||||
dfs_block_radar_events */
|
||||
if (ar->dfs_block_radar_events) {
|
||||
ath10k_info("DFS Radar detected, but ignored as requested\n");
|
||||
return;
|
||||
}
|
||||
|
||||
ieee80211_radar_detected(ar->hw);
|
||||
}
|
||||
|
||||
static int ath10k_dfs_fft_report(struct ath10k *ar,
|
||||
struct wmi_single_phyerr_rx_event *event,
|
||||
struct phyerr_fft_report *fftr,
|
||||
u64 tsf)
|
||||
{
|
||||
u32 reg0, reg1;
|
||||
u8 rssi, peak_mag;
|
||||
|
||||
reg0 = __le32_to_cpu(fftr->reg0);
|
||||
reg1 = __le32_to_cpu(fftr->reg1);
|
||||
rssi = event->hdr.rssi_combined;
|
||||
|
||||
ath10k_dbg(ATH10K_DBG_REGULATORY,
|
||||
"wmi phyerr fft report total_gain_db %d base_pwr_db %d fft_chn_idx %d peak_sidx %d\n",
|
||||
MS(reg0, SEARCH_FFT_REPORT_REG0_TOTAL_GAIN_DB),
|
||||
MS(reg0, SEARCH_FFT_REPORT_REG0_BASE_PWR_DB),
|
||||
MS(reg0, SEARCH_FFT_REPORT_REG0_FFT_CHN_IDX),
|
||||
MS(reg0, SEARCH_FFT_REPORT_REG0_PEAK_SIDX));
|
||||
ath10k_dbg(ATH10K_DBG_REGULATORY,
|
||||
"wmi phyerr fft report rel_pwr_db %d avgpwr_db %d peak_mag %d num_store_bin %d\n",
|
||||
MS(reg1, SEARCH_FFT_REPORT_REG1_RELPWR_DB),
|
||||
MS(reg1, SEARCH_FFT_REPORT_REG1_AVGPWR_DB),
|
||||
MS(reg1, SEARCH_FFT_REPORT_REG1_PEAK_MAG),
|
||||
MS(reg1, SEARCH_FFT_REPORT_REG1_NUM_STR_BINS_IB));
|
||||
|
||||
peak_mag = MS(reg1, SEARCH_FFT_REPORT_REG1_PEAK_MAG);
|
||||
|
||||
/* false event detection */
|
||||
if (rssi == DFS_RSSI_POSSIBLY_FALSE &&
|
||||
peak_mag < 2 * DFS_PEAK_MAG_THOLD_POSSIBLY_FALSE) {
|
||||
ath10k_dbg(ATH10K_DBG_REGULATORY, "dfs false pulse detected\n");
|
||||
ATH10K_DFS_STAT_INC(ar, pulses_discarded);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void ath10k_wmi_event_dfs(struct ath10k *ar,
|
||||
struct wmi_single_phyerr_rx_event *event,
|
||||
u64 tsf)
|
||||
{
|
||||
int buf_len, tlv_len, res, i = 0;
|
||||
struct phyerr_tlv *tlv;
|
||||
struct phyerr_radar_report *rr;
|
||||
struct phyerr_fft_report *fftr;
|
||||
u8 *tlv_buf;
|
||||
|
||||
buf_len = __le32_to_cpu(event->hdr.buf_len);
|
||||
ath10k_dbg(ATH10K_DBG_REGULATORY,
|
||||
"wmi event dfs err_code %d rssi %d tsfl 0x%X tsf64 0x%llX len %d\n",
|
||||
event->hdr.phy_err_code, event->hdr.rssi_combined,
|
||||
__le32_to_cpu(event->hdr.tsf_timestamp), tsf, buf_len);
|
||||
|
||||
/* Skip event if DFS disabled */
|
||||
if (!config_enabled(CONFIG_ATH10K_DFS_CERTIFIED))
|
||||
return;
|
||||
|
||||
ATH10K_DFS_STAT_INC(ar, pulses_total);
|
||||
|
||||
while (i < buf_len) {
|
||||
if (i + sizeof(*tlv) > buf_len) {
|
||||
ath10k_warn("too short buf for tlv header (%d)\n", i);
|
||||
return;
|
||||
}
|
||||
|
||||
tlv = (struct phyerr_tlv *)&event->bufp[i];
|
||||
tlv_len = __le16_to_cpu(tlv->len);
|
||||
tlv_buf = &event->bufp[i + sizeof(*tlv)];
|
||||
ath10k_dbg(ATH10K_DBG_REGULATORY,
|
||||
"wmi event dfs tlv_len %d tlv_tag 0x%02X tlv_sig 0x%02X\n",
|
||||
tlv_len, tlv->tag, tlv->sig);
|
||||
|
||||
switch (tlv->tag) {
|
||||
case PHYERR_TLV_TAG_RADAR_PULSE_SUMMARY:
|
||||
if (i + sizeof(*tlv) + sizeof(*rr) > buf_len) {
|
||||
ath10k_warn("too short radar pulse summary (%d)\n",
|
||||
i);
|
||||
return;
|
||||
}
|
||||
|
||||
rr = (struct phyerr_radar_report *)tlv_buf;
|
||||
ath10k_dfs_radar_report(ar, event, rr, tsf);
|
||||
break;
|
||||
case PHYERR_TLV_TAG_SEARCH_FFT_REPORT:
|
||||
if (i + sizeof(*tlv) + sizeof(*fftr) > buf_len) {
|
||||
ath10k_warn("too short fft report (%d)\n", i);
|
||||
return;
|
||||
}
|
||||
|
||||
fftr = (struct phyerr_fft_report *)tlv_buf;
|
||||
res = ath10k_dfs_fft_report(ar, event, fftr, tsf);
|
||||
if (res)
|
||||
return;
|
||||
break;
|
||||
}
|
||||
|
||||
i += sizeof(*tlv) + tlv_len;
|
||||
}
|
||||
}
|
||||
|
||||
static void ath10k_wmi_event_spectral_scan(struct ath10k *ar,
|
||||
struct wmi_single_phyerr_rx_event *event,
|
||||
u64 tsf)
|
||||
{
|
||||
ath10k_dbg(ATH10K_DBG_WMI, "wmi event spectral scan\n");
|
||||
}
|
||||
|
||||
static void ath10k_wmi_event_phyerr(struct ath10k *ar, struct sk_buff *skb)
|
||||
{
|
||||
ath10k_dbg(ATH10K_DBG_WMI, "WMI_PHYERR_EVENTID\n");
|
||||
struct wmi_comb_phyerr_rx_event *comb_event;
|
||||
struct wmi_single_phyerr_rx_event *event;
|
||||
u32 count, i, buf_len, phy_err_code;
|
||||
u64 tsf;
|
||||
int left_len = skb->len;
|
||||
|
||||
ATH10K_DFS_STAT_INC(ar, phy_errors);
|
||||
|
||||
/* Check if combined event available */
|
||||
if (left_len < sizeof(*comb_event)) {
|
||||
ath10k_warn("wmi phyerr combined event wrong len\n");
|
||||
return;
|
||||
}
|
||||
|
||||
left_len -= sizeof(*comb_event);
|
||||
|
||||
/* Check number of included events */
|
||||
comb_event = (struct wmi_comb_phyerr_rx_event *)skb->data;
|
||||
count = __le32_to_cpu(comb_event->hdr.num_phyerr_events);
|
||||
|
||||
tsf = __le32_to_cpu(comb_event->hdr.tsf_u32);
|
||||
tsf <<= 32;
|
||||
tsf |= __le32_to_cpu(comb_event->hdr.tsf_l32);
|
||||
|
||||
ath10k_dbg(ATH10K_DBG_WMI,
|
||||
"wmi event phyerr count %d tsf64 0x%llX\n",
|
||||
count, tsf);
|
||||
|
||||
event = (struct wmi_single_phyerr_rx_event *)comb_event->bufp;
|
||||
for (i = 0; i < count; i++) {
|
||||
/* Check if we can read event header */
|
||||
if (left_len < sizeof(*event)) {
|
||||
ath10k_warn("single event (%d) wrong head len\n", i);
|
||||
return;
|
||||
}
|
||||
|
||||
left_len -= sizeof(*event);
|
||||
|
||||
buf_len = __le32_to_cpu(event->hdr.buf_len);
|
||||
phy_err_code = event->hdr.phy_err_code;
|
||||
|
||||
if (left_len < buf_len) {
|
||||
ath10k_warn("single event (%d) wrong buf len\n", i);
|
||||
return;
|
||||
}
|
||||
|
||||
left_len -= buf_len;
|
||||
|
||||
switch (phy_err_code) {
|
||||
case PHY_ERROR_RADAR:
|
||||
ath10k_wmi_event_dfs(ar, event, tsf);
|
||||
break;
|
||||
case PHY_ERROR_SPECTRAL_SCAN:
|
||||
ath10k_wmi_event_spectral_scan(ar, event, tsf);
|
||||
break;
|
||||
case PHY_ERROR_FALSE_RADAR_EXT:
|
||||
ath10k_wmi_event_dfs(ar, event, tsf);
|
||||
ath10k_wmi_event_spectral_scan(ar, event, tsf);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
event += sizeof(*event) + buf_len;
|
||||
}
|
||||
}
|
||||
|
||||
static void ath10k_wmi_event_roam(struct ath10k *ar, struct sk_buff *skb)
|
||||
|
@ -2062,6 +2315,7 @@ int ath10k_wmi_pdev_set_channel(struct ath10k *ar,
|
|||
{
|
||||
struct wmi_set_channel_cmd *cmd;
|
||||
struct sk_buff *skb;
|
||||
u32 ch_flags = 0;
|
||||
|
||||
if (arg->passive)
|
||||
return -EINVAL;
|
||||
|
@ -2070,10 +2324,14 @@ int ath10k_wmi_pdev_set_channel(struct ath10k *ar,
|
|||
if (!skb)
|
||||
return -ENOMEM;
|
||||
|
||||
if (arg->chan_radar)
|
||||
ch_flags |= WMI_CHAN_FLAG_DFS;
|
||||
|
||||
cmd = (struct wmi_set_channel_cmd *)skb->data;
|
||||
cmd->chan.mhz = __cpu_to_le32(arg->freq);
|
||||
cmd->chan.band_center_freq1 = __cpu_to_le32(arg->freq);
|
||||
cmd->chan.mode = arg->mode;
|
||||
cmd->chan.flags |= __cpu_to_le32(ch_flags);
|
||||
cmd->chan.min_power = arg->min_power;
|
||||
cmd->chan.max_power = arg->max_power;
|
||||
cmd->chan.reg_power = arg->max_reg_power;
|
||||
|
@ -2211,7 +2469,7 @@ static int ath10k_wmi_main_cmd_init(struct ath10k *ar)
|
|||
}
|
||||
|
||||
ath10k_dbg(ATH10K_DBG_WMI, "wmi sending %d memory chunks info.\n",
|
||||
__cpu_to_le32(ar->wmi.num_mem_chunks));
|
||||
ar->wmi.num_mem_chunks);
|
||||
|
||||
cmd->num_host_mem_chunks = __cpu_to_le32(ar->wmi.num_mem_chunks);
|
||||
|
||||
|
@ -2224,10 +2482,10 @@ static int ath10k_wmi_main_cmd_init(struct ath10k *ar)
|
|||
__cpu_to_le32(ar->wmi.mem_chunks[i].req_id);
|
||||
|
||||
ath10k_dbg(ATH10K_DBG_WMI,
|
||||
"wmi chunk %d len %d requested, addr 0x%x\n",
|
||||
"wmi chunk %d len %d requested, addr 0x%llx\n",
|
||||
i,
|
||||
cmd->host_mem_chunks[i].size,
|
||||
cmd->host_mem_chunks[i].ptr);
|
||||
ar->wmi.mem_chunks[i].len,
|
||||
(unsigned long long)ar->wmi.mem_chunks[i].paddr);
|
||||
}
|
||||
out:
|
||||
memcpy(&cmd->resource_config, &config, sizeof(config));
|
||||
|
@ -2302,7 +2560,7 @@ static int ath10k_wmi_10x_cmd_init(struct ath10k *ar)
|
|||
}
|
||||
|
||||
ath10k_dbg(ATH10K_DBG_WMI, "wmi sending %d memory chunks info.\n",
|
||||
__cpu_to_le32(ar->wmi.num_mem_chunks));
|
||||
ar->wmi.num_mem_chunks);
|
||||
|
||||
cmd->num_host_mem_chunks = __cpu_to_le32(ar->wmi.num_mem_chunks);
|
||||
|
||||
|
@ -2315,10 +2573,10 @@ static int ath10k_wmi_10x_cmd_init(struct ath10k *ar)
|
|||
__cpu_to_le32(ar->wmi.mem_chunks[i].req_id);
|
||||
|
||||
ath10k_dbg(ATH10K_DBG_WMI,
|
||||
"wmi chunk %d len %d requested, addr 0x%x\n",
|
||||
"wmi chunk %d len %d requested, addr 0x%llx\n",
|
||||
i,
|
||||
cmd->host_mem_chunks[i].size,
|
||||
cmd->host_mem_chunks[i].ptr);
|
||||
ar->wmi.mem_chunks[i].len,
|
||||
(unsigned long long)ar->wmi.mem_chunks[i].paddr);
|
||||
}
|
||||
out:
|
||||
memcpy(&cmd->resource_config, &config, sizeof(config));
|
||||
|
@ -2622,6 +2880,7 @@ static int ath10k_wmi_vdev_start_restart(struct ath10k *ar,
|
|||
struct sk_buff *skb;
|
||||
const char *cmdname;
|
||||
u32 flags = 0;
|
||||
u32 ch_flags = 0;
|
||||
|
||||
if (cmd_id != ar->wmi.cmd->vdev_start_request_cmdid &&
|
||||
cmd_id != ar->wmi.cmd->vdev_restart_request_cmdid)
|
||||
|
@ -2648,6 +2907,8 @@ static int ath10k_wmi_vdev_start_restart(struct ath10k *ar,
|
|||
flags |= WMI_VDEV_START_HIDDEN_SSID;
|
||||
if (arg->pmf_enabled)
|
||||
flags |= WMI_VDEV_START_PMF_ENABLED;
|
||||
if (arg->channel.chan_radar)
|
||||
ch_flags |= WMI_CHAN_FLAG_DFS;
|
||||
|
||||
cmd = (struct wmi_vdev_start_request_cmd *)skb->data;
|
||||
cmd->vdev_id = __cpu_to_le32(arg->vdev_id);
|
||||
|
@ -2669,6 +2930,7 @@ static int ath10k_wmi_vdev_start_restart(struct ath10k *ar,
|
|||
__cpu_to_le32(arg->channel.band_center_freq1);
|
||||
|
||||
cmd->chan.mode = arg->channel.mode;
|
||||
cmd->chan.flags |= __cpu_to_le32(ch_flags);
|
||||
cmd->chan.min_power = arg->channel.min_power;
|
||||
cmd->chan.max_power = arg->channel.max_power;
|
||||
cmd->chan.reg_power = arg->channel.max_reg_power;
|
||||
|
@ -2676,9 +2938,10 @@ static int ath10k_wmi_vdev_start_restart(struct ath10k *ar,
|
|||
cmd->chan.antenna_max = arg->channel.max_antenna_gain;
|
||||
|
||||
ath10k_dbg(ATH10K_DBG_WMI,
|
||||
"wmi vdev %s id 0x%x freq %d, mode %d, ch_flags: 0x%0X,"
|
||||
"max_power: %d\n", cmdname, arg->vdev_id, arg->channel.freq,
|
||||
arg->channel.mode, flags, arg->channel.max_power);
|
||||
"wmi vdev %s id 0x%x flags: 0x%0X, freq %d, mode %d, "
|
||||
"ch_flags: 0x%0X, max_power: %d\n", cmdname, arg->vdev_id,
|
||||
flags, arg->channel.freq, arg->channel.mode,
|
||||
cmd->chan.flags, arg->channel.max_power);
|
||||
|
||||
return ath10k_wmi_cmd_send(ar, skb, cmd_id);
|
||||
}
|
||||
|
@ -3012,6 +3275,8 @@ int ath10k_wmi_scan_chan_list(struct ath10k *ar,
|
|||
flags |= WMI_CHAN_FLAG_ALLOW_VHT;
|
||||
if (ch->ht40plus)
|
||||
flags |= WMI_CHAN_FLAG_HT40_PLUS;
|
||||
if (ch->chan_radar)
|
||||
flags |= WMI_CHAN_FLAG_DFS;
|
||||
|
||||
ci->mhz = __cpu_to_le32(ch->freq);
|
||||
ci->band_center_freq1 = __cpu_to_le32(ch->freq);
|
||||
|
@ -3094,6 +3359,7 @@ int ath10k_wmi_beacon_send_nowait(struct ath10k *ar,
|
|||
{
|
||||
struct wmi_bcn_tx_cmd *cmd;
|
||||
struct sk_buff *skb;
|
||||
int ret;
|
||||
|
||||
skb = ath10k_wmi_alloc_skb(sizeof(*cmd) + arg->bcn_len);
|
||||
if (!skb)
|
||||
|
@ -3106,7 +3372,11 @@ int ath10k_wmi_beacon_send_nowait(struct ath10k *ar,
|
|||
cmd->hdr.bcn_len = __cpu_to_le32(arg->bcn_len);
|
||||
memcpy(cmd->bcn, arg->bcn, arg->bcn_len);
|
||||
|
||||
return ath10k_wmi_cmd_send_nowait(ar, skb, ar->wmi.cmd->bcn_tx_cmdid);
|
||||
ret = ath10k_wmi_cmd_send_nowait(ar, skb, ar->wmi.cmd->bcn_tx_cmdid);
|
||||
if (ret)
|
||||
dev_kfree_skb(skb);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void ath10k_wmi_pdev_set_wmm_param(struct wmi_wmm_params *params,
|
||||
|
|
|
@ -893,6 +893,7 @@ struct wmi_channel {
|
|||
union {
|
||||
__le32 reginfo0;
|
||||
struct {
|
||||
/* note: power unit is 0.5 dBm */
|
||||
u8 min_power;
|
||||
u8 max_power;
|
||||
u8 reg_power;
|
||||
|
@ -915,7 +916,8 @@ struct wmi_channel_arg {
|
|||
bool allow_ht;
|
||||
bool allow_vht;
|
||||
bool ht40plus;
|
||||
/* note: power unit is 1/4th of dBm */
|
||||
bool chan_radar;
|
||||
/* note: power unit is 0.5 dBm */
|
||||
u32 min_power;
|
||||
u32 max_power;
|
||||
u32 max_reg_power;
|
||||
|
@ -1977,6 +1979,10 @@ struct wmi_mgmt_rx_event_v2 {
|
|||
#define WMI_RX_STATUS_ERR_MIC 0x10
|
||||
#define WMI_RX_STATUS_ERR_KEY_CACHE_MISS 0x20
|
||||
|
||||
#define PHY_ERROR_SPECTRAL_SCAN 0x26
|
||||
#define PHY_ERROR_FALSE_RADAR_EXT 0x24
|
||||
#define PHY_ERROR_RADAR 0x05
|
||||
|
||||
struct wmi_single_phyerr_rx_hdr {
|
||||
/* TSF timestamp */
|
||||
__le32 tsf_timestamp;
|
||||
|
@ -2068,6 +2074,87 @@ struct wmi_comb_phyerr_rx_event {
|
|||
u8 bufp[0];
|
||||
} __packed;
|
||||
|
||||
#define PHYERR_TLV_SIG 0xBB
|
||||
#define PHYERR_TLV_TAG_SEARCH_FFT_REPORT 0xFB
|
||||
#define PHYERR_TLV_TAG_RADAR_PULSE_SUMMARY 0xF8
|
||||
|
||||
struct phyerr_radar_report {
|
||||
__le32 reg0; /* RADAR_REPORT_REG0_* */
|
||||
__le32 reg1; /* REDAR_REPORT_REG1_* */
|
||||
} __packed;
|
||||
|
||||
#define RADAR_REPORT_REG0_PULSE_IS_CHIRP_MASK 0x80000000
|
||||
#define RADAR_REPORT_REG0_PULSE_IS_CHIRP_LSB 31
|
||||
|
||||
#define RADAR_REPORT_REG0_PULSE_IS_MAX_WIDTH_MASK 0x40000000
|
||||
#define RADAR_REPORT_REG0_PULSE_IS_MAX_WIDTH_LSB 30
|
||||
|
||||
#define RADAR_REPORT_REG0_AGC_TOTAL_GAIN_MASK 0x3FF00000
|
||||
#define RADAR_REPORT_REG0_AGC_TOTAL_GAIN_LSB 20
|
||||
|
||||
#define RADAR_REPORT_REG0_PULSE_DELTA_DIFF_MASK 0x000F0000
|
||||
#define RADAR_REPORT_REG0_PULSE_DELTA_DIFF_LSB 16
|
||||
|
||||
#define RADAR_REPORT_REG0_PULSE_DELTA_PEAK_MASK 0x0000FC00
|
||||
#define RADAR_REPORT_REG0_PULSE_DELTA_PEAK_LSB 10
|
||||
|
||||
#define RADAR_REPORT_REG0_PULSE_SIDX_MASK 0x000003FF
|
||||
#define RADAR_REPORT_REG0_PULSE_SIDX_LSB 0
|
||||
|
||||
#define RADAR_REPORT_REG1_PULSE_SRCH_FFT_VALID_MASK 0x80000000
|
||||
#define RADAR_REPORT_REG1_PULSE_SRCH_FFT_VALID_LSB 31
|
||||
|
||||
#define RADAR_REPORT_REG1_PULSE_AGC_MB_GAIN_MASK 0x7F000000
|
||||
#define RADAR_REPORT_REG1_PULSE_AGC_MB_GAIN_LSB 24
|
||||
|
||||
#define RADAR_REPORT_REG1_PULSE_SUBCHAN_MASK_MASK 0x00FF0000
|
||||
#define RADAR_REPORT_REG1_PULSE_SUBCHAN_MASK_LSB 16
|
||||
|
||||
#define RADAR_REPORT_REG1_PULSE_TSF_OFFSET_MASK 0x0000FF00
|
||||
#define RADAR_REPORT_REG1_PULSE_TSF_OFFSET_LSB 8
|
||||
|
||||
#define RADAR_REPORT_REG1_PULSE_DUR_MASK 0x000000FF
|
||||
#define RADAR_REPORT_REG1_PULSE_DUR_LSB 0
|
||||
|
||||
struct phyerr_fft_report {
|
||||
__le32 reg0; /* SEARCH_FFT_REPORT_REG0_ * */
|
||||
__le32 reg1; /* SEARCH_FFT_REPORT_REG1_ * */
|
||||
} __packed;
|
||||
|
||||
#define SEARCH_FFT_REPORT_REG0_TOTAL_GAIN_DB_MASK 0xFF800000
|
||||
#define SEARCH_FFT_REPORT_REG0_TOTAL_GAIN_DB_LSB 23
|
||||
|
||||
#define SEARCH_FFT_REPORT_REG0_BASE_PWR_DB_MASK 0x007FC000
|
||||
#define SEARCH_FFT_REPORT_REG0_BASE_PWR_DB_LSB 14
|
||||
|
||||
#define SEARCH_FFT_REPORT_REG0_FFT_CHN_IDX_MASK 0x00003000
|
||||
#define SEARCH_FFT_REPORT_REG0_FFT_CHN_IDX_LSB 12
|
||||
|
||||
#define SEARCH_FFT_REPORT_REG0_PEAK_SIDX_MASK 0x00000FFF
|
||||
#define SEARCH_FFT_REPORT_REG0_PEAK_SIDX_LSB 0
|
||||
|
||||
#define SEARCH_FFT_REPORT_REG1_RELPWR_DB_MASK 0xFC000000
|
||||
#define SEARCH_FFT_REPORT_REG1_RELPWR_DB_LSB 26
|
||||
|
||||
#define SEARCH_FFT_REPORT_REG1_AVGPWR_DB_MASK 0x03FC0000
|
||||
#define SEARCH_FFT_REPORT_REG1_AVGPWR_DB_LSB 18
|
||||
|
||||
#define SEARCH_FFT_REPORT_REG1_PEAK_MAG_MASK 0x0003FF00
|
||||
#define SEARCH_FFT_REPORT_REG1_PEAK_MAG_LSB 8
|
||||
|
||||
#define SEARCH_FFT_REPORT_REG1_NUM_STR_BINS_IB_MASK 0x000000FF
|
||||
#define SEARCH_FFT_REPORT_REG1_NUM_STR_BINS_IB_LSB 0
|
||||
|
||||
|
||||
struct phyerr_tlv {
|
||||
__le16 len;
|
||||
u8 tag;
|
||||
u8 sig;
|
||||
} __packed;
|
||||
|
||||
#define DFS_RSSI_POSSIBLY_FALSE 50
|
||||
#define DFS_PEAK_MAG_THOLD_POSSIBLY_FALSE 40
|
||||
|
||||
struct wmi_mgmt_tx_hdr {
|
||||
__le32 vdev_id;
|
||||
struct wmi_mac_addr peer_macaddr;
|
||||
|
@ -2233,7 +2320,12 @@ enum wmi_pdev_param {
|
|||
* 0: no protection 1:use CTS-to-self 2: use RTS/CTS
|
||||
*/
|
||||
WMI_PDEV_PARAM_PROTECTION_MODE,
|
||||
/* Dynamic bandwidth 0: disable 1: enable */
|
||||
/*
|
||||
* Dynamic bandwidth - 0: disable, 1: enable
|
||||
*
|
||||
* When enabled HW rate control tries different bandwidths when
|
||||
* retransmitting frames.
|
||||
*/
|
||||
WMI_PDEV_PARAM_DYNAMIC_BW,
|
||||
/* Non aggregrate/ 11g sw retry threshold.0-disable */
|
||||
WMI_PDEV_PARAM_NON_AGG_SW_RETRY_TH,
|
||||
|
|
|
@ -616,7 +616,16 @@ ath5k_hw_get_isr(struct ath5k_hw *ah, enum ath5k_int *interrupt_mask)
|
|||
* SISRs will also clear PISR so no need to worry here.
|
||||
*/
|
||||
|
||||
pisr_clear = pisr & ~AR5K_ISR_BITS_FROM_SISRS;
|
||||
/* XXX: There seems to be an issue on some cards
|
||||
* with tx interrupt flags not being updated
|
||||
* on PISR despite that all Tx interrupt bits
|
||||
* are cleared on SISRs. Since we handle all
|
||||
* Tx queues all together it shouldn't be an
|
||||
* issue if we clear Tx interrupt flags also
|
||||
* on PISR to avoid that.
|
||||
*/
|
||||
pisr_clear = (pisr & ~AR5K_ISR_BITS_FROM_SISRS) |
|
||||
(pisr & AR5K_INT_TX_ALL);
|
||||
|
||||
/*
|
||||
* Write to clear them...
|
||||
|
|
|
@ -303,7 +303,7 @@ static const u32 ar9300_2p2_mac_postamble[][5] = {
|
|||
{0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38},
|
||||
{0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00},
|
||||
{0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b},
|
||||
{0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810},
|
||||
{0x00008120, 0x18f04800, 0x18f04800, 0x18f04810, 0x18f04810},
|
||||
{0x000081d0, 0x00003210, 0x00003210, 0x0000320a, 0x0000320a},
|
||||
{0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440},
|
||||
};
|
||||
|
@ -534,107 +534,107 @@ static const u32 ar9300_2p2_baseband_core[][2] = {
|
|||
|
||||
static const u32 ar9300Modes_high_power_tx_gain_table_2p2[][5] = {
|
||||
/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
|
||||
{0x0000a2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352},
|
||||
{0x0000a2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584},
|
||||
{0x0000a2e4, 0x03ff0000, 0x03ff0000, 0x03f0f800, 0x03f0f800},
|
||||
{0x0000a2dc, 0x000cfff0, 0x000cfff0, 0x03aaa352, 0x03aaa352},
|
||||
{0x0000a2e0, 0x000f0000, 0x000f0000, 0x03ccc584, 0x03ccc584},
|
||||
{0x0000a2e4, 0x03f00000, 0x03f00000, 0x03f0f800, 0x03f0f800},
|
||||
{0x0000a2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
|
||||
{0x0000a410, 0x000050d8, 0x000050d8, 0x000050d9, 0x000050d9},
|
||||
{0x0000a500, 0x00002220, 0x00002220, 0x00000000, 0x00000000},
|
||||
{0x0000a504, 0x04002222, 0x04002222, 0x04000002, 0x04000002},
|
||||
{0x0000a508, 0x09002421, 0x09002421, 0x08000004, 0x08000004},
|
||||
{0x0000a50c, 0x0d002621, 0x0d002621, 0x0b000200, 0x0b000200},
|
||||
{0x0000a510, 0x13004620, 0x13004620, 0x0f000202, 0x0f000202},
|
||||
{0x0000a514, 0x19004a20, 0x19004a20, 0x11000400, 0x11000400},
|
||||
{0x0000a518, 0x1d004e20, 0x1d004e20, 0x15000402, 0x15000402},
|
||||
{0x0000a51c, 0x21005420, 0x21005420, 0x19000404, 0x19000404},
|
||||
{0x0000a520, 0x26005e20, 0x26005e20, 0x1b000603, 0x1b000603},
|
||||
{0x0000a524, 0x2b005e40, 0x2b005e40, 0x1f000a02, 0x1f000a02},
|
||||
{0x0000a528, 0x2f005e42, 0x2f005e42, 0x23000a04, 0x23000a04},
|
||||
{0x0000a52c, 0x33005e44, 0x33005e44, 0x26000a20, 0x26000a20},
|
||||
{0x0000a530, 0x38005e65, 0x38005e65, 0x2a000e20, 0x2a000e20},
|
||||
{0x0000a534, 0x3c005e69, 0x3c005e69, 0x2e000e22, 0x2e000e22},
|
||||
{0x0000a538, 0x40005e6b, 0x40005e6b, 0x31000e24, 0x31000e24},
|
||||
{0x0000a53c, 0x44005e6d, 0x44005e6d, 0x34001640, 0x34001640},
|
||||
{0x0000a540, 0x49005e72, 0x49005e72, 0x38001660, 0x38001660},
|
||||
{0x0000a544, 0x4e005eb2, 0x4e005eb2, 0x3b001861, 0x3b001861},
|
||||
{0x0000a548, 0x53005f12, 0x53005f12, 0x3e001a81, 0x3e001a81},
|
||||
{0x0000a54c, 0x59025eb2, 0x59025eb2, 0x42001a83, 0x42001a83},
|
||||
{0x0000a550, 0x5e025f12, 0x5e025f12, 0x44001c84, 0x44001c84},
|
||||
{0x0000a554, 0x61027f12, 0x61027f12, 0x48001ce3, 0x48001ce3},
|
||||
{0x0000a558, 0x6702bf12, 0x6702bf12, 0x4c001ce5, 0x4c001ce5},
|
||||
{0x0000a55c, 0x6b02bf14, 0x6b02bf14, 0x50001ce9, 0x50001ce9},
|
||||
{0x0000a560, 0x6f02bf16, 0x6f02bf16, 0x54001ceb, 0x54001ceb},
|
||||
{0x0000a564, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
|
||||
{0x0000a568, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
|
||||
{0x0000a56c, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
|
||||
{0x0000a570, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
|
||||
{0x0000a574, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
|
||||
{0x0000a578, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
|
||||
{0x0000a57c, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
|
||||
{0x0000a580, 0x00802220, 0x00802220, 0x00800000, 0x00800000},
|
||||
{0x0000a584, 0x04802222, 0x04802222, 0x04800002, 0x04800002},
|
||||
{0x0000a588, 0x09802421, 0x09802421, 0x08800004, 0x08800004},
|
||||
{0x0000a58c, 0x0d802621, 0x0d802621, 0x0b800200, 0x0b800200},
|
||||
{0x0000a590, 0x13804620, 0x13804620, 0x0f800202, 0x0f800202},
|
||||
{0x0000a594, 0x19804a20, 0x19804a20, 0x11800400, 0x11800400},
|
||||
{0x0000a598, 0x1d804e20, 0x1d804e20, 0x15800402, 0x15800402},
|
||||
{0x0000a59c, 0x21805420, 0x21805420, 0x19800404, 0x19800404},
|
||||
{0x0000a5a0, 0x26805e20, 0x26805e20, 0x1b800603, 0x1b800603},
|
||||
{0x0000a5a4, 0x2b805e40, 0x2b805e40, 0x1f800a02, 0x1f800a02},
|
||||
{0x0000a5a8, 0x2f805e42, 0x2f805e42, 0x23800a04, 0x23800a04},
|
||||
{0x0000a5ac, 0x33805e44, 0x33805e44, 0x26800a20, 0x26800a20},
|
||||
{0x0000a5b0, 0x38805e65, 0x38805e65, 0x2a800e20, 0x2a800e20},
|
||||
{0x0000a5b4, 0x3c805e69, 0x3c805e69, 0x2e800e22, 0x2e800e22},
|
||||
{0x0000a5b8, 0x40805e6b, 0x40805e6b, 0x31800e24, 0x31800e24},
|
||||
{0x0000a5bc, 0x44805e6d, 0x44805e6d, 0x34801640, 0x34801640},
|
||||
{0x0000a5c0, 0x49805e72, 0x49805e72, 0x38801660, 0x38801660},
|
||||
{0x0000a5c4, 0x4e805eb2, 0x4e805eb2, 0x3b801861, 0x3b801861},
|
||||
{0x0000a5c8, 0x53805f12, 0x53805f12, 0x3e801a81, 0x3e801a81},
|
||||
{0x0000a5cc, 0x59825eb2, 0x59825eb2, 0x42801a83, 0x42801a83},
|
||||
{0x0000a5d0, 0x5e825f12, 0x5e825f12, 0x44801c84, 0x44801c84},
|
||||
{0x0000a5d4, 0x61827f12, 0x61827f12, 0x48801ce3, 0x48801ce3},
|
||||
{0x0000a5d8, 0x6782bf12, 0x6782bf12, 0x4c801ce5, 0x4c801ce5},
|
||||
{0x0000a5dc, 0x6b82bf14, 0x6b82bf14, 0x50801ce9, 0x50801ce9},
|
||||
{0x0000a5e0, 0x6f82bf16, 0x6f82bf16, 0x54801ceb, 0x54801ceb},
|
||||
{0x0000a5e4, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
|
||||
{0x0000a5e8, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
|
||||
{0x0000a5ec, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
|
||||
{0x0000a5f0, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
|
||||
{0x0000a5f4, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
|
||||
{0x0000a5f8, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
|
||||
{0x0000a5fc, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
|
||||
{0x0000a410, 0x000050d9, 0x000050d9, 0x000050d9, 0x000050d9},
|
||||
{0x0000a500, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
|
||||
{0x0000a504, 0x06000003, 0x06000003, 0x04000002, 0x04000002},
|
||||
{0x0000a508, 0x0a000020, 0x0a000020, 0x08000004, 0x08000004},
|
||||
{0x0000a50c, 0x10000023, 0x10000023, 0x0b000200, 0x0b000200},
|
||||
{0x0000a510, 0x15000028, 0x15000028, 0x0f000202, 0x0f000202},
|
||||
{0x0000a514, 0x1b00002b, 0x1b00002b, 0x12000400, 0x12000400},
|
||||
{0x0000a518, 0x1f020028, 0x1f020028, 0x16000402, 0x16000402},
|
||||
{0x0000a51c, 0x2502002b, 0x2502002b, 0x19000404, 0x19000404},
|
||||
{0x0000a520, 0x2a04002a, 0x2a04002a, 0x1c000603, 0x1c000603},
|
||||
{0x0000a524, 0x2e06002a, 0x2e06002a, 0x21000a02, 0x21000a02},
|
||||
{0x0000a528, 0x3302202d, 0x3302202d, 0x25000a04, 0x25000a04},
|
||||
{0x0000a52c, 0x3804202c, 0x3804202c, 0x28000a20, 0x28000a20},
|
||||
{0x0000a530, 0x3c06202c, 0x3c06202c, 0x2c000e20, 0x2c000e20},
|
||||
{0x0000a534, 0x4108202d, 0x4108202d, 0x30000e22, 0x30000e22},
|
||||
{0x0000a538, 0x4506402d, 0x4506402d, 0x34000e24, 0x34000e24},
|
||||
{0x0000a53c, 0x4906222d, 0x4906222d, 0x38001640, 0x38001640},
|
||||
{0x0000a540, 0x4d062231, 0x4d062231, 0x3c001660, 0x3c001660},
|
||||
{0x0000a544, 0x50082231, 0x50082231, 0x3f001861, 0x3f001861},
|
||||
{0x0000a548, 0x5608422e, 0x5608422e, 0x43001a81, 0x43001a81},
|
||||
{0x0000a54c, 0x5e08442e, 0x5e08442e, 0x47001a83, 0x47001a83},
|
||||
{0x0000a550, 0x620a4431, 0x620a4431, 0x4a001c84, 0x4a001c84},
|
||||
{0x0000a554, 0x640a4432, 0x640a4432, 0x4e001ce3, 0x4e001ce3},
|
||||
{0x0000a558, 0x680a4434, 0x680a4434, 0x52001ce5, 0x52001ce5},
|
||||
{0x0000a55c, 0x6c0a6434, 0x6c0a6434, 0x56001ce9, 0x56001ce9},
|
||||
{0x0000a560, 0x6f0a6633, 0x6f0a6633, 0x5a001ceb, 0x5a001ceb},
|
||||
{0x0000a564, 0x730c6634, 0x730c6634, 0x5d001eec, 0x5d001eec},
|
||||
{0x0000a568, 0x730c6634, 0x730c6634, 0x5d001eec, 0x5d001eec},
|
||||
{0x0000a56c, 0x730c6634, 0x730c6634, 0x5d001eec, 0x5d001eec},
|
||||
{0x0000a570, 0x730c6634, 0x730c6634, 0x5d001eec, 0x5d001eec},
|
||||
{0x0000a574, 0x730c6634, 0x730c6634, 0x5d001eec, 0x5d001eec},
|
||||
{0x0000a578, 0x730c6634, 0x730c6634, 0x5d001eec, 0x5d001eec},
|
||||
{0x0000a57c, 0x730c6634, 0x730c6634, 0x5d001eec, 0x5d001eec},
|
||||
{0x0000a580, 0x00800000, 0x00800000, 0x00800000, 0x00800000},
|
||||
{0x0000a584, 0x06800003, 0x06800003, 0x04800002, 0x04800002},
|
||||
{0x0000a588, 0x0a800020, 0x0a800020, 0x08800004, 0x08800004},
|
||||
{0x0000a58c, 0x10800023, 0x10800023, 0x0b800200, 0x0b800200},
|
||||
{0x0000a590, 0x15800028, 0x15800028, 0x0f800202, 0x0f800202},
|
||||
{0x0000a594, 0x1b80002b, 0x1b80002b, 0x12800400, 0x12800400},
|
||||
{0x0000a598, 0x1f820028, 0x1f820028, 0x16800402, 0x16800402},
|
||||
{0x0000a59c, 0x2582002b, 0x2582002b, 0x19800404, 0x19800404},
|
||||
{0x0000a5a0, 0x2a84002a, 0x2a84002a, 0x1c800603, 0x1c800603},
|
||||
{0x0000a5a4, 0x2e86002a, 0x2e86002a, 0x21800a02, 0x21800a02},
|
||||
{0x0000a5a8, 0x3382202d, 0x3382202d, 0x25800a04, 0x25800a04},
|
||||
{0x0000a5ac, 0x3884202c, 0x3884202c, 0x28800a20, 0x28800a20},
|
||||
{0x0000a5b0, 0x3c86202c, 0x3c86202c, 0x2c800e20, 0x2c800e20},
|
||||
{0x0000a5b4, 0x4188202d, 0x4188202d, 0x30800e22, 0x30800e22},
|
||||
{0x0000a5b8, 0x4586402d, 0x4586402d, 0x34800e24, 0x34800e24},
|
||||
{0x0000a5bc, 0x4986222d, 0x4986222d, 0x38801640, 0x38801640},
|
||||
{0x0000a5c0, 0x4d862231, 0x4d862231, 0x3c801660, 0x3c801660},
|
||||
{0x0000a5c4, 0x50882231, 0x50882231, 0x3f801861, 0x3f801861},
|
||||
{0x0000a5c8, 0x5688422e, 0x5688422e, 0x43801a81, 0x43801a81},
|
||||
{0x0000a5cc, 0x5e88442e, 0x5e88442e, 0x47801a83, 0x47801a83},
|
||||
{0x0000a5d0, 0x628a4431, 0x628a4431, 0x4a801c84, 0x4a801c84},
|
||||
{0x0000a5d4, 0x648a4432, 0x648a4432, 0x4e801ce3, 0x4e801ce3},
|
||||
{0x0000a5d8, 0x688a4434, 0x688a4434, 0x52801ce5, 0x52801ce5},
|
||||
{0x0000a5dc, 0x6c8a6434, 0x6c8a6434, 0x56801ce9, 0x56801ce9},
|
||||
{0x0000a5e0, 0x6f8a6633, 0x6f8a6633, 0x5a801ceb, 0x5a801ceb},
|
||||
{0x0000a5e4, 0x738c6634, 0x738c6634, 0x5d801eec, 0x5d801eec},
|
||||
{0x0000a5e8, 0x738c6634, 0x738c6634, 0x5d801eec, 0x5d801eec},
|
||||
{0x0000a5ec, 0x738c6634, 0x738c6634, 0x5d801eec, 0x5d801eec},
|
||||
{0x0000a5f0, 0x738c6634, 0x738c6634, 0x5d801eec, 0x5d801eec},
|
||||
{0x0000a5f4, 0x738c6634, 0x738c6634, 0x5d801eec, 0x5d801eec},
|
||||
{0x0000a5f8, 0x738c6634, 0x738c6634, 0x5d801eec, 0x5d801eec},
|
||||
{0x0000a5fc, 0x738c6634, 0x738c6634, 0x5d801eec, 0x5d801eec},
|
||||
{0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
|
||||
{0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
|
||||
{0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
|
||||
{0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
|
||||
{0x0000a610, 0x00804000, 0x00804000, 0x00000000, 0x00000000},
|
||||
{0x0000a614, 0x00804201, 0x00804201, 0x01404000, 0x01404000},
|
||||
{0x0000a618, 0x0280c802, 0x0280c802, 0x01404501, 0x01404501},
|
||||
{0x0000a61c, 0x0280ca03, 0x0280ca03, 0x02008501, 0x02008501},
|
||||
{0x0000a620, 0x04c15104, 0x04c15104, 0x0280ca03, 0x0280ca03},
|
||||
{0x0000a624, 0x04c15305, 0x04c15305, 0x03010c04, 0x03010c04},
|
||||
{0x0000a628, 0x04c15305, 0x04c15305, 0x04014c04, 0x04014c04},
|
||||
{0x0000a62c, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
|
||||
{0x0000a630, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
|
||||
{0x0000a634, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
|
||||
{0x0000a638, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
|
||||
{0x0000a63c, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
|
||||
{0x0000b2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352},
|
||||
{0x0000b2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584},
|
||||
{0x0000b2e4, 0x03ff0000, 0x03ff0000, 0x03f0f800, 0x03f0f800},
|
||||
{0x0000a608, 0x01804601, 0x01804601, 0x00000000, 0x00000000},
|
||||
{0x0000a60c, 0x01804601, 0x01804601, 0x00000000, 0x00000000},
|
||||
{0x0000a610, 0x01804601, 0x01804601, 0x00000000, 0x00000000},
|
||||
{0x0000a614, 0x01804601, 0x01804601, 0x01404000, 0x01404000},
|
||||
{0x0000a618, 0x01804601, 0x01804601, 0x01404501, 0x01404501},
|
||||
{0x0000a61c, 0x01804601, 0x01804601, 0x02008501, 0x02008501},
|
||||
{0x0000a620, 0x03408d02, 0x03408d02, 0x0280ca03, 0x0280ca03},
|
||||
{0x0000a624, 0x0300cc03, 0x0300cc03, 0x03010c04, 0x03010c04},
|
||||
{0x0000a628, 0x03410d04, 0x03410d04, 0x04014c04, 0x04014c04},
|
||||
{0x0000a62c, 0x03410d04, 0x03410d04, 0x04015005, 0x04015005},
|
||||
{0x0000a630, 0x03410d04, 0x03410d04, 0x04015005, 0x04015005},
|
||||
{0x0000a634, 0x03410d04, 0x03410d04, 0x04015005, 0x04015005},
|
||||
{0x0000a638, 0x03410d04, 0x03410d04, 0x04015005, 0x04015005},
|
||||
{0x0000a63c, 0x03410d04, 0x03410d04, 0x04015005, 0x04015005},
|
||||
{0x0000b2dc, 0x000cfff0, 0x000cfff0, 0x03aaa352, 0x03aaa352},
|
||||
{0x0000b2e0, 0x000f0000, 0x000f0000, 0x03ccc584, 0x03ccc584},
|
||||
{0x0000b2e4, 0x03f00000, 0x03f00000, 0x03f0f800, 0x03f0f800},
|
||||
{0x0000b2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
|
||||
{0x0000c2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352},
|
||||
{0x0000c2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584},
|
||||
{0x0000c2e4, 0x03ff0000, 0x03ff0000, 0x03f0f800, 0x03f0f800},
|
||||
{0x0000c2dc, 0x000cfff0, 0x000cfff0, 0x03aaa352, 0x03aaa352},
|
||||
{0x0000c2e0, 0x000f0000, 0x000f0000, 0x03ccc584, 0x03ccc584},
|
||||
{0x0000c2e4, 0x03f00000, 0x03f00000, 0x03f0f800, 0x03f0f800},
|
||||
{0x0000c2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
|
||||
{0x00016044, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4},
|
||||
{0x00016048, 0x66480001, 0x66480001, 0x66480001, 0x66480001},
|
||||
{0x00016048, 0x61200001, 0x61200001, 0x66480001, 0x66480001},
|
||||
{0x00016068, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
|
||||
{0x00016444, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4},
|
||||
{0x00016448, 0x66480001, 0x66480001, 0x66480001, 0x66480001},
|
||||
{0x00016448, 0x61200001, 0x61200001, 0x66480001, 0x66480001},
|
||||
{0x00016468, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
|
||||
{0x00016844, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4},
|
||||
{0x00016848, 0x66480001, 0x66480001, 0x66480001, 0x66480001},
|
||||
{0x00016848, 0x61200001, 0x61200001, 0x66480001, 0x66480001},
|
||||
{0x00016868, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
|
||||
};
|
||||
|
||||
|
@ -1745,4 +1745,11 @@ static const u32 ar9300_2p2_baseband_core_txfir_coeff_japan_2484[][2] = {
|
|||
{0x0000a3a0, 0xca9228ee},
|
||||
};
|
||||
|
||||
static const u32 ar9300_2p2_baseband_postamble_dfs_channel[][3] = {
|
||||
/* Addr 5G 2G */
|
||||
{0x00009824, 0x5ac668d0, 0x5ac668d0},
|
||||
{0x00009e0c, 0x6d4000e2, 0x6d4000e2},
|
||||
{0x00009e14, 0x37b9625e, 0x37b9625e},
|
||||
};
|
||||
|
||||
#endif /* INITVALS_9003_2P2_H */
|
||||
|
|
126
drivers/net/wireless/ath/ath9k/ar9003_buffalo_initvals.h
Normal file
126
drivers/net/wireless/ath/ath9k/ar9003_buffalo_initvals.h
Normal file
|
@ -0,0 +1,126 @@
|
|||
/*
|
||||
* Copyright (c) 2013 Qualcomm Atheros Inc.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef INITVALS_9003_BUFFALO_H
|
||||
#define INITVALS_9003_BUFFALO_H
|
||||
|
||||
static const u32 ar9300Modes_high_power_tx_gain_table_buffalo[][5] = {
|
||||
/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
|
||||
{0x0000a2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352},
|
||||
{0x0000a2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584},
|
||||
{0x0000a2e4, 0x03ff0000, 0x03ff0000, 0x03f0f800, 0x03f0f800},
|
||||
{0x0000a2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
|
||||
{0x0000a410, 0x000050d8, 0x000050d8, 0x000050d9, 0x000050d9},
|
||||
{0x0000a500, 0x00002220, 0x00002220, 0x00000000, 0x00000000},
|
||||
{0x0000a504, 0x04002222, 0x04002222, 0x04000002, 0x04000002},
|
||||
{0x0000a508, 0x09002421, 0x09002421, 0x08000004, 0x08000004},
|
||||
{0x0000a50c, 0x0d002621, 0x0d002621, 0x0b000200, 0x0b000200},
|
||||
{0x0000a510, 0x13004620, 0x13004620, 0x0f000202, 0x0f000202},
|
||||
{0x0000a514, 0x19004a20, 0x19004a20, 0x11000400, 0x11000400},
|
||||
{0x0000a518, 0x1d004e20, 0x1d004e20, 0x15000402, 0x15000402},
|
||||
{0x0000a51c, 0x21005420, 0x21005420, 0x19000404, 0x19000404},
|
||||
{0x0000a520, 0x26005e20, 0x26005e20, 0x1b000603, 0x1b000603},
|
||||
{0x0000a524, 0x2b005e40, 0x2b005e40, 0x1f000a02, 0x1f000a02},
|
||||
{0x0000a528, 0x2f005e42, 0x2f005e42, 0x23000a04, 0x23000a04},
|
||||
{0x0000a52c, 0x33005e44, 0x33005e44, 0x26000a20, 0x26000a20},
|
||||
{0x0000a530, 0x38005e65, 0x38005e65, 0x2a000e20, 0x2a000e20},
|
||||
{0x0000a534, 0x3c005e69, 0x3c005e69, 0x2e000e22, 0x2e000e22},
|
||||
{0x0000a538, 0x40005e6b, 0x40005e6b, 0x31000e24, 0x31000e24},
|
||||
{0x0000a53c, 0x44005e6d, 0x44005e6d, 0x34001640, 0x34001640},
|
||||
{0x0000a540, 0x49005e72, 0x49005e72, 0x38001660, 0x38001660},
|
||||
{0x0000a544, 0x4e005eb2, 0x4e005eb2, 0x3b001861, 0x3b001861},
|
||||
{0x0000a548, 0x53005f12, 0x53005f12, 0x3e001a81, 0x3e001a81},
|
||||
{0x0000a54c, 0x59025eb2, 0x59025eb2, 0x42001a83, 0x42001a83},
|
||||
{0x0000a550, 0x5e025f12, 0x5e025f12, 0x44001c84, 0x44001c84},
|
||||
{0x0000a554, 0x61027f12, 0x61027f12, 0x48001ce3, 0x48001ce3},
|
||||
{0x0000a558, 0x6702bf12, 0x6702bf12, 0x4c001ce5, 0x4c001ce5},
|
||||
{0x0000a55c, 0x6b02bf14, 0x6b02bf14, 0x50001ce9, 0x50001ce9},
|
||||
{0x0000a560, 0x6f02bf16, 0x6f02bf16, 0x54001ceb, 0x54001ceb},
|
||||
{0x0000a564, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
|
||||
{0x0000a568, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
|
||||
{0x0000a56c, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
|
||||
{0x0000a570, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
|
||||
{0x0000a574, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
|
||||
{0x0000a578, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
|
||||
{0x0000a57c, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
|
||||
{0x0000a580, 0x00802220, 0x00802220, 0x00800000, 0x00800000},
|
||||
{0x0000a584, 0x04802222, 0x04802222, 0x04800002, 0x04800002},
|
||||
{0x0000a588, 0x09802421, 0x09802421, 0x08800004, 0x08800004},
|
||||
{0x0000a58c, 0x0d802621, 0x0d802621, 0x0b800200, 0x0b800200},
|
||||
{0x0000a590, 0x13804620, 0x13804620, 0x0f800202, 0x0f800202},
|
||||
{0x0000a594, 0x19804a20, 0x19804a20, 0x11800400, 0x11800400},
|
||||
{0x0000a598, 0x1d804e20, 0x1d804e20, 0x15800402, 0x15800402},
|
||||
{0x0000a59c, 0x21805420, 0x21805420, 0x19800404, 0x19800404},
|
||||
{0x0000a5a0, 0x26805e20, 0x26805e20, 0x1b800603, 0x1b800603},
|
||||
{0x0000a5a4, 0x2b805e40, 0x2b805e40, 0x1f800a02, 0x1f800a02},
|
||||
{0x0000a5a8, 0x2f805e42, 0x2f805e42, 0x23800a04, 0x23800a04},
|
||||
{0x0000a5ac, 0x33805e44, 0x33805e44, 0x26800a20, 0x26800a20},
|
||||
{0x0000a5b0, 0x38805e65, 0x38805e65, 0x2a800e20, 0x2a800e20},
|
||||
{0x0000a5b4, 0x3c805e69, 0x3c805e69, 0x2e800e22, 0x2e800e22},
|
||||
{0x0000a5b8, 0x40805e6b, 0x40805e6b, 0x31800e24, 0x31800e24},
|
||||
{0x0000a5bc, 0x44805e6d, 0x44805e6d, 0x34801640, 0x34801640},
|
||||
{0x0000a5c0, 0x49805e72, 0x49805e72, 0x38801660, 0x38801660},
|
||||
{0x0000a5c4, 0x4e805eb2, 0x4e805eb2, 0x3b801861, 0x3b801861},
|
||||
{0x0000a5c8, 0x53805f12, 0x53805f12, 0x3e801a81, 0x3e801a81},
|
||||
{0x0000a5cc, 0x59825eb2, 0x59825eb2, 0x42801a83, 0x42801a83},
|
||||
{0x0000a5d0, 0x5e825f12, 0x5e825f12, 0x44801c84, 0x44801c84},
|
||||
{0x0000a5d4, 0x61827f12, 0x61827f12, 0x48801ce3, 0x48801ce3},
|
||||
{0x0000a5d8, 0x6782bf12, 0x6782bf12, 0x4c801ce5, 0x4c801ce5},
|
||||
{0x0000a5dc, 0x6b82bf14, 0x6b82bf14, 0x50801ce9, 0x50801ce9},
|
||||
{0x0000a5e0, 0x6f82bf16, 0x6f82bf16, 0x54801ceb, 0x54801ceb},
|
||||
{0x0000a5e4, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
|
||||
{0x0000a5e8, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
|
||||
{0x0000a5ec, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
|
||||
{0x0000a5f0, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
|
||||
{0x0000a5f4, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
|
||||
{0x0000a5f8, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
|
||||
{0x0000a5fc, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
|
||||
{0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
|
||||
{0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
|
||||
{0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
|
||||
{0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
|
||||
{0x0000a610, 0x00804000, 0x00804000, 0x00000000, 0x00000000},
|
||||
{0x0000a614, 0x00804201, 0x00804201, 0x01404000, 0x01404000},
|
||||
{0x0000a618, 0x0280c802, 0x0280c802, 0x01404501, 0x01404501},
|
||||
{0x0000a61c, 0x0280ca03, 0x0280ca03, 0x02008501, 0x02008501},
|
||||
{0x0000a620, 0x04c15104, 0x04c15104, 0x0280ca03, 0x0280ca03},
|
||||
{0x0000a624, 0x04c15305, 0x04c15305, 0x03010c04, 0x03010c04},
|
||||
{0x0000a628, 0x04c15305, 0x04c15305, 0x04014c04, 0x04014c04},
|
||||
{0x0000a62c, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
|
||||
{0x0000a630, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
|
||||
{0x0000a634, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
|
||||
{0x0000a638, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
|
||||
{0x0000a63c, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
|
||||
{0x0000b2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352},
|
||||
{0x0000b2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584},
|
||||
{0x0000b2e4, 0x03ff0000, 0x03ff0000, 0x03f0f800, 0x03f0f800},
|
||||
{0x0000b2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
|
||||
{0x0000c2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352},
|
||||
{0x0000c2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584},
|
||||
{0x0000c2e4, 0x03ff0000, 0x03ff0000, 0x03f0f800, 0x03f0f800},
|
||||
{0x0000c2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
|
||||
{0x00016044, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4},
|
||||
{0x00016048, 0x66480001, 0x66480001, 0x66480001, 0x66480001},
|
||||
{0x00016068, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
|
||||
{0x00016444, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4},
|
||||
{0x00016448, 0x66480001, 0x66480001, 0x66480001, 0x66480001},
|
||||
{0x00016468, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
|
||||
{0x00016844, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4},
|
||||
{0x00016848, 0x66480001, 0x66480001, 0x66480001, 0x66480001},
|
||||
{0x00016868, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
|
||||
};
|
||||
|
||||
#endif /* INITVALS_9003_BUFFALO_H */
|
|
@ -898,7 +898,7 @@ static void ar9003_hw_tx_iq_cal_reload(struct ath_hw *ah)
|
|||
|
||||
static void ar9003_hw_manual_peak_cal(struct ath_hw *ah, u8 chain, bool is_2g)
|
||||
{
|
||||
int offset[8], total = 0, test;
|
||||
int offset[8] = {0}, total = 0, test;
|
||||
int agc_out, i;
|
||||
|
||||
REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_GAINSTAGES(chain),
|
||||
|
@ -923,12 +923,18 @@ static void ar9003_hw_manual_peak_cal(struct ath_hw *ah, u8 chain, bool is_2g)
|
|||
AR_PHY_65NM_RXRF_AGC_AGC_ON_OVR, 0x1);
|
||||
REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_AGC(chain),
|
||||
AR_PHY_65NM_RXRF_AGC_AGC_CAL_OVR, 0x1);
|
||||
if (is_2g)
|
||||
|
||||
if (AR_SREV_9330_11(ah)) {
|
||||
REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_AGC(chain),
|
||||
AR_PHY_65NM_RXRF_AGC_AGC2G_DBDAC_OVR, 0x0);
|
||||
else
|
||||
REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_AGC(chain),
|
||||
AR_PHY_65NM_RXRF_AGC_AGC5G_DBDAC_OVR, 0x0);
|
||||
AR_PHY_65NM_RXRF_AGC_AGC2G_CALDAC_OVR, 0x0);
|
||||
} else {
|
||||
if (is_2g)
|
||||
REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_AGC(chain),
|
||||
AR_PHY_65NM_RXRF_AGC_AGC2G_DBDAC_OVR, 0x0);
|
||||
else
|
||||
REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_AGC(chain),
|
||||
AR_PHY_65NM_RXRF_AGC_AGC5G_DBDAC_OVR, 0x0);
|
||||
}
|
||||
|
||||
for (i = 6; i > 0; i--) {
|
||||
offset[i] = BIT(i - 1);
|
||||
|
@ -964,9 +970,9 @@ static void ar9003_hw_manual_peak_cal(struct ath_hw *ah, u8 chain, bool is_2g)
|
|||
AR_PHY_65NM_RXRF_AGC_AGC_CAL_OVR, 0);
|
||||
}
|
||||
|
||||
static void ar9003_hw_do_manual_peak_cal(struct ath_hw *ah,
|
||||
struct ath9k_channel *chan,
|
||||
bool run_rtt_cal)
|
||||
static void ar9003_hw_do_pcoem_manual_peak_cal(struct ath_hw *ah,
|
||||
struct ath9k_channel *chan,
|
||||
bool run_rtt_cal)
|
||||
{
|
||||
struct ath9k_hw_cal_data *caldata = ah->caldata;
|
||||
int i;
|
||||
|
@ -1145,7 +1151,7 @@ static bool ar9003_hw_init_cal_pcoem(struct ath_hw *ah,
|
|||
AR_PHY_AGC_CONTROL_CAL,
|
||||
0, AH_WAIT_TIMEOUT);
|
||||
|
||||
ar9003_hw_do_manual_peak_cal(ah, chan, run_rtt_cal);
|
||||
ar9003_hw_do_pcoem_manual_peak_cal(ah, chan, run_rtt_cal);
|
||||
}
|
||||
|
||||
if (REG_READ(ah, AR_PHY_CL_CAL_CTL) & AR_PHY_CL_CAL_ENABLE) {
|
||||
|
@ -1267,6 +1273,9 @@ static bool ar9003_hw_init_cal_soc(struct ath_hw *ah,
|
|||
|
||||
skip_tx_iqcal:
|
||||
if (run_agc_cal || !(ah->ah_flags & AH_FASTCC)) {
|
||||
if (AR_SREV_9330_11(ah))
|
||||
ar9003_hw_manual_peak_cal(ah, 0, IS_CHAN_2GHZ(chan));
|
||||
|
||||
/* Calibrate the AGC */
|
||||
REG_WRITE(ah, AR_PHY_AGC_CONTROL,
|
||||
REG_READ(ah, AR_PHY_AGC_CONTROL) |
|
||||
|
|
|
@ -3965,7 +3965,7 @@ static void ar9003_hw_apply_tuning_caps(struct ath_hw *ah)
|
|||
struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
|
||||
u8 tuning_caps_param = eep->baseEepHeader.params_for_tuning_caps[0];
|
||||
|
||||
if (AR_SREV_9485(ah) || AR_SREV_9330(ah) || AR_SREV_9340(ah))
|
||||
if (AR_SREV_9340(ah))
|
||||
return;
|
||||
|
||||
if (eep->baseEepHeader.featureEnable & 0x40) {
|
||||
|
@ -4122,7 +4122,7 @@ static void ath9k_hw_ar9300_set_board_values(struct ath_hw *ah,
|
|||
ar9003_hw_xlna_bias_strength_apply(ah, is2ghz);
|
||||
ar9003_hw_atten_apply(ah, chan);
|
||||
ar9003_hw_quick_drop_apply(ah, chan->channel);
|
||||
if (!AR_SREV_9330(ah) && !AR_SREV_9340(ah) && !AR_SREV_9550(ah))
|
||||
if (!AR_SREV_9330(ah) && !AR_SREV_9340(ah))
|
||||
ar9003_hw_internal_regulator_apply(ah);
|
||||
ar9003_hw_apply_tuning_caps(ah);
|
||||
ar9003_hw_txend_to_xpa_off_apply(ah, is2ghz);
|
||||
|
|
|
@ -17,6 +17,7 @@
|
|||
#include "hw.h"
|
||||
#include "ar9003_mac.h"
|
||||
#include "ar9003_2p2_initvals.h"
|
||||
#include "ar9003_buffalo_initvals.h"
|
||||
#include "ar9485_initvals.h"
|
||||
#include "ar9340_initvals.h"
|
||||
#include "ar9330_1p1_initvals.h"
|
||||
|
@ -152,6 +153,8 @@ static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
|
|||
ar9340Modes_fast_clock_1p0);
|
||||
INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
|
||||
ar9340_1p0_baseband_core_txfir_coeff_japan_2484);
|
||||
INIT_INI_ARRAY(&ah->ini_dfs,
|
||||
ar9340_1p0_baseband_postamble_dfs_channel);
|
||||
|
||||
if (!ah->is_clk_25mhz)
|
||||
INIT_INI_ARRAY(&ah->iniAdditional,
|
||||
|
@ -340,6 +343,8 @@ static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
|
|||
ar9580_1p0_modes_fast_clock);
|
||||
INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
|
||||
ar9580_1p0_baseband_core_txfir_coeff_japan_2484);
|
||||
INIT_INI_ARRAY(&ah->ini_dfs,
|
||||
ar9580_1p0_baseband_postamble_dfs_channel);
|
||||
} else if (AR_SREV_9565_11_OR_LATER(ah)) {
|
||||
INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
|
||||
ar9565_1p1_mac_core);
|
||||
|
@ -458,6 +463,8 @@ static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
|
|||
ar9300Modes_fast_clock_2p2);
|
||||
INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
|
||||
ar9300_2p2_baseband_core_txfir_coeff_japan_2484);
|
||||
INIT_INI_ARRAY(&ah->ini_dfs,
|
||||
ar9300_2p2_baseband_postamble_dfs_channel);
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -586,9 +593,14 @@ static void ar9003_tx_gain_table_mode3(struct ath_hw *ah)
|
|||
else if (AR_SREV_9565(ah))
|
||||
INIT_INI_ARRAY(&ah->iniModesTxGain,
|
||||
ar9565_1p0_modes_high_power_tx_gain_table);
|
||||
else
|
||||
INIT_INI_ARRAY(&ah->iniModesTxGain,
|
||||
ar9300Modes_high_power_tx_gain_table_2p2);
|
||||
else {
|
||||
if (ah->config.tx_gain_buffalo)
|
||||
INIT_INI_ARRAY(&ah->iniModesTxGain,
|
||||
ar9300Modes_high_power_tx_gain_table_buffalo);
|
||||
else
|
||||
INIT_INI_ARRAY(&ah->iniModesTxGain,
|
||||
ar9300Modes_high_power_tx_gain_table_2p2);
|
||||
}
|
||||
}
|
||||
|
||||
static void ar9003_tx_gain_table_mode4(struct ath_hw *ah)
|
||||
|
|
|
@ -1332,6 +1332,7 @@ static void ar9003_hw_ani_cache_ini_regs(struct ath_hw *ah)
|
|||
static void ar9003_hw_set_radar_params(struct ath_hw *ah,
|
||||
struct ath_hw_radar_conf *conf)
|
||||
{
|
||||
unsigned int regWrites = 0;
|
||||
u32 radar_0 = 0, radar_1 = 0;
|
||||
|
||||
if (!conf) {
|
||||
|
@ -1358,6 +1359,11 @@ static void ar9003_hw_set_radar_params(struct ath_hw *ah,
|
|||
REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
|
||||
else
|
||||
REG_CLR_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
|
||||
|
||||
if (AR_SREV_9300(ah) || AR_SREV_9340(ah) || AR_SREV_9580(ah)) {
|
||||
REG_WRITE_ARRAY(&ah->ini_dfs,
|
||||
IS_CHAN_HT40(ah->curchan) ? 2 : 1, regWrites);
|
||||
}
|
||||
}
|
||||
|
||||
static void ar9003_hw_set_radar_conf(struct ath_hw *ah)
|
||||
|
|
|
@ -341,14 +341,15 @@
|
|||
#define AR_PHY_CCA_MAX_GOOD_VAL_9300_2GHZ -95
|
||||
#define AR_PHY_CCA_MAX_GOOD_VAL_9300_5GHZ -100
|
||||
|
||||
#define AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_2GHZ -95
|
||||
#define AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_5GHZ -100
|
||||
|
||||
#define AR_PHY_CCA_NOM_VAL_9462_2GHZ -127
|
||||
#define AR_PHY_CCA_MIN_GOOD_VAL_9462_2GHZ -127
|
||||
#define AR_PHY_CCA_MAX_GOOD_VAL_9462_2GHZ -60
|
||||
#define AR_PHY_CCA_MAX_GOOD_VAL_9462_FCC_2GHZ -95
|
||||
#define AR_PHY_CCA_NOM_VAL_9462_5GHZ -127
|
||||
#define AR_PHY_CCA_MIN_GOOD_VAL_9462_5GHZ -127
|
||||
#define AR_PHY_CCA_MAX_GOOD_VAL_9462_5GHZ -60
|
||||
#define AR_PHY_CCA_MAX_GOOD_VAL_9462_FCC_5GHZ -100
|
||||
|
||||
#define AR_PHY_CCA_NOM_VAL_9330_2GHZ -118
|
||||
|
||||
|
|
|
@ -18,6 +18,10 @@
|
|||
#ifndef INITVALS_9330_1P1_H
|
||||
#define INITVALS_9330_1P1_H
|
||||
|
||||
#define ar9331_1p1_baseband_core_txfir_coeff_japan_2484 ar9300_2p2_baseband_core_txfir_coeff_japan_2484
|
||||
|
||||
#define ar9331_modes_high_power_tx_gain_1p1 ar9331_modes_lowest_ob_db_tx_gain_1p1
|
||||
|
||||
static const u32 ar9331_1p1_baseband_postamble[][5] = {
|
||||
/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
|
||||
{0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8005, 0xd00a8005},
|
||||
|
@ -55,7 +59,7 @@ static const u32 ar9331_1p1_baseband_postamble[][5] = {
|
|||
{0x0000a284, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
|
||||
{0x0000a288, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
|
||||
{0x0000a28c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
|
||||
{0x0000a2c4, 0x00158d18, 0x00158d18, 0x00158d18, 0x00158d18},
|
||||
{0x0000a2c4, 0x00158d18, 0x00158d18, 0x00058d18, 0x00058d18},
|
||||
{0x0000a2d0, 0x00071982, 0x00071982, 0x00071982, 0x00071982},
|
||||
{0x0000a2d8, 0xf999a83a, 0xf999a83a, 0xf999a83a, 0xf999a83a},
|
||||
{0x0000a358, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
|
||||
|
@ -252,7 +256,7 @@ static const u32 ar9331_modes_low_ob_db_tx_gain_1p1[][5] = {
|
|||
{0x0000a2e0, 0xffffcc84, 0xffffcc84, 0xffffcc84, 0xffffcc84},
|
||||
{0x0000a2e4, 0xfffff000, 0xfffff000, 0xfffff000, 0xfffff000},
|
||||
{0x0000a2e8, 0xfffe0000, 0xfffe0000, 0xfffe0000, 0xfffe0000},
|
||||
{0x0000a410, 0x000050d7, 0x000050d7, 0x000050d0, 0x000050d0},
|
||||
{0x0000a410, 0x000050d7, 0x000050d7, 0x000050d4, 0x000050d4},
|
||||
{0x0000a500, 0x00022200, 0x00022200, 0x00000000, 0x00000000},
|
||||
{0x0000a504, 0x05062002, 0x05062002, 0x04000002, 0x04000002},
|
||||
{0x0000a508, 0x0c002e00, 0x0c002e00, 0x08000004, 0x08000004},
|
||||
|
@ -337,8 +341,6 @@ static const u32 ar9331_modes_low_ob_db_tx_gain_1p1[][5] = {
|
|||
{0x00016284, 0x14d3f000, 0x14d3f000, 0x14d3f000, 0x14d3f000},
|
||||
};
|
||||
|
||||
#define ar9331_1p1_baseband_core_txfir_coeff_japan_2484 ar9462_2p0_baseband_core_txfir_coeff_japan_2484
|
||||
|
||||
static const u32 ar9331_1p1_xtal_25M[][2] = {
|
||||
/* Addr allmodes */
|
||||
{0x00007038, 0x000002f8},
|
||||
|
@ -373,17 +375,17 @@ static const u32 ar9331_1p1_radio_core[][2] = {
|
|||
{0x000160b4, 0x92480040},
|
||||
{0x000160c0, 0x006db6db},
|
||||
{0x000160c4, 0x0186db60},
|
||||
{0x000160c8, 0x6db4db6c},
|
||||
{0x000160c8, 0x6db6db6c},
|
||||
{0x000160cc, 0x6de6c300},
|
||||
{0x000160d0, 0x14500820},
|
||||
{0x00016100, 0x04cb0001},
|
||||
{0x00016104, 0xfff80015},
|
||||
{0x00016108, 0x00080010},
|
||||
{0x0001610c, 0x00170000},
|
||||
{0x00016140, 0x10800000},
|
||||
{0x00016140, 0x50804000},
|
||||
{0x00016144, 0x01884080},
|
||||
{0x00016148, 0x000080c0},
|
||||
{0x00016280, 0x01000015},
|
||||
{0x00016280, 0x01001015},
|
||||
{0x00016284, 0x14d20000},
|
||||
{0x00016288, 0x00318000},
|
||||
{0x0001628c, 0x50000000},
|
||||
|
@ -622,12 +624,12 @@ static const u32 ar9331_1p1_baseband_core[][2] = {
|
|||
{0x0000a370, 0x00000000},
|
||||
{0x0000a390, 0x00000001},
|
||||
{0x0000a394, 0x00000444},
|
||||
{0x0000a398, 0x001f0e0f},
|
||||
{0x0000a39c, 0x0075393f},
|
||||
{0x0000a3a0, 0xb79f6427},
|
||||
{0x0000a3a4, 0x00000000},
|
||||
{0x0000a3a8, 0xaaaaaaaa},
|
||||
{0x0000a3ac, 0x3c466478},
|
||||
{0x0000a398, 0x00000000},
|
||||
{0x0000a39c, 0x210d0401},
|
||||
{0x0000a3a0, 0xab9a7144},
|
||||
{0x0000a3a4, 0x00000011},
|
||||
{0x0000a3a8, 0x3c3c003d},
|
||||
{0x0000a3ac, 0x30310030},
|
||||
{0x0000a3c0, 0x20202020},
|
||||
{0x0000a3c4, 0x22222220},
|
||||
{0x0000a3c8, 0x20200020},
|
||||
|
@ -686,100 +688,18 @@ static const u32 ar9331_1p1_baseband_core[][2] = {
|
|||
{0x0000a7dc, 0x00000001},
|
||||
};
|
||||
|
||||
static const u32 ar9331_modes_high_power_tx_gain_1p1[][5] = {
|
||||
static const u32 ar9331_1p1_mac_postamble[][5] = {
|
||||
/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
|
||||
{0x0000a2d8, 0x7999a83a, 0x7999a83a, 0x7999a83a, 0x7999a83a},
|
||||
{0x0000a2dc, 0xffff2a52, 0xffff2a52, 0xffff2a52, 0xffff2a52},
|
||||
{0x0000a2e0, 0xffffcc84, 0xffffcc84, 0xffffcc84, 0xffffcc84},
|
||||
{0x0000a2e4, 0xfffff000, 0xfffff000, 0xfffff000, 0xfffff000},
|
||||
{0x0000a2e8, 0xfffe0000, 0xfffe0000, 0xfffe0000, 0xfffe0000},
|
||||
{0x0000a410, 0x000050d7, 0x000050d7, 0x000050d0, 0x000050d0},
|
||||
{0x0000a500, 0x00022200, 0x00022200, 0x00000000, 0x00000000},
|
||||
{0x0000a504, 0x05062002, 0x05062002, 0x04000002, 0x04000002},
|
||||
{0x0000a508, 0x0c002e00, 0x0c002e00, 0x08000004, 0x08000004},
|
||||
{0x0000a50c, 0x11062202, 0x11062202, 0x0d000200, 0x0d000200},
|
||||
{0x0000a510, 0x17022e00, 0x17022e00, 0x11000202, 0x11000202},
|
||||
{0x0000a514, 0x1d000ec2, 0x1d000ec2, 0x15000400, 0x15000400},
|
||||
{0x0000a518, 0x25020ec0, 0x25020ec0, 0x19000402, 0x19000402},
|
||||
{0x0000a51c, 0x2b020ec3, 0x2b020ec3, 0x1d000404, 0x1d000404},
|
||||
{0x0000a520, 0x2f001f04, 0x2f001f04, 0x23000a00, 0x23000a00},
|
||||
{0x0000a524, 0x35001fc4, 0x35001fc4, 0x27000a02, 0x27000a02},
|
||||
{0x0000a528, 0x3c022f04, 0x3c022f04, 0x2b000a04, 0x2b000a04},
|
||||
{0x0000a52c, 0x41023e85, 0x41023e85, 0x2d000a20, 0x2d000a20},
|
||||
{0x0000a530, 0x48023ec6, 0x48023ec6, 0x31000a22, 0x31000a22},
|
||||
{0x0000a534, 0x4d023f01, 0x4d023f01, 0x35000a24, 0x35000a24},
|
||||
{0x0000a538, 0x53023f4b, 0x53023f4b, 0x38000a43, 0x38000a43},
|
||||
{0x0000a53c, 0x5a027f09, 0x5a027f09, 0x3b000e42, 0x3b000e42},
|
||||
{0x0000a540, 0x5f027fc9, 0x5f027fc9, 0x3f000e44, 0x3f000e44},
|
||||
{0x0000a544, 0x6502feca, 0x6502feca, 0x42000e64, 0x42000e64},
|
||||
{0x0000a548, 0x6b02ff4a, 0x6b02ff4a, 0x46000e66, 0x46000e66},
|
||||
{0x0000a54c, 0x7203feca, 0x7203feca, 0x4a000ea6, 0x4a000ea6},
|
||||
{0x0000a550, 0x7703ff0b, 0x7703ff0b, 0x4a000ea6, 0x4a000ea6},
|
||||
{0x0000a554, 0x7d06ffcb, 0x7d06ffcb, 0x4a000ea6, 0x4a000ea6},
|
||||
{0x0000a558, 0x8407ff0b, 0x8407ff0b, 0x4a000ea6, 0x4a000ea6},
|
||||
{0x0000a55c, 0x8907ffcb, 0x8907ffcb, 0x4a000ea6, 0x4a000ea6},
|
||||
{0x0000a560, 0x900fff0b, 0x900fff0b, 0x4a000ea6, 0x4a000ea6},
|
||||
{0x0000a564, 0x960fffcb, 0x960fffcb, 0x4a000ea6, 0x4a000ea6},
|
||||
{0x0000a568, 0x9c1fff0b, 0x9c1fff0b, 0x4a000ea6, 0x4a000ea6},
|
||||
{0x0000a56c, 0x9c1fff0b, 0x9c1fff0b, 0x4a000ea6, 0x4a000ea6},
|
||||
{0x0000a570, 0x9c1fff0b, 0x9c1fff0b, 0x4a000ea6, 0x4a000ea6},
|
||||
{0x0000a574, 0x9c1fff0b, 0x9c1fff0b, 0x4a000ea6, 0x4a000ea6},
|
||||
{0x0000a578, 0x9c1fff0b, 0x9c1fff0b, 0x4a000ea6, 0x4a000ea6},
|
||||
{0x0000a57c, 0x9c1fff0b, 0x9c1fff0b, 0x4a000ea6, 0x4a000ea6},
|
||||
{0x0000a580, 0x00022200, 0x00022200, 0x00000000, 0x00000000},
|
||||
{0x0000a584, 0x05062002, 0x05062002, 0x04000002, 0x04000002},
|
||||
{0x0000a588, 0x0c002e00, 0x0c002e00, 0x08000004, 0x08000004},
|
||||
{0x0000a58c, 0x11062202, 0x11062202, 0x0b000200, 0x0b000200},
|
||||
{0x0000a590, 0x17022e00, 0x17022e00, 0x0f000202, 0x0f000202},
|
||||
{0x0000a594, 0x1d000ec2, 0x1d000ec2, 0x11000400, 0x11000400},
|
||||
{0x0000a598, 0x25020ec0, 0x25020ec0, 0x15000402, 0x15000402},
|
||||
{0x0000a59c, 0x2b020ec3, 0x2b020ec3, 0x19000404, 0x19000404},
|
||||
{0x0000a5a0, 0x2f001f04, 0x2f001f04, 0x1b000603, 0x1b000603},
|
||||
{0x0000a5a4, 0x35001fc4, 0x35001fc4, 0x1f000a02, 0x1f000a02},
|
||||
{0x0000a5a8, 0x3c022f04, 0x3c022f04, 0x23000a04, 0x23000a04},
|
||||
{0x0000a5ac, 0x41023e85, 0x41023e85, 0x26000a20, 0x26000a20},
|
||||
{0x0000a5b0, 0x48023ec6, 0x48023ec6, 0x2a000e20, 0x2a000e20},
|
||||
{0x0000a5b4, 0x4d023f01, 0x4d023f01, 0x2e000e22, 0x2e000e22},
|
||||
{0x0000a5b8, 0x53023f4b, 0x53023f4b, 0x31000e24, 0x31000e24},
|
||||
{0x0000a5bc, 0x5a027f09, 0x5a027f09, 0x34001640, 0x34001640},
|
||||
{0x0000a5c0, 0x5f027fc9, 0x5f027fc9, 0x38001660, 0x38001660},
|
||||
{0x0000a5c4, 0x6502feca, 0x6502feca, 0x3b001861, 0x3b001861},
|
||||
{0x0000a5c8, 0x6b02ff4a, 0x6b02ff4a, 0x3e001a81, 0x3e001a81},
|
||||
{0x0000a5cc, 0x7203feca, 0x7203feca, 0x42001a83, 0x42001a83},
|
||||
{0x0000a5d0, 0x7703ff0b, 0x7703ff0b, 0x44001c84, 0x44001c84},
|
||||
{0x0000a5d4, 0x7d06ffcb, 0x7d06ffcb, 0x48001ce3, 0x48001ce3},
|
||||
{0x0000a5d8, 0x8407ff0b, 0x8407ff0b, 0x4c001ce5, 0x4c001ce5},
|
||||
{0x0000a5dc, 0x8907ffcb, 0x8907ffcb, 0x50001ce9, 0x50001ce9},
|
||||
{0x0000a5e0, 0x900fff0b, 0x900fff0b, 0x54001ceb, 0x54001ceb},
|
||||
{0x0000a5e4, 0x960fffcb, 0x960fffcb, 0x56001eec, 0x56001eec},
|
||||
{0x0000a5e8, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
|
||||
{0x0000a5ec, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
|
||||
{0x0000a5f0, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
|
||||
{0x0000a5f4, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
|
||||
{0x0000a5f8, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
|
||||
{0x0000a5fc, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
|
||||
{0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
|
||||
{0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
|
||||
{0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
|
||||
{0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
|
||||
{0x0000a610, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
|
||||
{0x0000a614, 0x01404000, 0x01404000, 0x01404000, 0x01404000},
|
||||
{0x0000a618, 0x01404501, 0x01404501, 0x01404501, 0x01404501},
|
||||
{0x0000a61c, 0x02008802, 0x02008802, 0x02008802, 0x02008802},
|
||||
{0x0000a620, 0x0280c802, 0x0280c802, 0x0280c802, 0x0280c802},
|
||||
{0x0000a624, 0x03010a03, 0x03010a03, 0x03010a03, 0x03010a03},
|
||||
{0x0000a628, 0x03010c04, 0x03010c04, 0x03010c04, 0x03010c04},
|
||||
{0x0000a62c, 0x03010c04, 0x03010c04, 0x03010c04, 0x03010c04},
|
||||
{0x0000a630, 0x03010c04, 0x03010c04, 0x03010c04, 0x03010c04},
|
||||
{0x0000a634, 0x03010c04, 0x03010c04, 0x03010c04, 0x03010c04},
|
||||
{0x0000a638, 0x03010c04, 0x03010c04, 0x03010c04, 0x03010c04},
|
||||
{0x0000a63c, 0x03010c04, 0x03010c04, 0x03010c04, 0x03010c04},
|
||||
{0x00016044, 0x034922db, 0x034922db, 0x034922db, 0x034922db},
|
||||
{0x00016284, 0x14d3f000, 0x14d3f000, 0x14d3f000, 0x14d3f000},
|
||||
{0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160},
|
||||
{0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c},
|
||||
{0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38},
|
||||
{0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00},
|
||||
{0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b},
|
||||
{0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810},
|
||||
{0x000081d0, 0x00003210, 0x00003210, 0x0000320a, 0x0000320a},
|
||||
{0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440},
|
||||
};
|
||||
|
||||
#define ar9331_1p1_mac_postamble ar9300_2p2_mac_postamble
|
||||
|
||||
static const u32 ar9331_1p1_soc_preamble[][2] = {
|
||||
/* Addr allmodes */
|
||||
{0x00007020, 0x00000000},
|
||||
|
|
|
@ -18,6 +18,28 @@
|
|||
#ifndef INITVALS_9330_1P2_H
|
||||
#define INITVALS_9330_1P2_H
|
||||
|
||||
#define ar9331_modes_high_power_tx_gain_1p2 ar9331_modes_high_ob_db_tx_gain_1p2
|
||||
|
||||
#define ar9331_modes_low_ob_db_tx_gain_1p2 ar9331_modes_high_ob_db_tx_gain_1p2
|
||||
|
||||
#define ar9331_modes_lowest_ob_db_tx_gain_1p2 ar9331_modes_high_ob_db_tx_gain_1p2
|
||||
|
||||
#define ar9331_1p2_baseband_core_txfir_coeff_japan_2484 ar9331_1p1_baseband_core_txfir_coeff_japan_2484
|
||||
|
||||
#define ar9331_1p2_xtal_25M ar9331_1p1_xtal_25M
|
||||
|
||||
#define ar9331_1p2_xtal_40M ar9331_1p1_xtal_40M
|
||||
|
||||
#define ar9331_1p2_soc_postamble ar9331_1p1_soc_postamble
|
||||
|
||||
#define ar9331_1p2_mac_postamble ar9331_1p1_mac_postamble
|
||||
|
||||
#define ar9331_1p2_soc_preamble ar9331_1p1_soc_preamble
|
||||
|
||||
#define ar9331_1p2_mac_core ar9331_1p1_mac_core
|
||||
|
||||
#define ar9331_common_wo_xlna_rx_gain_1p2 ar9331_common_wo_xlna_rx_gain_1p1
|
||||
|
||||
static const u32 ar9331_modes_high_ob_db_tx_gain_1p2[][5] = {
|
||||
/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
|
||||
{0x0000a410, 0x000050d7, 0x000050d7, 0x000050d7, 0x000050d7},
|
||||
|
@ -103,57 +125,6 @@ static const u32 ar9331_modes_high_ob_db_tx_gain_1p2[][5] = {
|
|||
{0x0000a63c, 0x04011004, 0x04011004, 0x04011004, 0x04011004},
|
||||
};
|
||||
|
||||
#define ar9331_modes_high_power_tx_gain_1p2 ar9331_modes_high_ob_db_tx_gain_1p2
|
||||
|
||||
#define ar9331_modes_low_ob_db_tx_gain_1p2 ar9331_modes_high_power_tx_gain_1p2
|
||||
|
||||
#define ar9331_modes_lowest_ob_db_tx_gain_1p2 ar9331_modes_low_ob_db_tx_gain_1p2
|
||||
|
||||
static const u32 ar9331_1p2_baseband_postamble[][5] = {
|
||||
/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
|
||||
{0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8005, 0xd00a8005},
|
||||
{0x00009820, 0x206a002e, 0x206a002e, 0x206a002e, 0x206a002e},
|
||||
{0x00009824, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0},
|
||||
{0x00009828, 0x06903081, 0x06903081, 0x06903881, 0x06903881},
|
||||
{0x0000982c, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4},
|
||||
{0x00009830, 0x0000059c, 0x0000059c, 0x0000059c, 0x0000059c},
|
||||
{0x00009c00, 0x00000044, 0x00000044, 0x00000044, 0x00000044},
|
||||
{0x00009e00, 0x0372161e, 0x0372161e, 0x037216a4, 0x037216a4},
|
||||
{0x00009e04, 0x00182020, 0x00182020, 0x00182020, 0x00182020},
|
||||
{0x00009e0c, 0x6c4000e2, 0x6d4000e2, 0x6d4000e2, 0x6c4000e2},
|
||||
{0x00009e10, 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e},
|
||||
{0x00009e14, 0x31395d5e, 0x3139605e, 0x3139605e, 0x31395d5e},
|
||||
{0x00009e18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
|
||||
{0x00009e1c, 0x0001cf9c, 0x0001cf9c, 0x00021f9c, 0x00021f9c},
|
||||
{0x00009e20, 0x000003b5, 0x000003b5, 0x000003ce, 0x000003ce},
|
||||
{0x00009e2c, 0x0000001c, 0x0000001c, 0x00003221, 0x00003221},
|
||||
{0x00009e3c, 0xcf946222, 0xcf946222, 0xcf946222, 0xcf946222},
|
||||
{0x00009e44, 0x02321e27, 0x02321e27, 0x02282324, 0x02282324},
|
||||
{0x00009e48, 0x5030201a, 0x5030201a, 0x50302010, 0x50302010},
|
||||
{0x00009fc8, 0x0003f000, 0x0003f000, 0x0001a000, 0x0001a000},
|
||||
{0x0000a204, 0x00003fc0, 0x00003fc4, 0x00003fc4, 0x00003fc0},
|
||||
{0x0000a208, 0x00000104, 0x00000104, 0x00000004, 0x00000004},
|
||||
{0x0000a230, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b},
|
||||
{0x0000a234, 0x00000fff, 0x00000fff, 0x10000fff, 0x00000fff},
|
||||
{0x0000a238, 0xffb81018, 0xffb81018, 0xffb81018, 0xffb81018},
|
||||
{0x0000a250, 0x00000000, 0x00000000, 0x00000210, 0x00000108},
|
||||
{0x0000a254, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898},
|
||||
{0x0000a258, 0x02020002, 0x02020002, 0x02020002, 0x02020002},
|
||||
{0x0000a25c, 0x01000e0e, 0x01000e0e, 0x01000e0e, 0x01000e0e},
|
||||
{0x0000a260, 0x3a021501, 0x3a021501, 0x3a021501, 0x3a021501},
|
||||
{0x0000a264, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e},
|
||||
{0x0000a280, 0x00000007, 0x00000007, 0x0000000b, 0x0000000b},
|
||||
{0x0000a284, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
|
||||
{0x0000a288, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
|
||||
{0x0000a28c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
|
||||
{0x0000a2c4, 0x00158d18, 0x00158d18, 0x00158d18, 0x00158d18},
|
||||
{0x0000a2d0, 0x00071981, 0x00071981, 0x00071981, 0x00071981},
|
||||
{0x0000a2d8, 0xf999a83a, 0xf999a83a, 0xf999a83a, 0xf999a83a},
|
||||
{0x0000a358, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
|
||||
{0x0000ae04, 0x00802020, 0x00802020, 0x00802020, 0x00802020},
|
||||
{0x0000ae18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
|
||||
};
|
||||
|
||||
static const u32 ar9331_1p2_radio_core[][2] = {
|
||||
/* Addr allmodes */
|
||||
{0x00016000, 0x36db6db6},
|
||||
|
@ -219,24 +190,318 @@ static const u32 ar9331_1p2_radio_core[][2] = {
|
|||
{0x000163d4, 0x00000000},
|
||||
};
|
||||
|
||||
#define ar9331_1p2_baseband_core_txfir_coeff_japan_2484 ar9331_1p1_baseband_core_txfir_coeff_japan_2484
|
||||
static const u32 ar9331_1p2_baseband_core[][2] = {
|
||||
/* Addr allmodes */
|
||||
{0x00009800, 0xafe68e30},
|
||||
{0x00009804, 0xfd14e000},
|
||||
{0x00009808, 0x9c0a8f6b},
|
||||
{0x0000980c, 0x04800000},
|
||||
{0x00009814, 0x9280c00a},
|
||||
{0x00009818, 0x00000000},
|
||||
{0x0000981c, 0x00020028},
|
||||
{0x00009834, 0x5f3ca3de},
|
||||
{0x00009838, 0x0108ecff},
|
||||
{0x0000983c, 0x14750600},
|
||||
{0x00009880, 0x201fff00},
|
||||
{0x00009884, 0x00001042},
|
||||
{0x000098a4, 0x00200400},
|
||||
{0x000098b0, 0x32840bbe},
|
||||
{0x000098d0, 0x004b6a8e},
|
||||
{0x000098d4, 0x00000820},
|
||||
{0x000098dc, 0x00000000},
|
||||
{0x000098f0, 0x00000000},
|
||||
{0x000098f4, 0x00000000},
|
||||
{0x00009c04, 0x00000000},
|
||||
{0x00009c08, 0x03200000},
|
||||
{0x00009c0c, 0x00000000},
|
||||
{0x00009c10, 0x00000000},
|
||||
{0x00009c14, 0x00046384},
|
||||
{0x00009c18, 0x05b6b440},
|
||||
{0x00009c1c, 0x00b6b440},
|
||||
{0x00009d00, 0xc080a333},
|
||||
{0x00009d04, 0x40206c10},
|
||||
{0x00009d08, 0x009c4060},
|
||||
{0x00009d0c, 0x1883800a},
|
||||
{0x00009d10, 0x01834061},
|
||||
{0x00009d14, 0x00c00400},
|
||||
{0x00009d18, 0x00000000},
|
||||
{0x00009e08, 0x0038233c},
|
||||
{0x00009e24, 0x9927b515},
|
||||
{0x00009e28, 0x12ef0200},
|
||||
{0x00009e30, 0x06336f77},
|
||||
{0x00009e34, 0x6af6532f},
|
||||
{0x00009e38, 0x0cc80c00},
|
||||
{0x00009e40, 0x0d261820},
|
||||
{0x00009e4c, 0x00001004},
|
||||
{0x00009e50, 0x00ff03f1},
|
||||
{0x00009fc0, 0x803e4788},
|
||||
{0x00009fc4, 0x0001efb5},
|
||||
{0x00009fcc, 0x40000014},
|
||||
{0x0000a20c, 0x00000000},
|
||||
{0x0000a220, 0x00000000},
|
||||
{0x0000a224, 0x00000000},
|
||||
{0x0000a228, 0x10002310},
|
||||
{0x0000a23c, 0x00000000},
|
||||
{0x0000a244, 0x0c000000},
|
||||
{0x0000a2a0, 0x00000001},
|
||||
{0x0000a2c0, 0x00000001},
|
||||
{0x0000a2c8, 0x00000000},
|
||||
{0x0000a2cc, 0x18c43433},
|
||||
{0x0000a2d4, 0x00000000},
|
||||
{0x0000a2dc, 0x00000000},
|
||||
{0x0000a2e0, 0x00000000},
|
||||
{0x0000a2e4, 0x00000000},
|
||||
{0x0000a2e8, 0x00000000},
|
||||
{0x0000a2ec, 0x00000000},
|
||||
{0x0000a2f0, 0x00000000},
|
||||
{0x0000a2f4, 0x00000000},
|
||||
{0x0000a2f8, 0x00000000},
|
||||
{0x0000a344, 0x00000000},
|
||||
{0x0000a34c, 0x00000000},
|
||||
{0x0000a350, 0x0000a000},
|
||||
{0x0000a364, 0x00000000},
|
||||
{0x0000a370, 0x00000000},
|
||||
{0x0000a390, 0x00000001},
|
||||
{0x0000a394, 0x00000444},
|
||||
{0x0000a398, 0x001f0e0f},
|
||||
{0x0000a39c, 0x0075393f},
|
||||
{0x0000a3a0, 0xb79f6427},
|
||||
{0x0000a3a4, 0x00000000},
|
||||
{0x0000a3a8, 0xaaaaaaaa},
|
||||
{0x0000a3ac, 0x3c466478},
|
||||
{0x0000a3c0, 0x20202020},
|
||||
{0x0000a3c4, 0x22222220},
|
||||
{0x0000a3c8, 0x20200020},
|
||||
{0x0000a3cc, 0x20202020},
|
||||
{0x0000a3d0, 0x20202020},
|
||||
{0x0000a3d4, 0x20202020},
|
||||
{0x0000a3d8, 0x20202020},
|
||||
{0x0000a3dc, 0x20202020},
|
||||
{0x0000a3e0, 0x20202020},
|
||||
{0x0000a3e4, 0x20202020},
|
||||
{0x0000a3e8, 0x20202020},
|
||||
{0x0000a3ec, 0x20202020},
|
||||
{0x0000a3f0, 0x00000000},
|
||||
{0x0000a3f4, 0x00000006},
|
||||
{0x0000a3f8, 0x0cdbd380},
|
||||
{0x0000a3fc, 0x000f0f01},
|
||||
{0x0000a400, 0x8fa91f01},
|
||||
{0x0000a404, 0x00000000},
|
||||
{0x0000a408, 0x0e79e5c6},
|
||||
{0x0000a40c, 0x00820820},
|
||||
{0x0000a414, 0x1ce739ce},
|
||||
{0x0000a418, 0x2d001dce},
|
||||
{0x0000a41c, 0x1ce739ce},
|
||||
{0x0000a420, 0x000001ce},
|
||||
{0x0000a424, 0x1ce739ce},
|
||||
{0x0000a428, 0x000001ce},
|
||||
{0x0000a42c, 0x1ce739ce},
|
||||
{0x0000a430, 0x1ce739ce},
|
||||
{0x0000a434, 0x00000000},
|
||||
{0x0000a438, 0x00001801},
|
||||
{0x0000a43c, 0x00000000},
|
||||
{0x0000a440, 0x00000000},
|
||||
{0x0000a444, 0x00000000},
|
||||
{0x0000a448, 0x04000000},
|
||||
{0x0000a44c, 0x00000001},
|
||||
{0x0000a450, 0x00010000},
|
||||
{0x0000a458, 0x00000000},
|
||||
{0x0000a640, 0x00000000},
|
||||
{0x0000a644, 0x3fad9d74},
|
||||
{0x0000a648, 0x0048060a},
|
||||
{0x0000a64c, 0x00003c37},
|
||||
{0x0000a670, 0x03020100},
|
||||
{0x0000a674, 0x09080504},
|
||||
{0x0000a678, 0x0d0c0b0a},
|
||||
{0x0000a67c, 0x13121110},
|
||||
{0x0000a680, 0x31301514},
|
||||
{0x0000a684, 0x35343332},
|
||||
{0x0000a688, 0x00000036},
|
||||
{0x0000a690, 0x00000838},
|
||||
{0x0000a7c0, 0x00000000},
|
||||
{0x0000a7c4, 0xfffffffc},
|
||||
{0x0000a7c8, 0x00000000},
|
||||
{0x0000a7cc, 0x00000000},
|
||||
{0x0000a7d0, 0x00000000},
|
||||
{0x0000a7d4, 0x00000004},
|
||||
{0x0000a7dc, 0x00000001},
|
||||
};
|
||||
|
||||
#define ar9331_1p2_xtal_25M ar9331_1p1_xtal_25M
|
||||
static const u32 ar9331_1p2_baseband_postamble[][5] = {
|
||||
/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
|
||||
{0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8005, 0xd00a8005},
|
||||
{0x00009820, 0x206a002e, 0x206a002e, 0x206a002e, 0x206a002e},
|
||||
{0x00009824, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0},
|
||||
{0x00009828, 0x06903081, 0x06903081, 0x06903881, 0x06903881},
|
||||
{0x0000982c, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4},
|
||||
{0x00009830, 0x0000059c, 0x0000059c, 0x0000059c, 0x0000059c},
|
||||
{0x00009c00, 0x00000044, 0x00000044, 0x00000044, 0x00000044},
|
||||
{0x00009e00, 0x0372161e, 0x0372161e, 0x037216a4, 0x037216a4},
|
||||
{0x00009e04, 0x00182020, 0x00182020, 0x00182020, 0x00182020},
|
||||
{0x00009e0c, 0x6c4000e2, 0x6d4000e2, 0x6d4000e2, 0x6c4000e2},
|
||||
{0x00009e10, 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e},
|
||||
{0x00009e14, 0x31395d5e, 0x3139605e, 0x3139605e, 0x31395d5e},
|
||||
{0x00009e18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
|
||||
{0x00009e1c, 0x0001cf9c, 0x0001cf9c, 0x00021f9c, 0x00021f9c},
|
||||
{0x00009e20, 0x000003b5, 0x000003b5, 0x000003ce, 0x000003ce},
|
||||
{0x00009e2c, 0x0000001c, 0x0000001c, 0x00003221, 0x00003221},
|
||||
{0x00009e3c, 0xcf946222, 0xcf946222, 0xcf946222, 0xcf946222},
|
||||
{0x00009e44, 0x02321e27, 0x02321e27, 0x02282324, 0x02282324},
|
||||
{0x00009e48, 0x5030201a, 0x5030201a, 0x50302010, 0x50302010},
|
||||
{0x00009fc8, 0x0003f000, 0x0003f000, 0x0001a000, 0x0001a000},
|
||||
{0x0000a204, 0x00003fc0, 0x00003fc4, 0x00003fc4, 0x00003fc0},
|
||||
{0x0000a208, 0x00000104, 0x00000104, 0x00000004, 0x00000004},
|
||||
{0x0000a230, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b},
|
||||
{0x0000a234, 0x00000fff, 0x00000fff, 0x10000fff, 0x00000fff},
|
||||
{0x0000a238, 0xffb81018, 0xffb81018, 0xffb81018, 0xffb81018},
|
||||
{0x0000a250, 0x00000000, 0x00000000, 0x00000210, 0x00000108},
|
||||
{0x0000a254, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898},
|
||||
{0x0000a258, 0x02020002, 0x02020002, 0x02020002, 0x02020002},
|
||||
{0x0000a25c, 0x01000e0e, 0x01000e0e, 0x01000e0e, 0x01000e0e},
|
||||
{0x0000a260, 0x3a021501, 0x3a021501, 0x3a021501, 0x3a021501},
|
||||
{0x0000a264, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e},
|
||||
{0x0000a280, 0x00000007, 0x00000007, 0x0000000b, 0x0000000b},
|
||||
{0x0000a284, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
|
||||
{0x0000a288, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
|
||||
{0x0000a28c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
|
||||
{0x0000a2c4, 0x00158d18, 0x00158d18, 0x00158d18, 0x00158d18},
|
||||
{0x0000a2d0, 0x00071981, 0x00071981, 0x00071981, 0x00071981},
|
||||
{0x0000a2d8, 0xf999a83a, 0xf999a83a, 0xf999a83a, 0xf999a83a},
|
||||
{0x0000a358, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
|
||||
{0x0000ae04, 0x00802020, 0x00802020, 0x00802020, 0x00802020},
|
||||
{0x0000ae18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
|
||||
};
|
||||
|
||||
#define ar9331_1p2_xtal_40M ar9331_1p1_xtal_40M
|
||||
|
||||
#define ar9331_1p2_baseband_core ar9331_1p1_baseband_core
|
||||
|
||||
#define ar9331_1p2_soc_postamble ar9331_1p1_soc_postamble
|
||||
|
||||
#define ar9331_1p2_mac_postamble ar9331_1p1_mac_postamble
|
||||
|
||||
#define ar9331_1p2_soc_preamble ar9331_1p1_soc_preamble
|
||||
|
||||
#define ar9331_1p2_mac_core ar9331_1p1_mac_core
|
||||
|
||||
#define ar9331_common_wo_xlna_rx_gain_1p2 ar9331_common_wo_xlna_rx_gain_1p1
|
||||
|
||||
#define ar9331_common_rx_gain_1p2 ar9485_common_rx_gain_1_1
|
||||
static const u32 ar9331_common_rx_gain_1p2[][2] = {
|
||||
/* Addr allmodes */
|
||||
{0x0000a000, 0x00010000},
|
||||
{0x0000a004, 0x00030002},
|
||||
{0x0000a008, 0x00050004},
|
||||
{0x0000a00c, 0x00810080},
|
||||
{0x0000a010, 0x01800082},
|
||||
{0x0000a014, 0x01820181},
|
||||
{0x0000a018, 0x01840183},
|
||||
{0x0000a01c, 0x01880185},
|
||||
{0x0000a020, 0x018a0189},
|
||||
{0x0000a024, 0x02850284},
|
||||
{0x0000a028, 0x02890288},
|
||||
{0x0000a02c, 0x03850384},
|
||||
{0x0000a030, 0x03890388},
|
||||
{0x0000a034, 0x038b038a},
|
||||
{0x0000a038, 0x038d038c},
|
||||
{0x0000a03c, 0x03910390},
|
||||
{0x0000a040, 0x03930392},
|
||||
{0x0000a044, 0x03950394},
|
||||
{0x0000a048, 0x00000396},
|
||||
{0x0000a04c, 0x00000000},
|
||||
{0x0000a050, 0x00000000},
|
||||
{0x0000a054, 0x00000000},
|
||||
{0x0000a058, 0x00000000},
|
||||
{0x0000a05c, 0x00000000},
|
||||
{0x0000a060, 0x00000000},
|
||||
{0x0000a064, 0x00000000},
|
||||
{0x0000a068, 0x00000000},
|
||||
{0x0000a06c, 0x00000000},
|
||||
{0x0000a070, 0x00000000},
|
||||
{0x0000a074, 0x00000000},
|
||||
{0x0000a078, 0x00000000},
|
||||
{0x0000a07c, 0x00000000},
|
||||
{0x0000a080, 0x28282828},
|
||||
{0x0000a084, 0x28282828},
|
||||
{0x0000a088, 0x28282828},
|
||||
{0x0000a08c, 0x28282828},
|
||||
{0x0000a090, 0x28282828},
|
||||
{0x0000a094, 0x21212128},
|
||||
{0x0000a098, 0x171c1c1c},
|
||||
{0x0000a09c, 0x02020212},
|
||||
{0x0000a0a0, 0x00000202},
|
||||
{0x0000a0a4, 0x00000000},
|
||||
{0x0000a0a8, 0x00000000},
|
||||
{0x0000a0ac, 0x00000000},
|
||||
{0x0000a0b0, 0x00000000},
|
||||
{0x0000a0b4, 0x00000000},
|
||||
{0x0000a0b8, 0x00000000},
|
||||
{0x0000a0bc, 0x00000000},
|
||||
{0x0000a0c0, 0x001f0000},
|
||||
{0x0000a0c4, 0x111f1100},
|
||||
{0x0000a0c8, 0x111d111e},
|
||||
{0x0000a0cc, 0x111b111c},
|
||||
{0x0000a0d0, 0x22032204},
|
||||
{0x0000a0d4, 0x22012202},
|
||||
{0x0000a0d8, 0x221f2200},
|
||||
{0x0000a0dc, 0x221d221e},
|
||||
{0x0000a0e0, 0x33013302},
|
||||
{0x0000a0e4, 0x331f3300},
|
||||
{0x0000a0e8, 0x4402331e},
|
||||
{0x0000a0ec, 0x44004401},
|
||||
{0x0000a0f0, 0x441e441f},
|
||||
{0x0000a0f4, 0x55015502},
|
||||
{0x0000a0f8, 0x551f5500},
|
||||
{0x0000a0fc, 0x6602551e},
|
||||
{0x0000a100, 0x66006601},
|
||||
{0x0000a104, 0x661e661f},
|
||||
{0x0000a108, 0x7703661d},
|
||||
{0x0000a10c, 0x77017702},
|
||||
{0x0000a110, 0x00007700},
|
||||
{0x0000a114, 0x00000000},
|
||||
{0x0000a118, 0x00000000},
|
||||
{0x0000a11c, 0x00000000},
|
||||
{0x0000a120, 0x00000000},
|
||||
{0x0000a124, 0x00000000},
|
||||
{0x0000a128, 0x00000000},
|
||||
{0x0000a12c, 0x00000000},
|
||||
{0x0000a130, 0x00000000},
|
||||
{0x0000a134, 0x00000000},
|
||||
{0x0000a138, 0x00000000},
|
||||
{0x0000a13c, 0x00000000},
|
||||
{0x0000a140, 0x001f0000},
|
||||
{0x0000a144, 0x111f1100},
|
||||
{0x0000a148, 0x111d111e},
|
||||
{0x0000a14c, 0x111b111c},
|
||||
{0x0000a150, 0x22032204},
|
||||
{0x0000a154, 0x22012202},
|
||||
{0x0000a158, 0x221f2200},
|
||||
{0x0000a15c, 0x221d221e},
|
||||
{0x0000a160, 0x33013302},
|
||||
{0x0000a164, 0x331f3300},
|
||||
{0x0000a168, 0x4402331e},
|
||||
{0x0000a16c, 0x44004401},
|
||||
{0x0000a170, 0x441e441f},
|
||||
{0x0000a174, 0x55015502},
|
||||
{0x0000a178, 0x551f5500},
|
||||
{0x0000a17c, 0x6602551e},
|
||||
{0x0000a180, 0x66006601},
|
||||
{0x0000a184, 0x661e661f},
|
||||
{0x0000a188, 0x7703661d},
|
||||
{0x0000a18c, 0x77017702},
|
||||
{0x0000a190, 0x00007700},
|
||||
{0x0000a194, 0x00000000},
|
||||
{0x0000a198, 0x00000000},
|
||||
{0x0000a19c, 0x00000000},
|
||||
{0x0000a1a0, 0x00000000},
|
||||
{0x0000a1a4, 0x00000000},
|
||||
{0x0000a1a8, 0x00000000},
|
||||
{0x0000a1ac, 0x00000000},
|
||||
{0x0000a1b0, 0x00000000},
|
||||
{0x0000a1b4, 0x00000000},
|
||||
{0x0000a1b8, 0x00000000},
|
||||
{0x0000a1bc, 0x00000000},
|
||||
{0x0000a1c0, 0x00000000},
|
||||
{0x0000a1c4, 0x00000000},
|
||||
{0x0000a1c8, 0x00000000},
|
||||
{0x0000a1cc, 0x00000000},
|
||||
{0x0000a1d0, 0x00000000},
|
||||
{0x0000a1d4, 0x00000000},
|
||||
{0x0000a1d8, 0x00000000},
|
||||
{0x0000a1dc, 0x00000000},
|
||||
{0x0000a1e0, 0x00000000},
|
||||
{0x0000a1e4, 0x00000000},
|
||||
{0x0000a1e8, 0x00000000},
|
||||
{0x0000a1ec, 0x00000000},
|
||||
{0x0000a1f0, 0x00000396},
|
||||
{0x0000a1f4, 0x00000396},
|
||||
{0x0000a1f8, 0x00000396},
|
||||
{0x0000a1fc, 0x00000296},
|
||||
};
|
||||
|
||||
#endif /* INITVALS_9330_1P2_H */
|
||||
|
|
|
@ -30,6 +30,8 @@
|
|||
|
||||
#define ar9340_1p0_baseband_core_txfir_coeff_japan_2484 ar9300_2p2_baseband_core_txfir_coeff_japan_2484
|
||||
|
||||
#define ar9340_1p0_baseband_postamble_dfs_channel ar9300_2p2_baseband_postamble_dfs_channel
|
||||
|
||||
static const u32 ar9340_1p0_radio_postamble[][5] = {
|
||||
/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
|
||||
{0x000160ac, 0xa4646800, 0xa4646800, 0xa4646800, 0xa4646800},
|
||||
|
|
|
@ -20,6 +20,14 @@
|
|||
|
||||
/* AR9462 2.0 */
|
||||
|
||||
#define ar9462_2p0_mac_postamble ar9331_1p1_mac_postamble
|
||||
|
||||
#define ar9462_2p0_common_wo_xlna_rx_gain ar9300Common_wo_xlna_rx_gain_table_2p2
|
||||
|
||||
#define ar9462_2p0_common_5g_xlna_only_rxgain ar9462_2p0_common_mixed_rx_gain
|
||||
|
||||
#define ar9462_2p0_baseband_core_txfir_coeff_japan_2484 ar9300_2p2_baseband_core_txfir_coeff_japan_2484
|
||||
|
||||
static const u32 ar9462_2p0_modes_fast_clock[][3] = {
|
||||
/* Addr 5G_HT20 5G_HT40 */
|
||||
{0x00001030, 0x00000268, 0x000004d0},
|
||||
|
@ -366,273 +374,6 @@ static const u32 ar9462_2p0_radio_postamble_sys2ant[][5] = {
|
|||
{0x00016540, 0x10804008, 0x10804008, 0x50804008, 0x50804008},
|
||||
};
|
||||
|
||||
static const u32 ar9462_2p0_common_wo_xlna_rx_gain[][2] = {
|
||||
/* Addr allmodes */
|
||||
{0x0000a000, 0x00010000},
|
||||
{0x0000a004, 0x00030002},
|
||||
{0x0000a008, 0x00050004},
|
||||
{0x0000a00c, 0x00810080},
|
||||
{0x0000a010, 0x00830082},
|
||||
{0x0000a014, 0x01810180},
|
||||
{0x0000a018, 0x01830182},
|
||||
{0x0000a01c, 0x01850184},
|
||||
{0x0000a020, 0x01890188},
|
||||
{0x0000a024, 0x018b018a},
|
||||
{0x0000a028, 0x018d018c},
|
||||
{0x0000a02c, 0x03820190},
|
||||
{0x0000a030, 0x03840383},
|
||||
{0x0000a034, 0x03880385},
|
||||
{0x0000a038, 0x038a0389},
|
||||
{0x0000a03c, 0x038c038b},
|
||||
{0x0000a040, 0x0390038d},
|
||||
{0x0000a044, 0x03920391},
|
||||
{0x0000a048, 0x03940393},
|
||||
{0x0000a04c, 0x03960395},
|
||||
{0x0000a050, 0x00000000},
|
||||
{0x0000a054, 0x00000000},
|
||||
{0x0000a058, 0x00000000},
|
||||
{0x0000a05c, 0x00000000},
|
||||
{0x0000a060, 0x00000000},
|
||||
{0x0000a064, 0x00000000},
|
||||
{0x0000a068, 0x00000000},
|
||||
{0x0000a06c, 0x00000000},
|
||||
{0x0000a070, 0x00000000},
|
||||
{0x0000a074, 0x00000000},
|
||||
{0x0000a078, 0x00000000},
|
||||
{0x0000a07c, 0x00000000},
|
||||
{0x0000a080, 0x29292929},
|
||||
{0x0000a084, 0x29292929},
|
||||
{0x0000a088, 0x29292929},
|
||||
{0x0000a08c, 0x29292929},
|
||||
{0x0000a090, 0x22292929},
|
||||
{0x0000a094, 0x1d1d2222},
|
||||
{0x0000a098, 0x0c111117},
|
||||
{0x0000a09c, 0x00030303},
|
||||
{0x0000a0a0, 0x00000000},
|
||||
{0x0000a0a4, 0x00000000},
|
||||
{0x0000a0a8, 0x00000000},
|
||||
{0x0000a0ac, 0x00000000},
|
||||
{0x0000a0b0, 0x00000000},
|
||||
{0x0000a0b4, 0x00000000},
|
||||
{0x0000a0b8, 0x00000000},
|
||||
{0x0000a0bc, 0x00000000},
|
||||
{0x0000a0c0, 0x001f0000},
|
||||
{0x0000a0c4, 0x01000101},
|
||||
{0x0000a0c8, 0x011e011f},
|
||||
{0x0000a0cc, 0x011c011d},
|
||||
{0x0000a0d0, 0x02030204},
|
||||
{0x0000a0d4, 0x02010202},
|
||||
{0x0000a0d8, 0x021f0200},
|
||||
{0x0000a0dc, 0x0302021e},
|
||||
{0x0000a0e0, 0x03000301},
|
||||
{0x0000a0e4, 0x031e031f},
|
||||
{0x0000a0e8, 0x0402031d},
|
||||
{0x0000a0ec, 0x04000401},
|
||||
{0x0000a0f0, 0x041e041f},
|
||||
{0x0000a0f4, 0x0502041d},
|
||||
{0x0000a0f8, 0x05000501},
|
||||
{0x0000a0fc, 0x051e051f},
|
||||
{0x0000a100, 0x06010602},
|
||||
{0x0000a104, 0x061f0600},
|
||||
{0x0000a108, 0x061d061e},
|
||||
{0x0000a10c, 0x07020703},
|
||||
{0x0000a110, 0x07000701},
|
||||
{0x0000a114, 0x00000000},
|
||||
{0x0000a118, 0x00000000},
|
||||
{0x0000a11c, 0x00000000},
|
||||
{0x0000a120, 0x00000000},
|
||||
{0x0000a124, 0x00000000},
|
||||
{0x0000a128, 0x00000000},
|
||||
{0x0000a12c, 0x00000000},
|
||||
{0x0000a130, 0x00000000},
|
||||
{0x0000a134, 0x00000000},
|
||||
{0x0000a138, 0x00000000},
|
||||
{0x0000a13c, 0x00000000},
|
||||
{0x0000a140, 0x001f0000},
|
||||
{0x0000a144, 0x01000101},
|
||||
{0x0000a148, 0x011e011f},
|
||||
{0x0000a14c, 0x011c011d},
|
||||
{0x0000a150, 0x02030204},
|
||||
{0x0000a154, 0x02010202},
|
||||
{0x0000a158, 0x021f0200},
|
||||
{0x0000a15c, 0x0302021e},
|
||||
{0x0000a160, 0x03000301},
|
||||
{0x0000a164, 0x031e031f},
|
||||
{0x0000a168, 0x0402031d},
|
||||
{0x0000a16c, 0x04000401},
|
||||
{0x0000a170, 0x041e041f},
|
||||
{0x0000a174, 0x0502041d},
|
||||
{0x0000a178, 0x05000501},
|
||||
{0x0000a17c, 0x051e051f},
|
||||
{0x0000a180, 0x06010602},
|
||||
{0x0000a184, 0x061f0600},
|
||||
{0x0000a188, 0x061d061e},
|
||||
{0x0000a18c, 0x07020703},
|
||||
{0x0000a190, 0x07000701},
|
||||
{0x0000a194, 0x00000000},
|
||||
{0x0000a198, 0x00000000},
|
||||
{0x0000a19c, 0x00000000},
|
||||
{0x0000a1a0, 0x00000000},
|
||||
{0x0000a1a4, 0x00000000},
|
||||
{0x0000a1a8, 0x00000000},
|
||||
{0x0000a1ac, 0x00000000},
|
||||
{0x0000a1b0, 0x00000000},
|
||||
{0x0000a1b4, 0x00000000},
|
||||
{0x0000a1b8, 0x00000000},
|
||||
{0x0000a1bc, 0x00000000},
|
||||
{0x0000a1c0, 0x00000000},
|
||||
{0x0000a1c4, 0x00000000},
|
||||
{0x0000a1c8, 0x00000000},
|
||||
{0x0000a1cc, 0x00000000},
|
||||
{0x0000a1d0, 0x00000000},
|
||||
{0x0000a1d4, 0x00000000},
|
||||
{0x0000a1d8, 0x00000000},
|
||||
{0x0000a1dc, 0x00000000},
|
||||
{0x0000a1e0, 0x00000000},
|
||||
{0x0000a1e4, 0x00000000},
|
||||
{0x0000a1e8, 0x00000000},
|
||||
{0x0000a1ec, 0x00000000},
|
||||
{0x0000a1f0, 0x00000396},
|
||||
{0x0000a1f4, 0x00000396},
|
||||
{0x0000a1f8, 0x00000396},
|
||||
{0x0000a1fc, 0x00000196},
|
||||
{0x0000b000, 0x00010000},
|
||||
{0x0000b004, 0x00030002},
|
||||
{0x0000b008, 0x00050004},
|
||||
{0x0000b00c, 0x00810080},
|
||||
{0x0000b010, 0x00830082},
|
||||
{0x0000b014, 0x01810180},
|
||||
{0x0000b018, 0x01830182},
|
||||
{0x0000b01c, 0x01850184},
|
||||
{0x0000b020, 0x02810280},
|
||||
{0x0000b024, 0x02830282},
|
||||
{0x0000b028, 0x02850284},
|
||||
{0x0000b02c, 0x02890288},
|
||||
{0x0000b030, 0x028b028a},
|
||||
{0x0000b034, 0x0388028c},
|
||||
{0x0000b038, 0x038a0389},
|
||||
{0x0000b03c, 0x038c038b},
|
||||
{0x0000b040, 0x0390038d},
|
||||
{0x0000b044, 0x03920391},
|
||||
{0x0000b048, 0x03940393},
|
||||
{0x0000b04c, 0x03960395},
|
||||
{0x0000b050, 0x00000000},
|
||||
{0x0000b054, 0x00000000},
|
||||
{0x0000b058, 0x00000000},
|
||||
{0x0000b05c, 0x00000000},
|
||||
{0x0000b060, 0x00000000},
|
||||
{0x0000b064, 0x00000000},
|
||||
{0x0000b068, 0x00000000},
|
||||
{0x0000b06c, 0x00000000},
|
||||
{0x0000b070, 0x00000000},
|
||||
{0x0000b074, 0x00000000},
|
||||
{0x0000b078, 0x00000000},
|
||||
{0x0000b07c, 0x00000000},
|
||||
{0x0000b080, 0x32323232},
|
||||
{0x0000b084, 0x2f2f3232},
|
||||
{0x0000b088, 0x23282a2d},
|
||||
{0x0000b08c, 0x1c1e2123},
|
||||
{0x0000b090, 0x14171919},
|
||||
{0x0000b094, 0x0e0e1214},
|
||||
{0x0000b098, 0x03050707},
|
||||
{0x0000b09c, 0x00030303},
|
||||
{0x0000b0a0, 0x00000000},
|
||||
{0x0000b0a4, 0x00000000},
|
||||
{0x0000b0a8, 0x00000000},
|
||||
{0x0000b0ac, 0x00000000},
|
||||
{0x0000b0b0, 0x00000000},
|
||||
{0x0000b0b4, 0x00000000},
|
||||
{0x0000b0b8, 0x00000000},
|
||||
{0x0000b0bc, 0x00000000},
|
||||
{0x0000b0c0, 0x003f0020},
|
||||
{0x0000b0c4, 0x00400041},
|
||||
{0x0000b0c8, 0x0140005f},
|
||||
{0x0000b0cc, 0x0160015f},
|
||||
{0x0000b0d0, 0x017e017f},
|
||||
{0x0000b0d4, 0x02410242},
|
||||
{0x0000b0d8, 0x025f0240},
|
||||
{0x0000b0dc, 0x027f0260},
|
||||
{0x0000b0e0, 0x0341027e},
|
||||
{0x0000b0e4, 0x035f0340},
|
||||
{0x0000b0e8, 0x037f0360},
|
||||
{0x0000b0ec, 0x04400441},
|
||||
{0x0000b0f0, 0x0460045f},
|
||||
{0x0000b0f4, 0x0541047f},
|
||||
{0x0000b0f8, 0x055f0540},
|
||||
{0x0000b0fc, 0x057f0560},
|
||||
{0x0000b100, 0x06400641},
|
||||
{0x0000b104, 0x0660065f},
|
||||
{0x0000b108, 0x067e067f},
|
||||
{0x0000b10c, 0x07410742},
|
||||
{0x0000b110, 0x075f0740},
|
||||
{0x0000b114, 0x077f0760},
|
||||
{0x0000b118, 0x07800781},
|
||||
{0x0000b11c, 0x07a0079f},
|
||||
{0x0000b120, 0x07c107bf},
|
||||
{0x0000b124, 0x000007c0},
|
||||
{0x0000b128, 0x00000000},
|
||||
{0x0000b12c, 0x00000000},
|
||||
{0x0000b130, 0x00000000},
|
||||
{0x0000b134, 0x00000000},
|
||||
{0x0000b138, 0x00000000},
|
||||
{0x0000b13c, 0x00000000},
|
||||
{0x0000b140, 0x003f0020},
|
||||
{0x0000b144, 0x00400041},
|
||||
{0x0000b148, 0x0140005f},
|
||||
{0x0000b14c, 0x0160015f},
|
||||
{0x0000b150, 0x017e017f},
|
||||
{0x0000b154, 0x02410242},
|
||||
{0x0000b158, 0x025f0240},
|
||||
{0x0000b15c, 0x027f0260},
|
||||
{0x0000b160, 0x0341027e},
|
||||
{0x0000b164, 0x035f0340},
|
||||
{0x0000b168, 0x037f0360},
|
||||
{0x0000b16c, 0x04400441},
|
||||
{0x0000b170, 0x0460045f},
|
||||
{0x0000b174, 0x0541047f},
|
||||
{0x0000b178, 0x055f0540},
|
||||
{0x0000b17c, 0x057f0560},
|
||||
{0x0000b180, 0x06400641},
|
||||
{0x0000b184, 0x0660065f},
|
||||
{0x0000b188, 0x067e067f},
|
||||
{0x0000b18c, 0x07410742},
|
||||
{0x0000b190, 0x075f0740},
|
||||
{0x0000b194, 0x077f0760},
|
||||
{0x0000b198, 0x07800781},
|
||||
{0x0000b19c, 0x07a0079f},
|
||||
{0x0000b1a0, 0x07c107bf},
|
||||
{0x0000b1a4, 0x000007c0},
|
||||
{0x0000b1a8, 0x00000000},
|
||||
{0x0000b1ac, 0x00000000},
|
||||
{0x0000b1b0, 0x00000000},
|
||||
{0x0000b1b4, 0x00000000},
|
||||
{0x0000b1b8, 0x00000000},
|
||||
{0x0000b1bc, 0x00000000},
|
||||
{0x0000b1c0, 0x00000000},
|
||||
{0x0000b1c4, 0x00000000},
|
||||
{0x0000b1c8, 0x00000000},
|
||||
{0x0000b1cc, 0x00000000},
|
||||
{0x0000b1d0, 0x00000000},
|
||||
{0x0000b1d4, 0x00000000},
|
||||
{0x0000b1d8, 0x00000000},
|
||||
{0x0000b1dc, 0x00000000},
|
||||
{0x0000b1e0, 0x00000000},
|
||||
{0x0000b1e4, 0x00000000},
|
||||
{0x0000b1e8, 0x00000000},
|
||||
{0x0000b1ec, 0x00000000},
|
||||
{0x0000b1f0, 0x00000396},
|
||||
{0x0000b1f4, 0x00000396},
|
||||
{0x0000b1f8, 0x00000396},
|
||||
{0x0000b1fc, 0x00000196},
|
||||
};
|
||||
|
||||
static const u32 ar9462_2p0_baseband_core_txfir_coeff_japan_2484[][2] = {
|
||||
/* Addr allmodes */
|
||||
{0x0000a398, 0x00000000},
|
||||
{0x0000a39c, 0x6f7f0301},
|
||||
{0x0000a3a0, 0xca9228ee},
|
||||
};
|
||||
|
||||
static const u32 ar9462_2p0_modes_low_ob_db_tx_gain[][5] = {
|
||||
/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
|
||||
{0x000098bc, 0x00000002, 0x00000002, 0x00000002, 0x00000002},
|
||||
|
@ -1226,18 +967,6 @@ static const u32 ar9462_2p0_mac_core[][2] = {
|
|||
{0x000083d0, 0x000301ff},
|
||||
};
|
||||
|
||||
static const u32 ar9462_2p0_mac_postamble[][5] = {
|
||||
/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
|
||||
{0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160},
|
||||
{0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c},
|
||||
{0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38},
|
||||
{0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00},
|
||||
{0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b},
|
||||
{0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810},
|
||||
{0x000081d0, 0x00003210, 0x00003210, 0x0000320a, 0x0000320a},
|
||||
{0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440},
|
||||
};
|
||||
|
||||
static const u32 ar9462_2p0_common_mixed_rx_gain[][2] = {
|
||||
/* Addr allmodes */
|
||||
{0x0000a000, 0x00010000},
|
||||
|
@ -1503,266 +1232,6 @@ static const u32 ar9462_2p0_baseband_postamble_5g_xlna[][5] = {
|
|||
{0x00009e3c, 0xcf946220, 0xcf946220, 0xcfd5c782, 0xcfd5c282},
|
||||
};
|
||||
|
||||
static const u32 ar9462_2p0_common_5g_xlna_only_rxgain[][2] = {
|
||||
/* Addr allmodes */
|
||||
{0x0000a000, 0x00010000},
|
||||
{0x0000a004, 0x00030002},
|
||||
{0x0000a008, 0x00050004},
|
||||
{0x0000a00c, 0x00810080},
|
||||
{0x0000a010, 0x00830082},
|
||||
{0x0000a014, 0x01810180},
|
||||
{0x0000a018, 0x01830182},
|
||||
{0x0000a01c, 0x01850184},
|
||||
{0x0000a020, 0x01890188},
|
||||
{0x0000a024, 0x018b018a},
|
||||
{0x0000a028, 0x018d018c},
|
||||
{0x0000a02c, 0x03820190},
|
||||
{0x0000a030, 0x03840383},
|
||||
{0x0000a034, 0x03880385},
|
||||
{0x0000a038, 0x038a0389},
|
||||
{0x0000a03c, 0x038c038b},
|
||||
{0x0000a040, 0x0390038d},
|
||||
{0x0000a044, 0x03920391},
|
||||
{0x0000a048, 0x03940393},
|
||||
{0x0000a04c, 0x03960395},
|
||||
{0x0000a050, 0x00000000},
|
||||
{0x0000a054, 0x00000000},
|
||||
{0x0000a058, 0x00000000},
|
||||
{0x0000a05c, 0x00000000},
|
||||
{0x0000a060, 0x00000000},
|
||||
{0x0000a064, 0x00000000},
|
||||
{0x0000a068, 0x00000000},
|
||||
{0x0000a06c, 0x00000000},
|
||||
{0x0000a070, 0x00000000},
|
||||
{0x0000a074, 0x00000000},
|
||||
{0x0000a078, 0x00000000},
|
||||
{0x0000a07c, 0x00000000},
|
||||
{0x0000a080, 0x29292929},
|
||||
{0x0000a084, 0x29292929},
|
||||
{0x0000a088, 0x29292929},
|
||||
{0x0000a08c, 0x29292929},
|
||||
{0x0000a090, 0x22292929},
|
||||
{0x0000a094, 0x1d1d2222},
|
||||
{0x0000a098, 0x0c111117},
|
||||
{0x0000a09c, 0x00030303},
|
||||
{0x0000a0a0, 0x00000000},
|
||||
{0x0000a0a4, 0x00000000},
|
||||
{0x0000a0a8, 0x00000000},
|
||||
{0x0000a0ac, 0x00000000},
|
||||
{0x0000a0b0, 0x00000000},
|
||||
{0x0000a0b4, 0x00000000},
|
||||
{0x0000a0b8, 0x00000000},
|
||||
{0x0000a0bc, 0x00000000},
|
||||
{0x0000a0c0, 0x001f0000},
|
||||
{0x0000a0c4, 0x01000101},
|
||||
{0x0000a0c8, 0x011e011f},
|
||||
{0x0000a0cc, 0x011c011d},
|
||||
{0x0000a0d0, 0x02030204},
|
||||
{0x0000a0d4, 0x02010202},
|
||||
{0x0000a0d8, 0x021f0200},
|
||||
{0x0000a0dc, 0x0302021e},
|
||||
{0x0000a0e0, 0x03000301},
|
||||
{0x0000a0e4, 0x031e031f},
|
||||
{0x0000a0e8, 0x0402031d},
|
||||
{0x0000a0ec, 0x04000401},
|
||||
{0x0000a0f0, 0x041e041f},
|
||||
{0x0000a0f4, 0x0502041d},
|
||||
{0x0000a0f8, 0x05000501},
|
||||
{0x0000a0fc, 0x051e051f},
|
||||
{0x0000a100, 0x06010602},
|
||||
{0x0000a104, 0x061f0600},
|
||||
{0x0000a108, 0x061d061e},
|
||||
{0x0000a10c, 0x07020703},
|
||||
{0x0000a110, 0x07000701},
|
||||
{0x0000a114, 0x00000000},
|
||||
{0x0000a118, 0x00000000},
|
||||
{0x0000a11c, 0x00000000},
|
||||
{0x0000a120, 0x00000000},
|
||||
{0x0000a124, 0x00000000},
|
||||
{0x0000a128, 0x00000000},
|
||||
{0x0000a12c, 0x00000000},
|
||||
{0x0000a130, 0x00000000},
|
||||
{0x0000a134, 0x00000000},
|
||||
{0x0000a138, 0x00000000},
|
||||
{0x0000a13c, 0x00000000},
|
||||
{0x0000a140, 0x001f0000},
|
||||
{0x0000a144, 0x01000101},
|
||||
{0x0000a148, 0x011e011f},
|
||||
{0x0000a14c, 0x011c011d},
|
||||
{0x0000a150, 0x02030204},
|
||||
{0x0000a154, 0x02010202},
|
||||
{0x0000a158, 0x021f0200},
|
||||
{0x0000a15c, 0x0302021e},
|
||||
{0x0000a160, 0x03000301},
|
||||
{0x0000a164, 0x031e031f},
|
||||
{0x0000a168, 0x0402031d},
|
||||
{0x0000a16c, 0x04000401},
|
||||
{0x0000a170, 0x041e041f},
|
||||
{0x0000a174, 0x0502041d},
|
||||
{0x0000a178, 0x05000501},
|
||||
{0x0000a17c, 0x051e051f},
|
||||
{0x0000a180, 0x06010602},
|
||||
{0x0000a184, 0x061f0600},
|
||||
{0x0000a188, 0x061d061e},
|
||||
{0x0000a18c, 0x07020703},
|
||||
{0x0000a190, 0x07000701},
|
||||
{0x0000a194, 0x00000000},
|
||||
{0x0000a198, 0x00000000},
|
||||
{0x0000a19c, 0x00000000},
|
||||
{0x0000a1a0, 0x00000000},
|
||||
{0x0000a1a4, 0x00000000},
|
||||
{0x0000a1a8, 0x00000000},
|
||||
{0x0000a1ac, 0x00000000},
|
||||
{0x0000a1b0, 0x00000000},
|
||||
{0x0000a1b4, 0x00000000},
|
||||
{0x0000a1b8, 0x00000000},
|
||||
{0x0000a1bc, 0x00000000},
|
||||
{0x0000a1c0, 0x00000000},
|
||||
{0x0000a1c4, 0x00000000},
|
||||
{0x0000a1c8, 0x00000000},
|
||||
{0x0000a1cc, 0x00000000},
|
||||
{0x0000a1d0, 0x00000000},
|
||||
{0x0000a1d4, 0x00000000},
|
||||
{0x0000a1d8, 0x00000000},
|
||||
{0x0000a1dc, 0x00000000},
|
||||
{0x0000a1e0, 0x00000000},
|
||||
{0x0000a1e4, 0x00000000},
|
||||
{0x0000a1e8, 0x00000000},
|
||||
{0x0000a1ec, 0x00000000},
|
||||
{0x0000a1f0, 0x00000396},
|
||||
{0x0000a1f4, 0x00000396},
|
||||
{0x0000a1f8, 0x00000396},
|
||||
{0x0000a1fc, 0x00000196},
|
||||
{0x0000b000, 0x00010000},
|
||||
{0x0000b004, 0x00030002},
|
||||
{0x0000b008, 0x00050004},
|
||||
{0x0000b00c, 0x00810080},
|
||||
{0x0000b010, 0x00830082},
|
||||
{0x0000b014, 0x01810180},
|
||||
{0x0000b018, 0x01830182},
|
||||
{0x0000b01c, 0x01850184},
|
||||
{0x0000b020, 0x02810280},
|
||||
{0x0000b024, 0x02830282},
|
||||
{0x0000b028, 0x02850284},
|
||||
{0x0000b02c, 0x02890288},
|
||||
{0x0000b030, 0x028b028a},
|
||||
{0x0000b034, 0x0388028c},
|
||||
{0x0000b038, 0x038a0389},
|
||||
{0x0000b03c, 0x038c038b},
|
||||
{0x0000b040, 0x0390038d},
|
||||
{0x0000b044, 0x03920391},
|
||||
{0x0000b048, 0x03940393},
|
||||
{0x0000b04c, 0x03960395},
|
||||
{0x0000b050, 0x00000000},
|
||||
{0x0000b054, 0x00000000},
|
||||
{0x0000b058, 0x00000000},
|
||||
{0x0000b05c, 0x00000000},
|
||||
{0x0000b060, 0x00000000},
|
||||
{0x0000b064, 0x00000000},
|
||||
{0x0000b068, 0x00000000},
|
||||
{0x0000b06c, 0x00000000},
|
||||
{0x0000b070, 0x00000000},
|
||||
{0x0000b074, 0x00000000},
|
||||
{0x0000b078, 0x00000000},
|
||||
{0x0000b07c, 0x00000000},
|
||||
{0x0000b080, 0x2a2d2f32},
|
||||
{0x0000b084, 0x21232328},
|
||||
{0x0000b088, 0x19191c1e},
|
||||
{0x0000b08c, 0x12141417},
|
||||
{0x0000b090, 0x07070e0e},
|
||||
{0x0000b094, 0x03030305},
|
||||
{0x0000b098, 0x00000003},
|
||||
{0x0000b09c, 0x00000000},
|
||||
{0x0000b0a0, 0x00000000},
|
||||
{0x0000b0a4, 0x00000000},
|
||||
{0x0000b0a8, 0x00000000},
|
||||
{0x0000b0ac, 0x00000000},
|
||||
{0x0000b0b0, 0x00000000},
|
||||
{0x0000b0b4, 0x00000000},
|
||||
{0x0000b0b8, 0x00000000},
|
||||
{0x0000b0bc, 0x00000000},
|
||||
{0x0000b0c0, 0x003f0020},
|
||||
{0x0000b0c4, 0x00400041},
|
||||
{0x0000b0c8, 0x0140005f},
|
||||
{0x0000b0cc, 0x0160015f},
|
||||
{0x0000b0d0, 0x017e017f},
|
||||
{0x0000b0d4, 0x02410242},
|
||||
{0x0000b0d8, 0x025f0240},
|
||||
{0x0000b0dc, 0x027f0260},
|
||||
{0x0000b0e0, 0x0341027e},
|
||||
{0x0000b0e4, 0x035f0340},
|
||||
{0x0000b0e8, 0x037f0360},
|
||||
{0x0000b0ec, 0x04400441},
|
||||
{0x0000b0f0, 0x0460045f},
|
||||
{0x0000b0f4, 0x0541047f},
|
||||
{0x0000b0f8, 0x055f0540},
|
||||
{0x0000b0fc, 0x057f0560},
|
||||
{0x0000b100, 0x06400641},
|
||||
{0x0000b104, 0x0660065f},
|
||||
{0x0000b108, 0x067e067f},
|
||||
{0x0000b10c, 0x07410742},
|
||||
{0x0000b110, 0x075f0740},
|
||||
{0x0000b114, 0x077f0760},
|
||||
{0x0000b118, 0x07800781},
|
||||
{0x0000b11c, 0x07a0079f},
|
||||
{0x0000b120, 0x07c107bf},
|
||||
{0x0000b124, 0x000007c0},
|
||||
{0x0000b128, 0x00000000},
|
||||
{0x0000b12c, 0x00000000},
|
||||
{0x0000b130, 0x00000000},
|
||||
{0x0000b134, 0x00000000},
|
||||
{0x0000b138, 0x00000000},
|
||||
{0x0000b13c, 0x00000000},
|
||||
{0x0000b140, 0x003f0020},
|
||||
{0x0000b144, 0x00400041},
|
||||
{0x0000b148, 0x0140005f},
|
||||
{0x0000b14c, 0x0160015f},
|
||||
{0x0000b150, 0x017e017f},
|
||||
{0x0000b154, 0x02410242},
|
||||
{0x0000b158, 0x025f0240},
|
||||
{0x0000b15c, 0x027f0260},
|
||||
{0x0000b160, 0x0341027e},
|
||||
{0x0000b164, 0x035f0340},
|
||||
{0x0000b168, 0x037f0360},
|
||||
{0x0000b16c, 0x04400441},
|
||||
{0x0000b170, 0x0460045f},
|
||||
{0x0000b174, 0x0541047f},
|
||||
{0x0000b178, 0x055f0540},
|
||||
{0x0000b17c, 0x057f0560},
|
||||
{0x0000b180, 0x06400641},
|
||||
{0x0000b184, 0x0660065f},
|
||||
{0x0000b188, 0x067e067f},
|
||||
{0x0000b18c, 0x07410742},
|
||||
{0x0000b190, 0x075f0740},
|
||||
{0x0000b194, 0x077f0760},
|
||||
{0x0000b198, 0x07800781},
|
||||
{0x0000b19c, 0x07a0079f},
|
||||
{0x0000b1a0, 0x07c107bf},
|
||||
{0x0000b1a4, 0x000007c0},
|
||||
{0x0000b1a8, 0x00000000},
|
||||
{0x0000b1ac, 0x00000000},
|
||||
{0x0000b1b0, 0x00000000},
|
||||
{0x0000b1b4, 0x00000000},
|
||||
{0x0000b1b8, 0x00000000},
|
||||
{0x0000b1bc, 0x00000000},
|
||||
{0x0000b1c0, 0x00000000},
|
||||
{0x0000b1c4, 0x00000000},
|
||||
{0x0000b1c8, 0x00000000},
|
||||
{0x0000b1cc, 0x00000000},
|
||||
{0x0000b1d0, 0x00000000},
|
||||
{0x0000b1d4, 0x00000000},
|
||||
{0x0000b1d8, 0x00000000},
|
||||
{0x0000b1dc, 0x00000000},
|
||||
{0x0000b1e0, 0x00000000},
|
||||
{0x0000b1e4, 0x00000000},
|
||||
{0x0000b1e8, 0x00000000},
|
||||
{0x0000b1ec, 0x00000000},
|
||||
{0x0000b1f0, 0x00000396},
|
||||
{0x0000b1f4, 0x00000396},
|
||||
{0x0000b1f8, 0x00000396},
|
||||
{0x0000b1fc, 0x00000196},
|
||||
};
|
||||
|
||||
static const u32 ar9462_2p0_baseband_core_mix_rxgain[][2] = {
|
||||
/* Addr allmodes */
|
||||
{0x00009fd0, 0x0a2d6b93},
|
||||
|
|
|
@ -20,17 +20,11 @@
|
|||
|
||||
/* AR9485 1.1 */
|
||||
|
||||
static const u32 ar9485_1_1_mac_postamble[][5] = {
|
||||
/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
|
||||
{0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160},
|
||||
{0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c},
|
||||
{0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38},
|
||||
{0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00},
|
||||
{0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b},
|
||||
{0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810},
|
||||
{0x000081d0, 0x00003210, 0x00003210, 0x0000320a, 0x0000320a},
|
||||
{0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440},
|
||||
};
|
||||
#define ar9485_modes_lowest_ob_db_tx_gain_1_1 ar9485Modes_low_ob_db_tx_gain_1_1
|
||||
|
||||
#define ar9485_1_1_mac_postamble ar9331_1p1_mac_postamble
|
||||
|
||||
#define ar9485_1_1_baseband_core_txfir_coeff_japan_2484 ar9300_2p2_baseband_core_txfir_coeff_japan_2484
|
||||
|
||||
static const u32 ar9485Common_wo_xlna_rx_gain_1_1[][2] = {
|
||||
/* Addr allmodes */
|
||||
|
@ -546,100 +540,6 @@ static const u32 ar9485Modes_low_ob_db_tx_gain_1_1[][5] = {
|
|||
{0x00016048, 0x6c924260, 0x6c924260, 0x6c924260, 0x6c924260},
|
||||
};
|
||||
|
||||
static const u32 ar9485_modes_lowest_ob_db_tx_gain_1_1[][5] = {
|
||||
/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
|
||||
{0x000098bc, 0x00000002, 0x00000002, 0x00000002, 0x00000002},
|
||||
{0x0000a2d8, 0xf999a83a, 0xf999a83a, 0x7999a83a, 0x7999a83a},
|
||||
{0x0000a2dc, 0x00000000, 0x00000000, 0xfe2d3552, 0xfe2d3552},
|
||||
{0x0000a2e0, 0x00000000, 0x00000000, 0xfe2d3552, 0xfe2d3552},
|
||||
{0x0000a2e4, 0x00000000, 0x00000000, 0xfe2d3552, 0xfe2d3552},
|
||||
{0x0000a2e8, 0x00000000, 0x00000000, 0xfe2d3552, 0xfe2d3552},
|
||||
{0x0000a410, 0x000050d9, 0x000050d9, 0x000050d8, 0x000050d8},
|
||||
{0x0000a458, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
|
||||
{0x0000a500, 0x00022200, 0x00022200, 0x00000000, 0x00000000},
|
||||
{0x0000a504, 0x05062002, 0x05062002, 0x04000002, 0x04000002},
|
||||
{0x0000a508, 0x0c002e00, 0x0c002e00, 0x08000004, 0x08000004},
|
||||
{0x0000a50c, 0x11062202, 0x11062202, 0x0d000200, 0x0d000200},
|
||||
{0x0000a510, 0x17022e00, 0x17022e00, 0x11000202, 0x11000202},
|
||||
{0x0000a514, 0x1d000ec2, 0x1d000ec2, 0x15000400, 0x15000400},
|
||||
{0x0000a518, 0x25020ec0, 0x25020ec0, 0x19000402, 0x19000402},
|
||||
{0x0000a51c, 0x2b020ec3, 0x2b020ec3, 0x1d000404, 0x1d000404},
|
||||
{0x0000a520, 0x2f001f04, 0x2f001f04, 0x21000603, 0x21000603},
|
||||
{0x0000a524, 0x35001fc4, 0x35001fc4, 0x25000605, 0x25000605},
|
||||
{0x0000a528, 0x3c022f04, 0x3c022f04, 0x2a000a03, 0x2a000a03},
|
||||
{0x0000a52c, 0x41023e85, 0x41023e85, 0x2c000a04, 0x2c000a04},
|
||||
{0x0000a530, 0x48023ec6, 0x48023ec6, 0x34000e20, 0x34000e20},
|
||||
{0x0000a534, 0x4d023f01, 0x4d023f01, 0x35000e21, 0x35000e21},
|
||||
{0x0000a538, 0x53023f4b, 0x53023f4b, 0x43000e62, 0x43000e62},
|
||||
{0x0000a53c, 0x5a027f09, 0x5a027f09, 0x45000e63, 0x45000e63},
|
||||
{0x0000a540, 0x5f027fc9, 0x5f027fc9, 0x49000e65, 0x49000e65},
|
||||
{0x0000a544, 0x6502feca, 0x6502feca, 0x4b000e66, 0x4b000e66},
|
||||
{0x0000a548, 0x6b02ff4a, 0x6b02ff4a, 0x4d001645, 0x4d001645},
|
||||
{0x0000a54c, 0x7203feca, 0x7203feca, 0x51001865, 0x51001865},
|
||||
{0x0000a550, 0x7703ff0b, 0x7703ff0b, 0x55001a86, 0x55001a86},
|
||||
{0x0000a554, 0x7d06ffcb, 0x7d06ffcb, 0x57001ce9, 0x57001ce9},
|
||||
{0x0000a558, 0x8407ff0b, 0x8407ff0b, 0x5a001ceb, 0x5a001ceb},
|
||||
{0x0000a55c, 0x8907ffcb, 0x8907ffcb, 0x5e001eeb, 0x5e001eeb},
|
||||
{0x0000a560, 0x900fff0b, 0x900fff0b, 0x5e001eeb, 0x5e001eeb},
|
||||
{0x0000a564, 0x960fffcb, 0x960fffcb, 0x5e001eeb, 0x5e001eeb},
|
||||
{0x0000a568, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
|
||||
{0x0000a56c, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
|
||||
{0x0000a570, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
|
||||
{0x0000a574, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
|
||||
{0x0000a578, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
|
||||
{0x0000a57c, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
|
||||
{0x0000a580, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
|
||||
{0x0000a584, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
|
||||
{0x0000a588, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
|
||||
{0x0000a58c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
|
||||
{0x0000a590, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
|
||||
{0x0000a594, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
|
||||
{0x0000a598, 0x00000000, 0x00000000, 0x01404501, 0x01404501},
|
||||
{0x0000a59c, 0x00000000, 0x00000000, 0x02808a02, 0x02808a02},
|
||||
{0x0000a5a0, 0x00000000, 0x00000000, 0x02808a02, 0x02808a02},
|
||||
{0x0000a5a4, 0x00000000, 0x00000000, 0x02808803, 0x02808803},
|
||||
{0x0000a5a8, 0x00000000, 0x00000000, 0x04c14b04, 0x04c14b04},
|
||||
{0x0000a5ac, 0x00000000, 0x00000000, 0x04c15305, 0x04c15305},
|
||||
{0x0000a5b0, 0x00000000, 0x00000000, 0x04c15305, 0x04c15305},
|
||||
{0x0000a5b4, 0x00000000, 0x00000000, 0x04c15305, 0x04c15305},
|
||||
{0x0000a5b8, 0x00000000, 0x00000000, 0x04c15305, 0x04c15305},
|
||||
{0x0000a5bc, 0x00000000, 0x00000000, 0x04c15305, 0x04c15305},
|
||||
{0x0000b500, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
|
||||
{0x0000b504, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
|
||||
{0x0000b508, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
|
||||
{0x0000b50c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
|
||||
{0x0000b510, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
|
||||
{0x0000b514, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
|
||||
{0x0000b518, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
|
||||
{0x0000b51c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
|
||||
{0x0000b520, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
|
||||
{0x0000b524, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
|
||||
{0x0000b528, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
|
||||
{0x0000b52c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
|
||||
{0x0000b530, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
|
||||
{0x0000b534, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
|
||||
{0x0000b538, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
|
||||
{0x0000b53c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
|
||||
{0x0000b540, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
|
||||
{0x0000b544, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
|
||||
{0x0000b548, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
|
||||
{0x0000b54c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
|
||||
{0x0000b550, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
|
||||
{0x0000b554, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
|
||||
{0x0000b558, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
|
||||
{0x0000b55c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
|
||||
{0x0000b560, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
|
||||
{0x0000b564, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
|
||||
{0x0000b568, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
|
||||
{0x0000b56c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
|
||||
{0x0000b570, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
|
||||
{0x0000b574, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
|
||||
{0x0000b578, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
|
||||
{0x0000b57c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
|
||||
{0x00016044, 0x05d6b2db, 0x05d6b2db, 0x05d6b2db, 0x05d6b2db},
|
||||
{0x00016048, 0x6c924260, 0x6c924260, 0x6c924260, 0x6c924260},
|
||||
};
|
||||
|
||||
static const u32 ar9485Modes_green_spur_ob_db_tx_gain_1_1[][5] = {
|
||||
/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
|
||||
{0x000098bc, 0x00000003, 0x00000003, 0x00000003, 0x00000003},
|
||||
|
@ -1323,13 +1223,6 @@ static const u32 ar9485_1_1_mac_core[][2] = {
|
|||
{0x000083d0, 0x000301ff},
|
||||
};
|
||||
|
||||
static const u32 ar9485_1_1_baseband_core_txfir_coeff_japan_2484[][2] = {
|
||||
/* Addr allmodes */
|
||||
{0x0000a398, 0x00000000},
|
||||
{0x0000a39c, 0x6f7f0301},
|
||||
{0x0000a3a0, 0xca9228ee},
|
||||
};
|
||||
|
||||
static const u32 ar9485_1_1_pcie_phy_clkreq_disable_L1[][2] = {
|
||||
/* Addr allmodes */
|
||||
{0x00018c00, 0x18013e5e},
|
||||
|
|
|
@ -20,6 +20,14 @@
|
|||
|
||||
/* AR955X 1.0 */
|
||||
|
||||
#define ar955x_1p0_soc_postamble ar9300_2p2_soc_postamble
|
||||
|
||||
#define ar955x_1p0_common_rx_gain_table ar9300Common_rx_gain_table_2p2
|
||||
|
||||
#define ar955x_1p0_common_wo_xlna_rx_gain_table ar9300Common_wo_xlna_rx_gain_table_2p2
|
||||
|
||||
#define ar955x_1p0_baseband_core_txfir_coeff_japan_2484 ar9300_2p2_baseband_core_txfir_coeff_japan_2484
|
||||
|
||||
static const u32 ar955x_1p0_radio_postamble[][5] = {
|
||||
/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
|
||||
{0x00016098, 0xd2dd5554, 0xd2dd5554, 0xd28b3330, 0xd28b3330},
|
||||
|
@ -37,13 +45,6 @@ static const u32 ar955x_1p0_radio_postamble[][5] = {
|
|||
{0x00016940, 0x10804008, 0x10804008, 0x10804008, 0x10804008},
|
||||
};
|
||||
|
||||
static const u32 ar955x_1p0_baseband_core_txfir_coeff_japan_2484[][2] = {
|
||||
/* Addr allmodes */
|
||||
{0x0000a398, 0x00000000},
|
||||
{0x0000a39c, 0x6f7f0301},
|
||||
{0x0000a3a0, 0xca9228ee},
|
||||
};
|
||||
|
||||
static const u32 ar955x_1p0_baseband_postamble[][5] = {
|
||||
/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
|
||||
{0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8011, 0xd00a8011},
|
||||
|
@ -473,266 +474,6 @@ static const u32 ar955x_1p0_mac_core[][2] = {
|
|||
{0x000083d0, 0x8c7901ff},
|
||||
};
|
||||
|
||||
static const u32 ar955x_1p0_common_rx_gain_table[][2] = {
|
||||
/* Addr allmodes */
|
||||
{0x0000a000, 0x00010000},
|
||||
{0x0000a004, 0x00030002},
|
||||
{0x0000a008, 0x00050004},
|
||||
{0x0000a00c, 0x00810080},
|
||||
{0x0000a010, 0x00830082},
|
||||
{0x0000a014, 0x01810180},
|
||||
{0x0000a018, 0x01830182},
|
||||
{0x0000a01c, 0x01850184},
|
||||
{0x0000a020, 0x01890188},
|
||||
{0x0000a024, 0x018b018a},
|
||||
{0x0000a028, 0x018d018c},
|
||||
{0x0000a02c, 0x01910190},
|
||||
{0x0000a030, 0x01930192},
|
||||
{0x0000a034, 0x01950194},
|
||||
{0x0000a038, 0x038a0196},
|
||||
{0x0000a03c, 0x038c038b},
|
||||
{0x0000a040, 0x0390038d},
|
||||
{0x0000a044, 0x03920391},
|
||||
{0x0000a048, 0x03940393},
|
||||
{0x0000a04c, 0x03960395},
|
||||
{0x0000a050, 0x00000000},
|
||||
{0x0000a054, 0x00000000},
|
||||
{0x0000a058, 0x00000000},
|
||||
{0x0000a05c, 0x00000000},
|
||||
{0x0000a060, 0x00000000},
|
||||
{0x0000a064, 0x00000000},
|
||||
{0x0000a068, 0x00000000},
|
||||
{0x0000a06c, 0x00000000},
|
||||
{0x0000a070, 0x00000000},
|
||||
{0x0000a074, 0x00000000},
|
||||
{0x0000a078, 0x00000000},
|
||||
{0x0000a07c, 0x00000000},
|
||||
{0x0000a080, 0x22222229},
|
||||
{0x0000a084, 0x1d1d1d1d},
|
||||
{0x0000a088, 0x1d1d1d1d},
|
||||
{0x0000a08c, 0x1d1d1d1d},
|
||||
{0x0000a090, 0x171d1d1d},
|
||||
{0x0000a094, 0x11111717},
|
||||
{0x0000a098, 0x00030311},
|
||||
{0x0000a09c, 0x00000000},
|
||||
{0x0000a0a0, 0x00000000},
|
||||
{0x0000a0a4, 0x00000000},
|
||||
{0x0000a0a8, 0x00000000},
|
||||
{0x0000a0ac, 0x00000000},
|
||||
{0x0000a0b0, 0x00000000},
|
||||
{0x0000a0b4, 0x00000000},
|
||||
{0x0000a0b8, 0x00000000},
|
||||
{0x0000a0bc, 0x00000000},
|
||||
{0x0000a0c0, 0x001f0000},
|
||||
{0x0000a0c4, 0x01000101},
|
||||
{0x0000a0c8, 0x011e011f},
|
||||
{0x0000a0cc, 0x011c011d},
|
||||
{0x0000a0d0, 0x02030204},
|
||||
{0x0000a0d4, 0x02010202},
|
||||
{0x0000a0d8, 0x021f0200},
|
||||
{0x0000a0dc, 0x0302021e},
|
||||
{0x0000a0e0, 0x03000301},
|
||||
{0x0000a0e4, 0x031e031f},
|
||||
{0x0000a0e8, 0x0402031d},
|
||||
{0x0000a0ec, 0x04000401},
|
||||
{0x0000a0f0, 0x041e041f},
|
||||
{0x0000a0f4, 0x0502041d},
|
||||
{0x0000a0f8, 0x05000501},
|
||||
{0x0000a0fc, 0x051e051f},
|
||||
{0x0000a100, 0x06010602},
|
||||
{0x0000a104, 0x061f0600},
|
||||
{0x0000a108, 0x061d061e},
|
||||
{0x0000a10c, 0x07020703},
|
||||
{0x0000a110, 0x07000701},
|
||||
{0x0000a114, 0x00000000},
|
||||
{0x0000a118, 0x00000000},
|
||||
{0x0000a11c, 0x00000000},
|
||||
{0x0000a120, 0x00000000},
|
||||
{0x0000a124, 0x00000000},
|
||||
{0x0000a128, 0x00000000},
|
||||
{0x0000a12c, 0x00000000},
|
||||
{0x0000a130, 0x00000000},
|
||||
{0x0000a134, 0x00000000},
|
||||
{0x0000a138, 0x00000000},
|
||||
{0x0000a13c, 0x00000000},
|
||||
{0x0000a140, 0x001f0000},
|
||||
{0x0000a144, 0x01000101},
|
||||
{0x0000a148, 0x011e011f},
|
||||
{0x0000a14c, 0x011c011d},
|
||||
{0x0000a150, 0x02030204},
|
||||
{0x0000a154, 0x02010202},
|
||||
{0x0000a158, 0x021f0200},
|
||||
{0x0000a15c, 0x0302021e},
|
||||
{0x0000a160, 0x03000301},
|
||||
{0x0000a164, 0x031e031f},
|
||||
{0x0000a168, 0x0402031d},
|
||||
{0x0000a16c, 0x04000401},
|
||||
{0x0000a170, 0x041e041f},
|
||||
{0x0000a174, 0x0502041d},
|
||||
{0x0000a178, 0x05000501},
|
||||
{0x0000a17c, 0x051e051f},
|
||||
{0x0000a180, 0x06010602},
|
||||
{0x0000a184, 0x061f0600},
|
||||
{0x0000a188, 0x061d061e},
|
||||
{0x0000a18c, 0x07020703},
|
||||
{0x0000a190, 0x07000701},
|
||||
{0x0000a194, 0x00000000},
|
||||
{0x0000a198, 0x00000000},
|
||||
{0x0000a19c, 0x00000000},
|
||||
{0x0000a1a0, 0x00000000},
|
||||
{0x0000a1a4, 0x00000000},
|
||||
{0x0000a1a8, 0x00000000},
|
||||
{0x0000a1ac, 0x00000000},
|
||||
{0x0000a1b0, 0x00000000},
|
||||
{0x0000a1b4, 0x00000000},
|
||||
{0x0000a1b8, 0x00000000},
|
||||
{0x0000a1bc, 0x00000000},
|
||||
{0x0000a1c0, 0x00000000},
|
||||
{0x0000a1c4, 0x00000000},
|
||||
{0x0000a1c8, 0x00000000},
|
||||
{0x0000a1cc, 0x00000000},
|
||||
{0x0000a1d0, 0x00000000},
|
||||
{0x0000a1d4, 0x00000000},
|
||||
{0x0000a1d8, 0x00000000},
|
||||
{0x0000a1dc, 0x00000000},
|
||||
{0x0000a1e0, 0x00000000},
|
||||
{0x0000a1e4, 0x00000000},
|
||||
{0x0000a1e8, 0x00000000},
|
||||
{0x0000a1ec, 0x00000000},
|
||||
{0x0000a1f0, 0x00000396},
|
||||
{0x0000a1f4, 0x00000396},
|
||||
{0x0000a1f8, 0x00000396},
|
||||
{0x0000a1fc, 0x00000196},
|
||||
{0x0000b000, 0x00010000},
|
||||
{0x0000b004, 0x00030002},
|
||||
{0x0000b008, 0x00050004},
|
||||
{0x0000b00c, 0x00810080},
|
||||
{0x0000b010, 0x00830082},
|
||||
{0x0000b014, 0x01810180},
|
||||
{0x0000b018, 0x01830182},
|
||||
{0x0000b01c, 0x01850184},
|
||||
{0x0000b020, 0x02810280},
|
||||
{0x0000b024, 0x02830282},
|
||||
{0x0000b028, 0x02850284},
|
||||
{0x0000b02c, 0x02890288},
|
||||
{0x0000b030, 0x028b028a},
|
||||
{0x0000b034, 0x0388028c},
|
||||
{0x0000b038, 0x038a0389},
|
||||
{0x0000b03c, 0x038c038b},
|
||||
{0x0000b040, 0x0390038d},
|
||||
{0x0000b044, 0x03920391},
|
||||
{0x0000b048, 0x03940393},
|
||||
{0x0000b04c, 0x03960395},
|
||||
{0x0000b050, 0x00000000},
|
||||
{0x0000b054, 0x00000000},
|
||||
{0x0000b058, 0x00000000},
|
||||
{0x0000b05c, 0x00000000},
|
||||
{0x0000b060, 0x00000000},
|
||||
{0x0000b064, 0x00000000},
|
||||
{0x0000b068, 0x00000000},
|
||||
{0x0000b06c, 0x00000000},
|
||||
{0x0000b070, 0x00000000},
|
||||
{0x0000b074, 0x00000000},
|
||||
{0x0000b078, 0x00000000},
|
||||
{0x0000b07c, 0x00000000},
|
||||
{0x0000b080, 0x23232323},
|
||||
{0x0000b084, 0x21232323},
|
||||
{0x0000b088, 0x19191c1e},
|
||||
{0x0000b08c, 0x12141417},
|
||||
{0x0000b090, 0x07070e0e},
|
||||
{0x0000b094, 0x03030305},
|
||||
{0x0000b098, 0x00000003},
|
||||
{0x0000b09c, 0x00000000},
|
||||
{0x0000b0a0, 0x00000000},
|
||||
{0x0000b0a4, 0x00000000},
|
||||
{0x0000b0a8, 0x00000000},
|
||||
{0x0000b0ac, 0x00000000},
|
||||
{0x0000b0b0, 0x00000000},
|
||||
{0x0000b0b4, 0x00000000},
|
||||
{0x0000b0b8, 0x00000000},
|
||||
{0x0000b0bc, 0x00000000},
|
||||
{0x0000b0c0, 0x003f0020},
|
||||
{0x0000b0c4, 0x00400041},
|
||||
{0x0000b0c8, 0x0140005f},
|
||||
{0x0000b0cc, 0x0160015f},
|
||||
{0x0000b0d0, 0x017e017f},
|
||||
{0x0000b0d4, 0x02410242},
|
||||
{0x0000b0d8, 0x025f0240},
|
||||
{0x0000b0dc, 0x027f0260},
|
||||
{0x0000b0e0, 0x0341027e},
|
||||
{0x0000b0e4, 0x035f0340},
|
||||
{0x0000b0e8, 0x037f0360},
|
||||
{0x0000b0ec, 0x04400441},
|
||||
{0x0000b0f0, 0x0460045f},
|
||||
{0x0000b0f4, 0x0541047f},
|
||||
{0x0000b0f8, 0x055f0540},
|
||||
{0x0000b0fc, 0x057f0560},
|
||||
{0x0000b100, 0x06400641},
|
||||
{0x0000b104, 0x0660065f},
|
||||
{0x0000b108, 0x067e067f},
|
||||
{0x0000b10c, 0x07410742},
|
||||
{0x0000b110, 0x075f0740},
|
||||
{0x0000b114, 0x077f0760},
|
||||
{0x0000b118, 0x07800781},
|
||||
{0x0000b11c, 0x07a0079f},
|
||||
{0x0000b120, 0x07c107bf},
|
||||
{0x0000b124, 0x000007c0},
|
||||
{0x0000b128, 0x00000000},
|
||||
{0x0000b12c, 0x00000000},
|
||||
{0x0000b130, 0x00000000},
|
||||
{0x0000b134, 0x00000000},
|
||||
{0x0000b138, 0x00000000},
|
||||
{0x0000b13c, 0x00000000},
|
||||
{0x0000b140, 0x003f0020},
|
||||
{0x0000b144, 0x00400041},
|
||||
{0x0000b148, 0x0140005f},
|
||||
{0x0000b14c, 0x0160015f},
|
||||
{0x0000b150, 0x017e017f},
|
||||
{0x0000b154, 0x02410242},
|
||||
{0x0000b158, 0x025f0240},
|
||||
{0x0000b15c, 0x027f0260},
|
||||
{0x0000b160, 0x0341027e},
|
||||
{0x0000b164, 0x035f0340},
|
||||
{0x0000b168, 0x037f0360},
|
||||
{0x0000b16c, 0x04400441},
|
||||
{0x0000b170, 0x0460045f},
|
||||
{0x0000b174, 0x0541047f},
|
||||
{0x0000b178, 0x055f0540},
|
||||
{0x0000b17c, 0x057f0560},
|
||||
{0x0000b180, 0x06400641},
|
||||
{0x0000b184, 0x0660065f},
|
||||
{0x0000b188, 0x067e067f},
|
||||
{0x0000b18c, 0x07410742},
|
||||
{0x0000b190, 0x075f0740},
|
||||
{0x0000b194, 0x077f0760},
|
||||
{0x0000b198, 0x07800781},
|
||||
{0x0000b19c, 0x07a0079f},
|
||||
{0x0000b1a0, 0x07c107bf},
|
||||
{0x0000b1a4, 0x000007c0},
|
||||
{0x0000b1a8, 0x00000000},
|
||||
{0x0000b1ac, 0x00000000},
|
||||
{0x0000b1b0, 0x00000000},
|
||||
{0x0000b1b4, 0x00000000},
|
||||
{0x0000b1b8, 0x00000000},
|
||||
{0x0000b1bc, 0x00000000},
|
||||
{0x0000b1c0, 0x00000000},
|
||||
{0x0000b1c4, 0x00000000},
|
||||
{0x0000b1c8, 0x00000000},
|
||||
{0x0000b1cc, 0x00000000},
|
||||
{0x0000b1d0, 0x00000000},
|
||||
{0x0000b1d4, 0x00000000},
|
||||
{0x0000b1d8, 0x00000000},
|
||||
{0x0000b1dc, 0x00000000},
|
||||
{0x0000b1e0, 0x00000000},
|
||||
{0x0000b1e4, 0x00000000},
|
||||
{0x0000b1e8, 0x00000000},
|
||||
{0x0000b1ec, 0x00000000},
|
||||
{0x0000b1f0, 0x00000396},
|
||||
{0x0000b1f4, 0x00000396},
|
||||
{0x0000b1f8, 0x00000396},
|
||||
{0x0000b1fc, 0x00000196},
|
||||
};
|
||||
|
||||
static const u32 ar955x_1p0_baseband_core[][2] = {
|
||||
/* Addr allmodes */
|
||||
{0x00009800, 0xafe68e30},
|
||||
|
@ -891,266 +632,6 @@ static const u32 ar955x_1p0_baseband_core[][2] = {
|
|||
{0x0000c420, 0x00000000},
|
||||
};
|
||||
|
||||
static const u32 ar955x_1p0_common_wo_xlna_rx_gain_table[][2] = {
|
||||
/* Addr allmodes */
|
||||
{0x0000a000, 0x00010000},
|
||||
{0x0000a004, 0x00030002},
|
||||
{0x0000a008, 0x00050004},
|
||||
{0x0000a00c, 0x00810080},
|
||||
{0x0000a010, 0x00830082},
|
||||
{0x0000a014, 0x01810180},
|
||||
{0x0000a018, 0x01830182},
|
||||
{0x0000a01c, 0x01850184},
|
||||
{0x0000a020, 0x01890188},
|
||||
{0x0000a024, 0x018b018a},
|
||||
{0x0000a028, 0x018d018c},
|
||||
{0x0000a02c, 0x03820190},
|
||||
{0x0000a030, 0x03840383},
|
||||
{0x0000a034, 0x03880385},
|
||||
{0x0000a038, 0x038a0389},
|
||||
{0x0000a03c, 0x038c038b},
|
||||
{0x0000a040, 0x0390038d},
|
||||
{0x0000a044, 0x03920391},
|
||||
{0x0000a048, 0x03940393},
|
||||
{0x0000a04c, 0x03960395},
|
||||
{0x0000a050, 0x00000000},
|
||||
{0x0000a054, 0x00000000},
|
||||
{0x0000a058, 0x00000000},
|
||||
{0x0000a05c, 0x00000000},
|
||||
{0x0000a060, 0x00000000},
|
||||
{0x0000a064, 0x00000000},
|
||||
{0x0000a068, 0x00000000},
|
||||
{0x0000a06c, 0x00000000},
|
||||
{0x0000a070, 0x00000000},
|
||||
{0x0000a074, 0x00000000},
|
||||
{0x0000a078, 0x00000000},
|
||||
{0x0000a07c, 0x00000000},
|
||||
{0x0000a080, 0x29292929},
|
||||
{0x0000a084, 0x29292929},
|
||||
{0x0000a088, 0x29292929},
|
||||
{0x0000a08c, 0x29292929},
|
||||
{0x0000a090, 0x22292929},
|
||||
{0x0000a094, 0x1d1d2222},
|
||||
{0x0000a098, 0x0c111117},
|
||||
{0x0000a09c, 0x00030303},
|
||||
{0x0000a0a0, 0x00000000},
|
||||
{0x0000a0a4, 0x00000000},
|
||||
{0x0000a0a8, 0x00000000},
|
||||
{0x0000a0ac, 0x00000000},
|
||||
{0x0000a0b0, 0x00000000},
|
||||
{0x0000a0b4, 0x00000000},
|
||||
{0x0000a0b8, 0x00000000},
|
||||
{0x0000a0bc, 0x00000000},
|
||||
{0x0000a0c0, 0x001f0000},
|
||||
{0x0000a0c4, 0x01000101},
|
||||
{0x0000a0c8, 0x011e011f},
|
||||
{0x0000a0cc, 0x011c011d},
|
||||
{0x0000a0d0, 0x02030204},
|
||||
{0x0000a0d4, 0x02010202},
|
||||
{0x0000a0d8, 0x021f0200},
|
||||
{0x0000a0dc, 0x0302021e},
|
||||
{0x0000a0e0, 0x03000301},
|
||||
{0x0000a0e4, 0x031e031f},
|
||||
{0x0000a0e8, 0x0402031d},
|
||||
{0x0000a0ec, 0x04000401},
|
||||
{0x0000a0f0, 0x041e041f},
|
||||
{0x0000a0f4, 0x0502041d},
|
||||
{0x0000a0f8, 0x05000501},
|
||||
{0x0000a0fc, 0x051e051f},
|
||||
{0x0000a100, 0x06010602},
|
||||
{0x0000a104, 0x061f0600},
|
||||
{0x0000a108, 0x061d061e},
|
||||
{0x0000a10c, 0x07020703},
|
||||
{0x0000a110, 0x07000701},
|
||||
{0x0000a114, 0x00000000},
|
||||
{0x0000a118, 0x00000000},
|
||||
{0x0000a11c, 0x00000000},
|
||||
{0x0000a120, 0x00000000},
|
||||
{0x0000a124, 0x00000000},
|
||||
{0x0000a128, 0x00000000},
|
||||
{0x0000a12c, 0x00000000},
|
||||
{0x0000a130, 0x00000000},
|
||||
{0x0000a134, 0x00000000},
|
||||
{0x0000a138, 0x00000000},
|
||||
{0x0000a13c, 0x00000000},
|
||||
{0x0000a140, 0x001f0000},
|
||||
{0x0000a144, 0x01000101},
|
||||
{0x0000a148, 0x011e011f},
|
||||
{0x0000a14c, 0x011c011d},
|
||||
{0x0000a150, 0x02030204},
|
||||
{0x0000a154, 0x02010202},
|
||||
{0x0000a158, 0x021f0200},
|
||||
{0x0000a15c, 0x0302021e},
|
||||
{0x0000a160, 0x03000301},
|
||||
{0x0000a164, 0x031e031f},
|
||||
{0x0000a168, 0x0402031d},
|
||||
{0x0000a16c, 0x04000401},
|
||||
{0x0000a170, 0x041e041f},
|
||||
{0x0000a174, 0x0502041d},
|
||||
{0x0000a178, 0x05000501},
|
||||
{0x0000a17c, 0x051e051f},
|
||||
{0x0000a180, 0x06010602},
|
||||
{0x0000a184, 0x061f0600},
|
||||
{0x0000a188, 0x061d061e},
|
||||
{0x0000a18c, 0x07020703},
|
||||
{0x0000a190, 0x07000701},
|
||||
{0x0000a194, 0x00000000},
|
||||
{0x0000a198, 0x00000000},
|
||||
{0x0000a19c, 0x00000000},
|
||||
{0x0000a1a0, 0x00000000},
|
||||
{0x0000a1a4, 0x00000000},
|
||||
{0x0000a1a8, 0x00000000},
|
||||
{0x0000a1ac, 0x00000000},
|
||||
{0x0000a1b0, 0x00000000},
|
||||
{0x0000a1b4, 0x00000000},
|
||||
{0x0000a1b8, 0x00000000},
|
||||
{0x0000a1bc, 0x00000000},
|
||||
{0x0000a1c0, 0x00000000},
|
||||
{0x0000a1c4, 0x00000000},
|
||||
{0x0000a1c8, 0x00000000},
|
||||
{0x0000a1cc, 0x00000000},
|
||||
{0x0000a1d0, 0x00000000},
|
||||
{0x0000a1d4, 0x00000000},
|
||||
{0x0000a1d8, 0x00000000},
|
||||
{0x0000a1dc, 0x00000000},
|
||||
{0x0000a1e0, 0x00000000},
|
||||
{0x0000a1e4, 0x00000000},
|
||||
{0x0000a1e8, 0x00000000},
|
||||
{0x0000a1ec, 0x00000000},
|
||||
{0x0000a1f0, 0x00000396},
|
||||
{0x0000a1f4, 0x00000396},
|
||||
{0x0000a1f8, 0x00000396},
|
||||
{0x0000a1fc, 0x00000196},
|
||||
{0x0000b000, 0x00010000},
|
||||
{0x0000b004, 0x00030002},
|
||||
{0x0000b008, 0x00050004},
|
||||
{0x0000b00c, 0x00810080},
|
||||
{0x0000b010, 0x00830082},
|
||||
{0x0000b014, 0x01810180},
|
||||
{0x0000b018, 0x01830182},
|
||||
{0x0000b01c, 0x01850184},
|
||||
{0x0000b020, 0x02810280},
|
||||
{0x0000b024, 0x02830282},
|
||||
{0x0000b028, 0x02850284},
|
||||
{0x0000b02c, 0x02890288},
|
||||
{0x0000b030, 0x028b028a},
|
||||
{0x0000b034, 0x0388028c},
|
||||
{0x0000b038, 0x038a0389},
|
||||
{0x0000b03c, 0x038c038b},
|
||||
{0x0000b040, 0x0390038d},
|
||||
{0x0000b044, 0x03920391},
|
||||
{0x0000b048, 0x03940393},
|
||||
{0x0000b04c, 0x03960395},
|
||||
{0x0000b050, 0x00000000},
|
||||
{0x0000b054, 0x00000000},
|
||||
{0x0000b058, 0x00000000},
|
||||
{0x0000b05c, 0x00000000},
|
||||
{0x0000b060, 0x00000000},
|
||||
{0x0000b064, 0x00000000},
|
||||
{0x0000b068, 0x00000000},
|
||||
{0x0000b06c, 0x00000000},
|
||||
{0x0000b070, 0x00000000},
|
||||
{0x0000b074, 0x00000000},
|
||||
{0x0000b078, 0x00000000},
|
||||
{0x0000b07c, 0x00000000},
|
||||
{0x0000b080, 0x32323232},
|
||||
{0x0000b084, 0x2f2f3232},
|
||||
{0x0000b088, 0x23282a2d},
|
||||
{0x0000b08c, 0x1c1e2123},
|
||||
{0x0000b090, 0x14171919},
|
||||
{0x0000b094, 0x0e0e1214},
|
||||
{0x0000b098, 0x03050707},
|
||||
{0x0000b09c, 0x00030303},
|
||||
{0x0000b0a0, 0x00000000},
|
||||
{0x0000b0a4, 0x00000000},
|
||||
{0x0000b0a8, 0x00000000},
|
||||
{0x0000b0ac, 0x00000000},
|
||||
{0x0000b0b0, 0x00000000},
|
||||
{0x0000b0b4, 0x00000000},
|
||||
{0x0000b0b8, 0x00000000},
|
||||
{0x0000b0bc, 0x00000000},
|
||||
{0x0000b0c0, 0x003f0020},
|
||||
{0x0000b0c4, 0x00400041},
|
||||
{0x0000b0c8, 0x0140005f},
|
||||
{0x0000b0cc, 0x0160015f},
|
||||
{0x0000b0d0, 0x017e017f},
|
||||
{0x0000b0d4, 0x02410242},
|
||||
{0x0000b0d8, 0x025f0240},
|
||||
{0x0000b0dc, 0x027f0260},
|
||||
{0x0000b0e0, 0x0341027e},
|
||||
{0x0000b0e4, 0x035f0340},
|
||||
{0x0000b0e8, 0x037f0360},
|
||||
{0x0000b0ec, 0x04400441},
|
||||
{0x0000b0f0, 0x0460045f},
|
||||
{0x0000b0f4, 0x0541047f},
|
||||
{0x0000b0f8, 0x055f0540},
|
||||
{0x0000b0fc, 0x057f0560},
|
||||
{0x0000b100, 0x06400641},
|
||||
{0x0000b104, 0x0660065f},
|
||||
{0x0000b108, 0x067e067f},
|
||||
{0x0000b10c, 0x07410742},
|
||||
{0x0000b110, 0x075f0740},
|
||||
{0x0000b114, 0x077f0760},
|
||||
{0x0000b118, 0x07800781},
|
||||
{0x0000b11c, 0x07a0079f},
|
||||
{0x0000b120, 0x07c107bf},
|
||||
{0x0000b124, 0x000007c0},
|
||||
{0x0000b128, 0x00000000},
|
||||
{0x0000b12c, 0x00000000},
|
||||
{0x0000b130, 0x00000000},
|
||||
{0x0000b134, 0x00000000},
|
||||
{0x0000b138, 0x00000000},
|
||||
{0x0000b13c, 0x00000000},
|
||||
{0x0000b140, 0x003f0020},
|
||||
{0x0000b144, 0x00400041},
|
||||
{0x0000b148, 0x0140005f},
|
||||
{0x0000b14c, 0x0160015f},
|
||||
{0x0000b150, 0x017e017f},
|
||||
{0x0000b154, 0x02410242},
|
||||
{0x0000b158, 0x025f0240},
|
||||
{0x0000b15c, 0x027f0260},
|
||||
{0x0000b160, 0x0341027e},
|
||||
{0x0000b164, 0x035f0340},
|
||||
{0x0000b168, 0x037f0360},
|
||||
{0x0000b16c, 0x04400441},
|
||||
{0x0000b170, 0x0460045f},
|
||||
{0x0000b174, 0x0541047f},
|
||||
{0x0000b178, 0x055f0540},
|
||||
{0x0000b17c, 0x057f0560},
|
||||
{0x0000b180, 0x06400641},
|
||||
{0x0000b184, 0x0660065f},
|
||||
{0x0000b188, 0x067e067f},
|
||||
{0x0000b18c, 0x07410742},
|
||||
{0x0000b190, 0x075f0740},
|
||||
{0x0000b194, 0x077f0760},
|
||||
{0x0000b198, 0x07800781},
|
||||
{0x0000b19c, 0x07a0079f},
|
||||
{0x0000b1a0, 0x07c107bf},
|
||||
{0x0000b1a4, 0x000007c0},
|
||||
{0x0000b1a8, 0x00000000},
|
||||
{0x0000b1ac, 0x00000000},
|
||||
{0x0000b1b0, 0x00000000},
|
||||
{0x0000b1b4, 0x00000000},
|
||||
{0x0000b1b8, 0x00000000},
|
||||
{0x0000b1bc, 0x00000000},
|
||||
{0x0000b1c0, 0x00000000},
|
||||
{0x0000b1c4, 0x00000000},
|
||||
{0x0000b1c8, 0x00000000},
|
||||
{0x0000b1cc, 0x00000000},
|
||||
{0x0000b1d0, 0x00000000},
|
||||
{0x0000b1d4, 0x00000000},
|
||||
{0x0000b1d8, 0x00000000},
|
||||
{0x0000b1dc, 0x00000000},
|
||||
{0x0000b1e0, 0x00000000},
|
||||
{0x0000b1e4, 0x00000000},
|
||||
{0x0000b1e8, 0x00000000},
|
||||
{0x0000b1ec, 0x00000000},
|
||||
{0x0000b1f0, 0x00000396},
|
||||
{0x0000b1f4, 0x00000396},
|
||||
{0x0000b1f8, 0x00000396},
|
||||
{0x0000b1fc, 0x00000196},
|
||||
};
|
||||
|
||||
static const u32 ar955x_1p0_soc_preamble[][2] = {
|
||||
/* Addr allmodes */
|
||||
{0x00007000, 0x00000000},
|
||||
|
@ -1263,11 +744,6 @@ static const u32 ar955x_1p0_modes_no_xpa_tx_gain_table[][9] = {
|
|||
{0x00016848, 0x66482401, 0x66482401, 0x66482401, 0x66482401, 0x66482401, 0x66482401, 0x66482401, 0x66482401},
|
||||
};
|
||||
|
||||
static const u32 ar955x_1p0_soc_postamble[][5] = {
|
||||
/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
|
||||
{0x00007010, 0x00000023, 0x00000023, 0x00000023, 0x00000023},
|
||||
};
|
||||
|
||||
static const u32 ar955x_1p0_modes_fast_clock[][3] = {
|
||||
/* Addr 5G_HT20 5G_HT40 */
|
||||
{0x00001030, 0x00000268, 0x000004d0},
|
||||
|
|
|
@ -20,6 +20,12 @@
|
|||
|
||||
/* AR9565 1.0 */
|
||||
|
||||
#define ar9565_1p0_mac_postamble ar9331_1p1_mac_postamble
|
||||
|
||||
#define ar9565_1p0_Modes_lowest_ob_db_tx_gain_table ar9565_1p0_modes_low_ob_db_tx_gain_table
|
||||
|
||||
#define ar9565_1p0_baseband_core_txfir_coeff_japan_2484 ar9300_2p2_baseband_core_txfir_coeff_japan_2484
|
||||
|
||||
static const u32 ar9565_1p0_mac_core[][2] = {
|
||||
/* Addr allmodes */
|
||||
{0x00000008, 0x00000000},
|
||||
|
@ -182,18 +188,6 @@ static const u32 ar9565_1p0_mac_core[][2] = {
|
|||
{0x000083d0, 0x800301ff},
|
||||
};
|
||||
|
||||
static const u32 ar9565_1p0_mac_postamble[][5] = {
|
||||
/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
|
||||
{0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160},
|
||||
{0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c},
|
||||
{0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38},
|
||||
{0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00},
|
||||
{0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b},
|
||||
{0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810},
|
||||
{0x000081d0, 0x00003210, 0x00003210, 0x0000320a, 0x0000320a},
|
||||
{0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440},
|
||||
};
|
||||
|
||||
static const u32 ar9565_1p0_baseband_core[][2] = {
|
||||
/* Addr allmodes */
|
||||
{0x00009800, 0xafe68e30},
|
||||
|
@ -711,66 +705,6 @@ static const u32 ar9565_1p0_Common_rx_gain_table[][2] = {
|
|||
{0x0000b1fc, 0x00000196},
|
||||
};
|
||||
|
||||
static const u32 ar9565_1p0_Modes_lowest_ob_db_tx_gain_table[][5] = {
|
||||
/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
|
||||
{0x0000a2dc, 0xfc0a9380, 0xfc0a9380, 0xfdab5b52, 0xfdab5b52},
|
||||
{0x0000a2e0, 0xffecec00, 0xffecec00, 0xfd339c84, 0xfd339c84},
|
||||
{0x0000a2e4, 0xfc0f0000, 0xfc0f0000, 0xfec3e000, 0xfec3e000},
|
||||
{0x0000a2e8, 0xfc100000, 0xfc100000, 0xfffc0000, 0xfffc0000},
|
||||
{0x0000a410, 0x000050d9, 0x000050d9, 0x000050d9, 0x000050d9},
|
||||
{0x0000a500, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
|
||||
{0x0000a504, 0x06000003, 0x06000003, 0x04000002, 0x04000002},
|
||||
{0x0000a508, 0x0a000020, 0x0a000020, 0x08000004, 0x08000004},
|
||||
{0x0000a50c, 0x10000023, 0x10000023, 0x0b000200, 0x0b000200},
|
||||
{0x0000a510, 0x16000220, 0x16000220, 0x0f000202, 0x0f000202},
|
||||
{0x0000a514, 0x1c000223, 0x1c000223, 0x12000400, 0x12000400},
|
||||
{0x0000a518, 0x21020220, 0x21020220, 0x16000402, 0x16000402},
|
||||
{0x0000a51c, 0x27020223, 0x27020223, 0x19000404, 0x19000404},
|
||||
{0x0000a520, 0x2b022220, 0x2b022220, 0x1c000603, 0x1c000603},
|
||||
{0x0000a524, 0x2f022222, 0x2f022222, 0x21000a02, 0x21000a02},
|
||||
{0x0000a528, 0x34022225, 0x34022225, 0x25000a04, 0x25000a04},
|
||||
{0x0000a52c, 0x3a02222a, 0x3a02222a, 0x28000a20, 0x28000a20},
|
||||
{0x0000a530, 0x3e02222c, 0x3e02222c, 0x2c000e20, 0x2c000e20},
|
||||
{0x0000a534, 0x4202242a, 0x4202242a, 0x30000e22, 0x30000e22},
|
||||
{0x0000a538, 0x4702244a, 0x4702244a, 0x34000e24, 0x34000e24},
|
||||
{0x0000a53c, 0x4b02244c, 0x4b02244c, 0x38001640, 0x38001640},
|
||||
{0x0000a540, 0x4e02246c, 0x4e02246c, 0x3c001660, 0x3c001660},
|
||||
{0x0000a544, 0x5302266c, 0x5302266c, 0x3f001861, 0x3f001861},
|
||||
{0x0000a548, 0x5702286c, 0x5702286c, 0x43001a81, 0x43001a81},
|
||||
{0x0000a54c, 0x5c04286b, 0x5c04286b, 0x47001a83, 0x47001a83},
|
||||
{0x0000a550, 0x61042a6c, 0x61042a6c, 0x4a001c84, 0x4a001c84},
|
||||
{0x0000a554, 0x66062a6c, 0x66062a6c, 0x4e001ce3, 0x4e001ce3},
|
||||
{0x0000a558, 0x6b062e6c, 0x6b062e6c, 0x52001ce5, 0x52001ce5},
|
||||
{0x0000a55c, 0x7006308c, 0x7006308c, 0x56001ce9, 0x56001ce9},
|
||||
{0x0000a560, 0x730a308a, 0x730a308a, 0x5a001ceb, 0x5a001ceb},
|
||||
{0x0000a564, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
|
||||
{0x0000a568, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
|
||||
{0x0000a56c, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
|
||||
{0x0000a570, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
|
||||
{0x0000a574, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
|
||||
{0x0000a578, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
|
||||
{0x0000a57c, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
|
||||
{0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
|
||||
{0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
|
||||
{0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
|
||||
{0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
|
||||
{0x0000a610, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
|
||||
{0x0000a614, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
|
||||
{0x0000a618, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
|
||||
{0x0000a61c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
|
||||
{0x0000a620, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
|
||||
{0x0000a624, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
|
||||
{0x0000a628, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
|
||||
{0x0000a62c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
|
||||
{0x0000a630, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
|
||||
{0x0000a634, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
|
||||
{0x0000a638, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
|
||||
{0x0000a63c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
|
||||
{0x00016044, 0x012482d4, 0x012482d4, 0x012482d4, 0x012482d4},
|
||||
{0x00016048, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
|
||||
{0x00016054, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
|
||||
};
|
||||
|
||||
static const u32 ar9565_1p0_pciephy_clkreq_disable_L1[][2] = {
|
||||
/* Addr allmodes */
|
||||
{0x00018c00, 0x18212ede},
|
||||
|
@ -1231,11 +1165,4 @@ static const u32 ar9565_1p0_modes_high_power_tx_gain_table[][5] = {
|
|||
{0x00016054, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
|
||||
};
|
||||
|
||||
static const u32 ar9565_1p0_baseband_core_txfir_coeff_japan_2484[][2] = {
|
||||
/* Addr allmodes */
|
||||
{0x0000a398, 0x00000000},
|
||||
{0x0000a39c, 0x6f7f0301},
|
||||
{0x0000a3a0, 0xca9228ee},
|
||||
};
|
||||
|
||||
#endif /* INITVALS_9565_1P0_H */
|
||||
|
|
|
@ -57,8 +57,6 @@ static const u32 ar9580_1p0_baseband_core[][2] = {
|
|||
{0x00009804, 0xfd14e000},
|
||||
{0x00009808, 0x9c0a9f6b},
|
||||
{0x0000980c, 0x04900000},
|
||||
{0x00009814, 0x3280c00a},
|
||||
{0x00009818, 0x00000000},
|
||||
{0x0000981c, 0x00020028},
|
||||
{0x00009834, 0x6400a190},
|
||||
{0x00009838, 0x0108ecff},
|
||||
|
@ -1133,6 +1131,8 @@ static const u32 ar9580_1p0_rx_gain_table[][2] = {
|
|||
static const u32 ar9580_1p0_baseband_postamble[][5] = {
|
||||
/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
|
||||
{0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8011, 0xd00a8011},
|
||||
{0x00009814, 0x3280c00a, 0x3280c00a, 0x3280c00a, 0x3280c00a},
|
||||
{0x00009818, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
|
||||
{0x00009820, 0x206a022e, 0x206a022e, 0x206a012e, 0x206a012e},
|
||||
{0x00009824, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0},
|
||||
{0x00009828, 0x06903081, 0x06903081, 0x06903881, 0x06903881},
|
||||
|
@ -1207,4 +1207,13 @@ static const u32 ar9580_1p0_pcie_phy_pll_on_clkreq[][2] = {
|
|||
{0x00004044, 0x00000000},
|
||||
};
|
||||
|
||||
static const u32 ar9580_1p0_baseband_postamble_dfs_channel[][3] = {
|
||||
/* Addr 5G 2G */
|
||||
{0x00009814, 0x3400c00f, 0x3400c00f},
|
||||
{0x00009824, 0x5ac668d0, 0x5ac668d0},
|
||||
{0x00009828, 0x06903080, 0x06903080},
|
||||
{0x00009e0c, 0x6d4000e2, 0x6d4000e2},
|
||||
{0x00009e14, 0x37b9625e, 0x37b9625e},
|
||||
};
|
||||
|
||||
#endif /* INITVALS_9580_1P0_H */
|
||||
|
|
|
@ -548,11 +548,11 @@ static int ath9k_hw_post_init(struct ath_hw *ah)
|
|||
* EEPROM needs to be initialized before we do this.
|
||||
* This is required for regulatory compliance.
|
||||
*/
|
||||
if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
|
||||
if (AR_SREV_9300_20_OR_LATER(ah)) {
|
||||
u16 regdmn = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
|
||||
if ((regdmn & 0xF0) == CTL_FCC) {
|
||||
ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9462_FCC_2GHZ;
|
||||
ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9462_FCC_5GHZ;
|
||||
ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_2GHZ;
|
||||
ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_5GHZ;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
@ -316,6 +316,7 @@ struct ath9k_ops_config {
|
|||
bool xatten_margin_cfg;
|
||||
bool alt_mingainidx;
|
||||
bool no_pll_pwrsave;
|
||||
bool tx_gain_buffalo;
|
||||
};
|
||||
|
||||
enum ath9k_int {
|
||||
|
@ -864,6 +865,7 @@ struct ath_hw {
|
|||
u32 gpio_mask;
|
||||
u32 gpio_val;
|
||||
|
||||
struct ar5416IniArray ini_dfs;
|
||||
struct ar5416IniArray iniModes;
|
||||
struct ar5416IniArray iniCommon;
|
||||
struct ar5416IniArray iniBB_RfGain;
|
||||
|
|
|
@ -554,7 +554,7 @@ static void ath9k_init_misc(struct ath_softc *sc)
|
|||
sc->spec_config.fft_period = 0xF;
|
||||
}
|
||||
|
||||
static void ath9k_init_platform(struct ath_softc *sc)
|
||||
static void ath9k_init_pcoem_platform(struct ath_softc *sc)
|
||||
{
|
||||
struct ath_hw *ah = sc->sc_ah;
|
||||
struct ath9k_hw_capabilities *pCap = &ah->caps;
|
||||
|
@ -664,6 +664,27 @@ static void ath9k_eeprom_release(struct ath_softc *sc)
|
|||
release_firmware(sc->sc_ah->eeprom_blob);
|
||||
}
|
||||
|
||||
static int ath9k_init_soc_platform(struct ath_softc *sc)
|
||||
{
|
||||
struct ath9k_platform_data *pdata = sc->dev->platform_data;
|
||||
struct ath_hw *ah = sc->sc_ah;
|
||||
int ret = 0;
|
||||
|
||||
if (!pdata)
|
||||
return 0;
|
||||
|
||||
if (pdata->eeprom_name) {
|
||||
ret = ath9k_eeprom_request(sc, pdata->eeprom_name);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
if (pdata->tx_gain_buffalo)
|
||||
ah->config.tx_gain_buffalo = true;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int ath9k_init_softc(u16 devid, struct ath_softc *sc,
|
||||
const struct ath_bus_ops *bus_ops)
|
||||
{
|
||||
|
@ -717,7 +738,11 @@ static int ath9k_init_softc(u16 devid, struct ath_softc *sc,
|
|||
/*
|
||||
* Platform quirks.
|
||||
*/
|
||||
ath9k_init_platform(sc);
|
||||
ath9k_init_pcoem_platform(sc);
|
||||
|
||||
ret = ath9k_init_soc_platform(sc);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/*
|
||||
* Enable WLAN/BT RX Antenna diversity only when:
|
||||
|
@ -731,7 +756,6 @@ static int ath9k_init_softc(u16 devid, struct ath_softc *sc,
|
|||
common->bt_ant_diversity = 1;
|
||||
|
||||
spin_lock_init(&common->cc_lock);
|
||||
|
||||
spin_lock_init(&sc->sc_serial_rw);
|
||||
spin_lock_init(&sc->sc_pm_lock);
|
||||
mutex_init(&sc->mutex);
|
||||
|
@ -753,12 +777,6 @@ static int ath9k_init_softc(u16 devid, struct ath_softc *sc,
|
|||
ath_read_cachesize(common, &csz);
|
||||
common->cachelsz = csz << 2; /* convert to bytes */
|
||||
|
||||
if (pdata && pdata->eeprom_name) {
|
||||
ret = ath9k_eeprom_request(sc, pdata->eeprom_name);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* Initializes the hardware for all supported chipsets */
|
||||
ret = ath9k_hw_init(ah);
|
||||
if (ret)
|
||||
|
@ -856,6 +874,9 @@ static const struct ieee80211_iface_limit if_limits[] = {
|
|||
|
||||
static const struct ieee80211_iface_limit if_dfs_limits[] = {
|
||||
{ .max = 1, .types = BIT(NL80211_IFTYPE_AP) |
|
||||
#ifdef CONFIG_MAC80211_MESH
|
||||
BIT(NL80211_IFTYPE_MESH_POINT) |
|
||||
#endif
|
||||
BIT(NL80211_IFTYPE_ADHOC) },
|
||||
};
|
||||
|
||||
|
|
|
@ -883,9 +883,6 @@
|
|||
|
||||
#define AR_SREV_9330(_ah) \
|
||||
(((_ah)->hw_version.macVersion == AR_SREV_VERSION_9330))
|
||||
#define AR_SREV_9330_10(_ah) \
|
||||
(AR_SREV_9330((_ah)) && \
|
||||
((_ah)->hw_version.macRev == AR_SREV_REVISION_9330_10))
|
||||
#define AR_SREV_9330_11(_ah) \
|
||||
(AR_SREV_9330((_ah)) && \
|
||||
((_ah)->hw_version.macRev == AR_SREV_REVISION_9330_11))
|
||||
|
|
|
@ -48,7 +48,9 @@ static struct sk_buff *ath9k_build_tx99_skb(struct ath_softc *sc)
|
|||
0x02, 0x23, 0x23, 0xab, 0x63, 0x89, 0x51, 0xb3,
|
||||
0xe7, 0x8b, 0x72, 0x90, 0x4c, 0xe8, 0xfb, 0xc0};
|
||||
u32 len = 1200;
|
||||
struct ieee80211_tx_rate *rate;
|
||||
struct ieee80211_hw *hw = sc->hw;
|
||||
struct ath_hw *ah = sc->sc_ah;
|
||||
struct ieee80211_hdr *hdr;
|
||||
struct ieee80211_tx_info *tx_info;
|
||||
struct sk_buff *skb;
|
||||
|
@ -73,10 +75,16 @@ static struct sk_buff *ath9k_build_tx99_skb(struct ath_softc *sc)
|
|||
|
||||
tx_info = IEEE80211_SKB_CB(skb);
|
||||
memset(tx_info, 0, sizeof(*tx_info));
|
||||
rate = &tx_info->control.rates[0];
|
||||
tx_info->band = hw->conf.chandef.chan->band;
|
||||
tx_info->flags = IEEE80211_TX_CTL_NO_ACK;
|
||||
tx_info->control.vif = sc->tx99_vif;
|
||||
tx_info->control.rates[0].count = 1;
|
||||
rate->count = 1;
|
||||
if (ah->curchan && IS_CHAN_HT(ah->curchan)) {
|
||||
rate->flags |= IEEE80211_TX_RC_MCS;
|
||||
if (IS_CHAN_HT40(ah->curchan))
|
||||
rate->flags |= IEEE80211_TX_RC_40_MHZ_WIDTH;
|
||||
}
|
||||
|
||||
memcpy(skb->data + sizeof(*hdr), PN9Data, sizeof(PN9Data));
|
||||
|
||||
|
|
|
@ -1151,14 +1151,14 @@ int wcn36xx_smd_config_bss(struct wcn36xx *wcn, struct ieee80211_vif *vif,
|
|||
/* STA */
|
||||
bss->oper_mode = 1;
|
||||
bss->wcn36xx_hal_persona = WCN36XX_HAL_STA_MODE;
|
||||
} else if (vif->type == NL80211_IFTYPE_AP) {
|
||||
} else if (vif->type == NL80211_IFTYPE_AP ||
|
||||
vif->type == NL80211_IFTYPE_MESH_POINT) {
|
||||
bss->bss_type = WCN36XX_HAL_INFRA_AP_MODE;
|
||||
|
||||
/* AP */
|
||||
bss->oper_mode = 0;
|
||||
bss->wcn36xx_hal_persona = WCN36XX_HAL_STA_SAP_MODE;
|
||||
} else if (vif->type == NL80211_IFTYPE_ADHOC ||
|
||||
vif->type == NL80211_IFTYPE_MESH_POINT) {
|
||||
} else if (vif->type == NL80211_IFTYPE_ADHOC) {
|
||||
bss->bss_type = WCN36XX_HAL_IBSS_MODE;
|
||||
|
||||
/* STA */
|
||||
|
@ -1309,7 +1309,11 @@ int wcn36xx_smd_send_beacon(struct wcn36xx *wcn, struct ieee80211_vif *vif,
|
|||
memcpy(msg_body.bssid, vif->addr, ETH_ALEN);
|
||||
|
||||
/* TODO need to find out why this is needed? */
|
||||
msg_body.tim_ie_offset = tim_off+4;
|
||||
if (vif->type == NL80211_IFTYPE_MESH_POINT)
|
||||
/* mesh beacon don't need this, so push further down */
|
||||
msg_body.tim_ie_offset = 256;
|
||||
else
|
||||
msg_body.tim_ie_offset = tim_off+4;
|
||||
msg_body.p2p_ie_offset = p2p_off;
|
||||
PREPARE_HAL_BUF(wcn->hal_buf, msg_body);
|
||||
|
||||
|
|
|
@ -28,8 +28,8 @@
|
|||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with Atmel wireless lan drivers; if not, write to the Free Software
|
||||
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
along with Atmel wireless lan drivers; if not, see
|
||||
<http://www.gnu.org/licenses/>.
|
||||
|
||||
For all queries about this code, please contact the current author,
|
||||
Simon Kelley <simon@thekelleys.org.uk> and not Atmel Corporation.
|
||||
|
@ -4278,8 +4278,7 @@ static void atmel_wmem32(struct atmel_private *priv, u16 pos, u32 data)
|
|||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with AtmelMACFW; if not, write to the Free Software
|
||||
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
along with AtmelMACFW; if not, see <http://www.gnu.org/licenses/>.
|
||||
|
||||
****************************************************************************/
|
||||
/* This firmware should work on the 76C502 RFMD, RFMD_D, and RFMD_E */
|
||||
|
|
|
@ -15,8 +15,8 @@
|
|||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with Atmel wireless lan drivers; if not, write to the Free Software
|
||||
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
along with Atmel wireless lan drivers; if not, see
|
||||
<http://www.gnu.org/licenses/>.
|
||||
|
||||
******************************************************************************/
|
||||
|
||||
|
|
|
@ -24,8 +24,8 @@
|
|||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with Atmel wireless lan drivers; if not, write to the Free Software
|
||||
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
along with Atmel wireless lan drivers; if not, see
|
||||
<http://www.gnu.org/licenses/>.
|
||||
|
||||
******************************************************************************/
|
||||
|
||||
|
|
|
@ -15,8 +15,8 @@
|
|||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with Atmel wireless lan drivers; if not, write to the Free Software
|
||||
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
along with Atmel wireless lan drivers; if not, see
|
||||
<http://www.gnu.org/licenses/>.
|
||||
|
||||
******************************************************************************/
|
||||
#include <linux/pci.h>
|
||||
|
|
|
@ -389,13 +389,6 @@ struct iwl_lq_sta {
|
|||
u8 last_bt_traffic;
|
||||
};
|
||||
|
||||
static inline u8 num_of_ant(u8 mask)
|
||||
{
|
||||
return !!((mask) & ANT_A) +
|
||||
!!((mask) & ANT_B) +
|
||||
!!((mask) & ANT_C);
|
||||
}
|
||||
|
||||
static inline u8 first_antenna(u8 mask)
|
||||
{
|
||||
if (mask & ANT_A)
|
||||
|
|
|
@ -368,6 +368,7 @@ int iwlagn_tx_skb(struct iwl_priv *priv,
|
|||
goto drop_unlock_priv;
|
||||
|
||||
memset(dev_cmd, 0, sizeof(*dev_cmd));
|
||||
dev_cmd->hdr.cmd = REPLY_TX;
|
||||
tx_cmd = (struct iwl_tx_cmd *) dev_cmd->payload;
|
||||
|
||||
/* Total # bytes to be transmitted */
|
||||
|
|
|
@ -129,6 +129,12 @@ enum iwl_led_mode {
|
|||
#define ANT_BC (ANT_B | ANT_C)
|
||||
#define ANT_ABC (ANT_A | ANT_B | ANT_C)
|
||||
|
||||
static inline u8 num_of_ant(u8 mask)
|
||||
{
|
||||
return !!((mask) & ANT_A) +
|
||||
!!((mask) & ANT_B) +
|
||||
!!((mask) & ANT_C);
|
||||
}
|
||||
|
||||
/*
|
||||
* @max_ll_items: max number of OTP blocks
|
||||
|
|
|
@ -283,7 +283,8 @@ static void iwl_init_vht_hw_capab(const struct iwl_cfg *cfg,
|
|||
IEEE80211_VHT_MCS_NOT_SUPPORTED << 12 |
|
||||
IEEE80211_VHT_MCS_NOT_SUPPORTED << 14);
|
||||
|
||||
if (data->valid_rx_ant == 1 || cfg->rx_with_siso_diversity) {
|
||||
if (num_of_ant(data->valid_rx_ant) == 1 ||
|
||||
cfg->rx_with_siso_diversity) {
|
||||
vht_cap->cap |= IEEE80211_VHT_CAP_RX_ANTENNA_PATTERN |
|
||||
IEEE80211_VHT_CAP_TX_ANTENNA_PATTERN;
|
||||
/* this works because NOT_SUPPORTED == 3 */
|
||||
|
|
|
@ -102,6 +102,9 @@
|
|||
/* Device system time */
|
||||
#define DEVICE_SYSTEM_TIME_REG 0xA0206C
|
||||
|
||||
/* Device NMI register */
|
||||
#define DEVICE_SET_NMI_REG 0x00a01c30
|
||||
|
||||
/*****************************************************************************
|
||||
* 7000/3000 series SHR DTS addresses *
|
||||
*****************************************************************************/
|
||||
|
|
|
@ -5,6 +5,7 @@ iwlmvm-y += scan.o time-event.o rs.o
|
|||
iwlmvm-y += power.o power_legacy.o bt-coex.o
|
||||
iwlmvm-y += led.o tt.o
|
||||
iwlmvm-$(CONFIG_IWLWIFI_DEBUGFS) += debugfs.o
|
||||
iwlmvm-$(CONFIG_IWLWIFI_DEBUGFS) += debugfs.o debugfs-vif.o
|
||||
iwlmvm-$(CONFIG_PM_SLEEP) += d3.o
|
||||
|
||||
ccflags-y += -D__CHECK_ENDIAN__ -I$(src)/../
|
||||
|
|
|
@ -396,7 +396,8 @@ int iwl_send_bt_init_conf(struct iwl_mvm *mvm)
|
|||
BT_VALID_ANT_ISOLATION |
|
||||
BT_VALID_ANT_ISOLATION_THRS |
|
||||
BT_VALID_TXTX_DELTA_FREQ_THRS |
|
||||
BT_VALID_TXRX_MAX_FREQ_0);
|
||||
BT_VALID_TXRX_MAX_FREQ_0 |
|
||||
BT_VALID_SYNC_TO_SCO);
|
||||
|
||||
if (mvm->cfg->bt_shared_single_ant)
|
||||
memcpy(&bt_cmd->decision_lut, iwl_single_shared_ant,
|
||||
|
@ -514,7 +515,7 @@ static int iwl_mvm_bt_coex_reduced_txp(struct iwl_mvm *mvm, u8 sta_id,
|
|||
if (IS_ERR_OR_NULL(sta))
|
||||
return 0;
|
||||
|
||||
mvmsta = (void *)sta->drv_priv;
|
||||
mvmsta = iwl_mvm_sta_from_mac80211(sta);
|
||||
|
||||
/* nothing to do */
|
||||
if (mvmsta->bt_reduced_txpower == enable)
|
||||
|
@ -846,7 +847,7 @@ static void iwl_mvm_bt_rssi_iterator(void *_data, u8 *mac,
|
|||
if (IS_ERR_OR_NULL(sta))
|
||||
return;
|
||||
|
||||
mvmsta = (void *)sta->drv_priv;
|
||||
mvmsta = iwl_mvm_sta_from_mac80211(sta);
|
||||
|
||||
data->num_bss_ifaces++;
|
||||
|
||||
|
@ -917,11 +918,11 @@ void iwl_mvm_bt_rssi_event(struct iwl_mvm *mvm, struct ieee80211_vif *vif,
|
|||
u16 iwl_mvm_bt_coex_agg_time_limit(struct iwl_mvm *mvm,
|
||||
struct ieee80211_sta *sta)
|
||||
{
|
||||
struct iwl_mvm_sta *mvmsta = (void *)sta->drv_priv;
|
||||
struct iwl_mvm_sta *mvmsta = iwl_mvm_sta_from_mac80211(sta);
|
||||
enum iwl_bt_coex_lut_type lut_type;
|
||||
|
||||
if (le32_to_cpu(mvm->last_bt_notif.bt_activity_grading) <
|
||||
BT_LOW_TRAFFIC)
|
||||
BT_HIGH_TRAFFIC)
|
||||
return LINK_QUAL_AGG_TIME_LIMIT_DEF;
|
||||
|
||||
lut_type = iwl_get_coex_type(mvm, mvmsta->vif);
|
||||
|
@ -936,7 +937,7 @@ u16 iwl_mvm_bt_coex_agg_time_limit(struct iwl_mvm *mvm,
|
|||
bool iwl_mvm_bt_coex_is_mimo_allowed(struct iwl_mvm *mvm,
|
||||
struct ieee80211_sta *sta)
|
||||
{
|
||||
struct iwl_mvm_sta *mvmsta = (void *)sta->drv_priv;
|
||||
struct iwl_mvm_sta *mvmsta = iwl_mvm_sta_from_mac80211(sta);
|
||||
|
||||
if (le32_to_cpu(mvm->last_bt_notif.bt_activity_grading) <
|
||||
BT_HIGH_TRAFFIC)
|
||||
|
|
|
@ -1216,10 +1216,6 @@ static int __iwl_mvm_suspend(struct ieee80211_hw *hw,
|
|||
if (len >= sizeof(u32) * 2) {
|
||||
mvm->d3_test_pme_ptr =
|
||||
le32_to_cpup((__le32 *)d3_cfg_cmd.resp_pkt->data);
|
||||
} else if (test) {
|
||||
/* in test mode we require the pointer */
|
||||
ret = -EIO;
|
||||
goto out;
|
||||
}
|
||||
#endif
|
||||
iwl_free_resp(&d3_cfg_cmd);
|
||||
|
@ -1231,10 +1227,11 @@ static int __iwl_mvm_suspend(struct ieee80211_hw *hw,
|
|||
mvm->aux_sta.sta_id = old_aux_sta_id;
|
||||
mvm_ap_sta->sta_id = old_ap_sta_id;
|
||||
mvmvif->ap_sta_id = old_ap_sta_id;
|
||||
out_noreset:
|
||||
kfree(key_data.rsc_tsc);
|
||||
|
||||
if (ret < 0)
|
||||
ieee80211_restart_hw(mvm->hw);
|
||||
out_noreset:
|
||||
kfree(key_data.rsc_tsc);
|
||||
|
||||
mutex_unlock(&mvm->mutex);
|
||||
|
||||
|
@ -1537,10 +1534,16 @@ static bool iwl_mvm_setup_connection_keep(struct iwl_mvm *mvm,
|
|||
struct iwl_mvm_d3_gtk_iter_data gtkdata = {
|
||||
.status = status,
|
||||
};
|
||||
u32 disconnection_reasons =
|
||||
IWL_WOWLAN_WAKEUP_BY_DISCONNECTION_ON_MISSED_BEACON |
|
||||
IWL_WOWLAN_WAKEUP_BY_DISCONNECTION_ON_DEAUTH;
|
||||
|
||||
if (!status || !vif->bss_conf.bssid)
|
||||
return false;
|
||||
|
||||
if (le32_to_cpu(status->wakeup_reasons) & disconnection_reasons)
|
||||
return false;
|
||||
|
||||
/* find last GTK that we used initially, if any */
|
||||
gtkdata.find_phase = true;
|
||||
ieee80211_iter_keys(mvm->hw, vif,
|
||||
|
@ -1805,6 +1808,10 @@ static int __iwl_mvm_resume(struct iwl_mvm *mvm, bool test)
|
|||
iwl_mvm_read_d3_sram(mvm);
|
||||
|
||||
keep = iwl_mvm_query_wakeup_reasons(mvm, vif);
|
||||
#ifdef CONFIG_IWLWIFI_DEBUGFS
|
||||
if (keep)
|
||||
mvm->keep_vif = vif;
|
||||
#endif
|
||||
/* has unlocked the mutex, so skip that */
|
||||
goto out;
|
||||
|
||||
|
@ -1861,6 +1868,7 @@ static int iwl_mvm_d3_test_open(struct inode *inode, struct file *file)
|
|||
return err;
|
||||
}
|
||||
mvm->d3_test_active = true;
|
||||
mvm->keep_vif = NULL;
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
@ -1871,10 +1879,14 @@ static ssize_t iwl_mvm_d3_test_read(struct file *file, char __user *user_buf,
|
|||
u32 pme_asserted;
|
||||
|
||||
while (true) {
|
||||
pme_asserted = iwl_trans_read_mem32(mvm->trans,
|
||||
mvm->d3_test_pme_ptr);
|
||||
if (pme_asserted)
|
||||
break;
|
||||
/* read pme_ptr if available */
|
||||
if (mvm->d3_test_pme_ptr) {
|
||||
pme_asserted = iwl_trans_read_mem32(mvm->trans,
|
||||
mvm->d3_test_pme_ptr);
|
||||
if (pme_asserted)
|
||||
break;
|
||||
}
|
||||
|
||||
if (msleep_interruptible(100))
|
||||
break;
|
||||
}
|
||||
|
@ -1885,6 +1897,10 @@ static ssize_t iwl_mvm_d3_test_read(struct file *file, char __user *user_buf,
|
|||
static void iwl_mvm_d3_test_disconn_work_iter(void *_data, u8 *mac,
|
||||
struct ieee80211_vif *vif)
|
||||
{
|
||||
/* skip the one we keep connection on */
|
||||
if (_data == vif)
|
||||
return;
|
||||
|
||||
if (vif->type == NL80211_IFTYPE_STATION)
|
||||
ieee80211_connection_loss(vif);
|
||||
}
|
||||
|
@ -1911,7 +1927,7 @@ static int iwl_mvm_d3_test_release(struct inode *inode, struct file *file)
|
|||
|
||||
ieee80211_iterate_active_interfaces_atomic(
|
||||
mvm->hw, IEEE80211_IFACE_ITER_NORMAL,
|
||||
iwl_mvm_d3_test_disconn_work_iter, NULL);
|
||||
iwl_mvm_d3_test_disconn_work_iter, mvm->keep_vif);
|
||||
|
||||
ieee80211_wake_queues(mvm->hw);
|
||||
|
||||
|
|
190
drivers/net/wireless/iwlwifi/mvm/debugfs-vif.c
Normal file
190
drivers/net/wireless/iwlwifi/mvm/debugfs-vif.c
Normal file
|
@ -0,0 +1,190 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* This file is provided under a dual BSD/GPLv2 license. When using or
|
||||
* redistributing this file, you may do so under either license.
|
||||
*
|
||||
* GPL LICENSE SUMMARY
|
||||
*
|
||||
* Copyright(c) 2012 - 2013 Intel Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but
|
||||
* WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
* General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
|
||||
* USA
|
||||
*
|
||||
* The full GNU General Public License is included in this distribution
|
||||
* in the file called COPYING.
|
||||
*
|
||||
* Contact Information:
|
||||
* Intel Linux Wireless <ilw@linux.intel.com>
|
||||
* Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
|
||||
*
|
||||
* BSD LICENSE
|
||||
*
|
||||
* Copyright(c) 2012 - 2013 Intel Corporation. All rights reserved.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* * Neither the name Intel Corporation nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#include "mvm.h"
|
||||
#include "debugfs.h"
|
||||
|
||||
static ssize_t iwl_dbgfs_mac_params_read(struct file *file,
|
||||
char __user *user_buf,
|
||||
size_t count, loff_t *ppos)
|
||||
{
|
||||
struct ieee80211_vif *vif = file->private_data;
|
||||
struct iwl_mvm_vif *mvmvif = iwl_mvm_vif_from_mac80211(vif);
|
||||
struct iwl_mvm *mvm = mvmvif->mvm;
|
||||
u8 ap_sta_id;
|
||||
struct ieee80211_chanctx_conf *chanctx_conf;
|
||||
char buf[512];
|
||||
int bufsz = sizeof(buf);
|
||||
int pos = 0;
|
||||
int i;
|
||||
|
||||
mutex_lock(&mvm->mutex);
|
||||
|
||||
ap_sta_id = mvmvif->ap_sta_id;
|
||||
|
||||
pos += scnprintf(buf+pos, bufsz-pos, "mac id/color: %d / %d\n",
|
||||
mvmvif->id, mvmvif->color);
|
||||
pos += scnprintf(buf+pos, bufsz-pos, "bssid: %pM\n",
|
||||
vif->bss_conf.bssid);
|
||||
pos += scnprintf(buf+pos, bufsz-pos, "QoS:\n");
|
||||
for (i = 0; i < ARRAY_SIZE(mvmvif->queue_params); i++)
|
||||
pos += scnprintf(buf+pos, bufsz-pos,
|
||||
"\t%d: txop:%d - cw_min:%d - cw_max = %d - aifs = %d upasd = %d\n",
|
||||
i, mvmvif->queue_params[i].txop,
|
||||
mvmvif->queue_params[i].cw_min,
|
||||
mvmvif->queue_params[i].cw_max,
|
||||
mvmvif->queue_params[i].aifs,
|
||||
mvmvif->queue_params[i].uapsd);
|
||||
|
||||
if (vif->type == NL80211_IFTYPE_STATION &&
|
||||
ap_sta_id != IWL_MVM_STATION_COUNT) {
|
||||
struct ieee80211_sta *sta;
|
||||
struct iwl_mvm_sta *mvm_sta;
|
||||
|
||||
sta = rcu_dereference_protected(mvm->fw_id_to_mac_id[ap_sta_id],
|
||||
lockdep_is_held(&mvm->mutex));
|
||||
mvm_sta = (void *)sta->drv_priv;
|
||||
pos += scnprintf(buf+pos, bufsz-pos,
|
||||
"ap_sta_id %d - reduced Tx power %d\n",
|
||||
ap_sta_id, mvm_sta->bt_reduced_txpower);
|
||||
}
|
||||
|
||||
rcu_read_lock();
|
||||
chanctx_conf = rcu_dereference(vif->chanctx_conf);
|
||||
if (chanctx_conf)
|
||||
pos += scnprintf(buf+pos, bufsz-pos,
|
||||
"idle rx chains %d, active rx chains: %d\n",
|
||||
chanctx_conf->rx_chains_static,
|
||||
chanctx_conf->rx_chains_dynamic);
|
||||
rcu_read_unlock();
|
||||
|
||||
mutex_unlock(&mvm->mutex);
|
||||
|
||||
return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
|
||||
}
|
||||
|
||||
#define MVM_DEBUGFS_ADD_FILE_VIF(name, parent, mode) do { \
|
||||
if (!debugfs_create_file(#name, mode, parent, vif, \
|
||||
&iwl_dbgfs_##name##_ops)) \
|
||||
goto err; \
|
||||
} while (0)
|
||||
|
||||
MVM_DEBUGFS_READ_FILE_OPS(mac_params);
|
||||
|
||||
void iwl_mvm_vif_dbgfs_register(struct iwl_mvm *mvm, struct ieee80211_vif *vif)
|
||||
{
|
||||
struct dentry *dbgfs_dir = vif->debugfs_dir;
|
||||
struct iwl_mvm_vif *mvmvif = iwl_mvm_vif_from_mac80211(vif);
|
||||
char buf[100];
|
||||
|
||||
/*
|
||||
* Check if debugfs directory already exist before creating it.
|
||||
* This may happen when, for example, resetting hw or suspend-resume
|
||||
*/
|
||||
if (!dbgfs_dir || mvmvif->dbgfs_dir)
|
||||
return;
|
||||
|
||||
mvmvif->dbgfs_dir = debugfs_create_dir("iwlmvm", dbgfs_dir);
|
||||
mvmvif->mvm = mvm;
|
||||
|
||||
if (!mvmvif->dbgfs_dir) {
|
||||
IWL_ERR(mvm, "Failed to create debugfs directory under %s\n",
|
||||
dbgfs_dir->d_name.name);
|
||||
return;
|
||||
}
|
||||
|
||||
MVM_DEBUGFS_ADD_FILE_VIF(mac_params, mvmvif->dbgfs_dir,
|
||||
S_IRUSR);
|
||||
|
||||
/*
|
||||
* Create symlink for convenience pointing to interface specific
|
||||
* debugfs entries for the driver. For example, under
|
||||
* /sys/kernel/debug/iwlwifi/0000\:02\:00.0/iwlmvm/
|
||||
* find
|
||||
* netdev:wlan0 -> ../../../ieee80211/phy0/netdev:wlan0/iwlmvm/
|
||||
*/
|
||||
snprintf(buf, 100, "../../../%s/%s/%s/%s",
|
||||
dbgfs_dir->d_parent->d_parent->d_name.name,
|
||||
dbgfs_dir->d_parent->d_name.name,
|
||||
dbgfs_dir->d_name.name,
|
||||
mvmvif->dbgfs_dir->d_name.name);
|
||||
|
||||
mvmvif->dbgfs_slink = debugfs_create_symlink(dbgfs_dir->d_name.name,
|
||||
mvm->debugfs_dir, buf);
|
||||
if (!mvmvif->dbgfs_slink)
|
||||
IWL_ERR(mvm, "Can't create debugfs symbolic link under %s\n",
|
||||
dbgfs_dir->d_name.name);
|
||||
return;
|
||||
err:
|
||||
IWL_ERR(mvm, "Can't create debugfs entity\n");
|
||||
}
|
||||
|
||||
void iwl_mvm_vif_dbgfs_clean(struct iwl_mvm *mvm, struct ieee80211_vif *vif)
|
||||
{
|
||||
struct iwl_mvm_vif *mvmvif = iwl_mvm_vif_from_mac80211(vif);
|
||||
|
||||
debugfs_remove(mvmvif->dbgfs_slink);
|
||||
mvmvif->dbgfs_slink = NULL;
|
||||
|
||||
debugfs_remove_recursive(mvmvif->dbgfs_dir);
|
||||
mvmvif->dbgfs_dir = NULL;
|
||||
}
|
|
@ -63,30 +63,18 @@
|
|||
#include "mvm.h"
|
||||
#include "sta.h"
|
||||
#include "iwl-io.h"
|
||||
#include "iwl-prph.h"
|
||||
#include "debugfs.h"
|
||||
|
||||
struct iwl_dbgfs_mvm_ctx {
|
||||
struct iwl_mvm *mvm;
|
||||
struct ieee80211_vif *vif;
|
||||
};
|
||||
|
||||
static ssize_t iwl_dbgfs_tx_flush_write(struct file *file,
|
||||
const char __user *user_buf,
|
||||
static ssize_t iwl_dbgfs_tx_flush_write(struct iwl_mvm *mvm, char *buf,
|
||||
size_t count, loff_t *ppos)
|
||||
{
|
||||
struct iwl_mvm *mvm = file->private_data;
|
||||
|
||||
char buf[16];
|
||||
int buf_size, ret;
|
||||
int ret;
|
||||
u32 scd_q_msk;
|
||||
|
||||
if (!mvm->ucode_loaded || mvm->cur_ucode != IWL_UCODE_REGULAR)
|
||||
return -EIO;
|
||||
|
||||
memset(buf, 0, sizeof(buf));
|
||||
buf_size = min(count, sizeof(buf) - 1);
|
||||
if (copy_from_user(buf, user_buf, buf_size))
|
||||
return -EFAULT;
|
||||
|
||||
if (sscanf(buf, "%x", &scd_q_msk) != 1)
|
||||
return -EINVAL;
|
||||
|
||||
|
@ -99,24 +87,15 @@ static ssize_t iwl_dbgfs_tx_flush_write(struct file *file,
|
|||
return ret;
|
||||
}
|
||||
|
||||
static ssize_t iwl_dbgfs_sta_drain_write(struct file *file,
|
||||
const char __user *user_buf,
|
||||
static ssize_t iwl_dbgfs_sta_drain_write(struct iwl_mvm *mvm, char *buf,
|
||||
size_t count, loff_t *ppos)
|
||||
{
|
||||
struct iwl_mvm *mvm = file->private_data;
|
||||
struct ieee80211_sta *sta;
|
||||
|
||||
char buf[8];
|
||||
int buf_size, sta_id, drain, ret;
|
||||
int sta_id, drain, ret;
|
||||
|
||||
if (!mvm->ucode_loaded || mvm->cur_ucode != IWL_UCODE_REGULAR)
|
||||
return -EIO;
|
||||
|
||||
memset(buf, 0, sizeof(buf));
|
||||
buf_size = min(count, sizeof(buf) - 1);
|
||||
if (copy_from_user(buf, user_buf, buf_size))
|
||||
return -EFAULT;
|
||||
|
||||
if (sscanf(buf, "%d %d", &sta_id, &drain) != 2)
|
||||
return -EINVAL;
|
||||
if (sta_id < 0 || sta_id >= IWL_MVM_STATION_COUNT)
|
||||
|
@ -194,20 +173,11 @@ static ssize_t iwl_dbgfs_sram_read(struct file *file, char __user *user_buf,
|
|||
return ret;
|
||||
}
|
||||
|
||||
static ssize_t iwl_dbgfs_sram_write(struct file *file,
|
||||
const char __user *user_buf, size_t count,
|
||||
loff_t *ppos)
|
||||
static ssize_t iwl_dbgfs_sram_write(struct iwl_mvm *mvm, char *buf,
|
||||
size_t count, loff_t *ppos)
|
||||
{
|
||||
struct iwl_mvm *mvm = file->private_data;
|
||||
char buf[64];
|
||||
int buf_size;
|
||||
u32 offset, len;
|
||||
|
||||
memset(buf, 0, sizeof(buf));
|
||||
buf_size = min(count, sizeof(buf) - 1);
|
||||
if (copy_from_user(buf, user_buf, buf_size))
|
||||
return -EFAULT;
|
||||
|
||||
if (sscanf(buf, "%x,%x", &offset, &len) == 2) {
|
||||
if ((offset & 0x3) || (len & 0x3))
|
||||
return -EINVAL;
|
||||
|
@ -267,22 +237,14 @@ static ssize_t iwl_dbgfs_disable_power_off_read(struct file *file,
|
|||
return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
|
||||
}
|
||||
|
||||
static ssize_t iwl_dbgfs_disable_power_off_write(struct file *file,
|
||||
const char __user *user_buf,
|
||||
static ssize_t iwl_dbgfs_disable_power_off_write(struct iwl_mvm *mvm, char *buf,
|
||||
size_t count, loff_t *ppos)
|
||||
{
|
||||
struct iwl_mvm *mvm = file->private_data;
|
||||
char buf[64] = {};
|
||||
int ret;
|
||||
int val;
|
||||
int ret, val;
|
||||
|
||||
if (!mvm->ucode_loaded)
|
||||
return -EIO;
|
||||
|
||||
count = min_t(size_t, count, sizeof(buf) - 1);
|
||||
if (copy_from_user(buf, user_buf, count))
|
||||
return -EFAULT;
|
||||
|
||||
if (!strncmp("disable_power_off_d0=", buf, 21)) {
|
||||
if (sscanf(buf + 21, "%d", &val) != 1)
|
||||
return -EINVAL;
|
||||
|
@ -302,212 +264,6 @@ static ssize_t iwl_dbgfs_disable_power_off_write(struct file *file,
|
|||
return ret ?: count;
|
||||
}
|
||||
|
||||
static void iwl_dbgfs_update_pm(struct iwl_mvm *mvm,
|
||||
struct ieee80211_vif *vif,
|
||||
enum iwl_dbgfs_pm_mask param, int val)
|
||||
{
|
||||
struct iwl_mvm_vif *mvmvif = iwl_mvm_vif_from_mac80211(vif);
|
||||
struct iwl_dbgfs_pm *dbgfs_pm = &mvmvif->dbgfs_pm;
|
||||
|
||||
dbgfs_pm->mask |= param;
|
||||
|
||||
switch (param) {
|
||||
case MVM_DEBUGFS_PM_KEEP_ALIVE: {
|
||||
struct ieee80211_hw *hw = mvm->hw;
|
||||
int dtimper = hw->conf.ps_dtim_period ?: 1;
|
||||
int dtimper_msec = dtimper * vif->bss_conf.beacon_int;
|
||||
|
||||
IWL_DEBUG_POWER(mvm, "debugfs: set keep_alive= %d sec\n", val);
|
||||
if (val * MSEC_PER_SEC < 3 * dtimper_msec) {
|
||||
IWL_WARN(mvm,
|
||||
"debugfs: keep alive period (%ld msec) is less than minimum required (%d msec)\n",
|
||||
val * MSEC_PER_SEC, 3 * dtimper_msec);
|
||||
}
|
||||
dbgfs_pm->keep_alive_seconds = val;
|
||||
break;
|
||||
}
|
||||
case MVM_DEBUGFS_PM_SKIP_OVER_DTIM:
|
||||
IWL_DEBUG_POWER(mvm, "skip_over_dtim %s\n",
|
||||
val ? "enabled" : "disabled");
|
||||
dbgfs_pm->skip_over_dtim = val;
|
||||
break;
|
||||
case MVM_DEBUGFS_PM_SKIP_DTIM_PERIODS:
|
||||
IWL_DEBUG_POWER(mvm, "skip_dtim_periods=%d\n", val);
|
||||
dbgfs_pm->skip_dtim_periods = val;
|
||||
break;
|
||||
case MVM_DEBUGFS_PM_RX_DATA_TIMEOUT:
|
||||
IWL_DEBUG_POWER(mvm, "rx_data_timeout=%d\n", val);
|
||||
dbgfs_pm->rx_data_timeout = val;
|
||||
break;
|
||||
case MVM_DEBUGFS_PM_TX_DATA_TIMEOUT:
|
||||
IWL_DEBUG_POWER(mvm, "tx_data_timeout=%d\n", val);
|
||||
dbgfs_pm->tx_data_timeout = val;
|
||||
break;
|
||||
case MVM_DEBUGFS_PM_DISABLE_POWER_OFF:
|
||||
IWL_DEBUG_POWER(mvm, "disable_power_off=%d\n", val);
|
||||
dbgfs_pm->disable_power_off = val;
|
||||
break;
|
||||
case MVM_DEBUGFS_PM_LPRX_ENA:
|
||||
IWL_DEBUG_POWER(mvm, "lprx %s\n", val ? "enabled" : "disabled");
|
||||
dbgfs_pm->lprx_ena = val;
|
||||
break;
|
||||
case MVM_DEBUGFS_PM_LPRX_RSSI_THRESHOLD:
|
||||
IWL_DEBUG_POWER(mvm, "lprx_rssi_threshold=%d\n", val);
|
||||
dbgfs_pm->lprx_rssi_threshold = val;
|
||||
break;
|
||||
case MVM_DEBUGFS_PM_SNOOZE_ENABLE:
|
||||
IWL_DEBUG_POWER(mvm, "snooze_enable=%d\n", val);
|
||||
dbgfs_pm->snooze_ena = val;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
static ssize_t iwl_dbgfs_pm_params_write(struct file *file,
|
||||
const char __user *user_buf,
|
||||
size_t count, loff_t *ppos)
|
||||
{
|
||||
struct ieee80211_vif *vif = file->private_data;
|
||||
struct iwl_mvm_vif *mvmvif = iwl_mvm_vif_from_mac80211(vif);
|
||||
struct iwl_mvm *mvm = mvmvif->dbgfs_data;
|
||||
enum iwl_dbgfs_pm_mask param;
|
||||
char buf[32] = {};
|
||||
int val;
|
||||
int ret;
|
||||
|
||||
count = min_t(size_t, count, sizeof(buf) - 1);
|
||||
if (copy_from_user(buf, user_buf, count))
|
||||
return -EFAULT;
|
||||
|
||||
if (!strncmp("keep_alive=", buf, 11)) {
|
||||
if (sscanf(buf + 11, "%d", &val) != 1)
|
||||
return -EINVAL;
|
||||
param = MVM_DEBUGFS_PM_KEEP_ALIVE;
|
||||
} else if (!strncmp("skip_over_dtim=", buf, 15)) {
|
||||
if (sscanf(buf + 15, "%d", &val) != 1)
|
||||
return -EINVAL;
|
||||
param = MVM_DEBUGFS_PM_SKIP_OVER_DTIM;
|
||||
} else if (!strncmp("skip_dtim_periods=", buf, 18)) {
|
||||
if (sscanf(buf + 18, "%d", &val) != 1)
|
||||
return -EINVAL;
|
||||
param = MVM_DEBUGFS_PM_SKIP_DTIM_PERIODS;
|
||||
} else if (!strncmp("rx_data_timeout=", buf, 16)) {
|
||||
if (sscanf(buf + 16, "%d", &val) != 1)
|
||||
return -EINVAL;
|
||||
param = MVM_DEBUGFS_PM_RX_DATA_TIMEOUT;
|
||||
} else if (!strncmp("tx_data_timeout=", buf, 16)) {
|
||||
if (sscanf(buf + 16, "%d", &val) != 1)
|
||||
return -EINVAL;
|
||||
param = MVM_DEBUGFS_PM_TX_DATA_TIMEOUT;
|
||||
} else if (!strncmp("disable_power_off=", buf, 18) &&
|
||||
!(mvm->fw->ucode_capa.flags &
|
||||
IWL_UCODE_TLV_FLAGS_DEVICE_PS_CMD)) {
|
||||
if (sscanf(buf + 18, "%d", &val) != 1)
|
||||
return -EINVAL;
|
||||
param = MVM_DEBUGFS_PM_DISABLE_POWER_OFF;
|
||||
} else if (!strncmp("lprx=", buf, 5)) {
|
||||
if (sscanf(buf + 5, "%d", &val) != 1)
|
||||
return -EINVAL;
|
||||
param = MVM_DEBUGFS_PM_LPRX_ENA;
|
||||
} else if (!strncmp("lprx_rssi_threshold=", buf, 20)) {
|
||||
if (sscanf(buf + 20, "%d", &val) != 1)
|
||||
return -EINVAL;
|
||||
if (val > POWER_LPRX_RSSI_THRESHOLD_MAX || val <
|
||||
POWER_LPRX_RSSI_THRESHOLD_MIN)
|
||||
return -EINVAL;
|
||||
param = MVM_DEBUGFS_PM_LPRX_RSSI_THRESHOLD;
|
||||
} else if (!strncmp("snooze_enable=", buf, 14)) {
|
||||
if (sscanf(buf + 14, "%d", &val) != 1)
|
||||
return -EINVAL;
|
||||
param = MVM_DEBUGFS_PM_SNOOZE_ENABLE;
|
||||
} else {
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
mutex_lock(&mvm->mutex);
|
||||
iwl_dbgfs_update_pm(mvm, vif, param, val);
|
||||
ret = iwl_mvm_power_update_mode(mvm, vif);
|
||||
mutex_unlock(&mvm->mutex);
|
||||
|
||||
return ret ?: count;
|
||||
}
|
||||
|
||||
static ssize_t iwl_dbgfs_pm_params_read(struct file *file,
|
||||
char __user *user_buf,
|
||||
size_t count, loff_t *ppos)
|
||||
{
|
||||
struct ieee80211_vif *vif = file->private_data;
|
||||
struct iwl_mvm_vif *mvmvif = iwl_mvm_vif_from_mac80211(vif);
|
||||
struct iwl_mvm *mvm = mvmvif->dbgfs_data;
|
||||
char buf[512];
|
||||
int bufsz = sizeof(buf);
|
||||
int pos;
|
||||
|
||||
pos = iwl_mvm_power_dbgfs_read(mvm, vif, buf, bufsz);
|
||||
|
||||
return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
|
||||
}
|
||||
|
||||
static ssize_t iwl_dbgfs_mac_params_read(struct file *file,
|
||||
char __user *user_buf,
|
||||
size_t count, loff_t *ppos)
|
||||
{
|
||||
struct ieee80211_vif *vif = file->private_data;
|
||||
struct iwl_mvm_vif *mvmvif = iwl_mvm_vif_from_mac80211(vif);
|
||||
struct iwl_mvm *mvm = mvmvif->dbgfs_data;
|
||||
u8 ap_sta_id;
|
||||
struct ieee80211_chanctx_conf *chanctx_conf;
|
||||
char buf[512];
|
||||
int bufsz = sizeof(buf);
|
||||
int pos = 0;
|
||||
int i;
|
||||
|
||||
mutex_lock(&mvm->mutex);
|
||||
|
||||
ap_sta_id = mvmvif->ap_sta_id;
|
||||
|
||||
pos += scnprintf(buf+pos, bufsz-pos, "mac id/color: %d / %d\n",
|
||||
mvmvif->id, mvmvif->color);
|
||||
pos += scnprintf(buf+pos, bufsz-pos, "bssid: %pM\n",
|
||||
vif->bss_conf.bssid);
|
||||
pos += scnprintf(buf+pos, bufsz-pos, "QoS:\n");
|
||||
for (i = 0; i < ARRAY_SIZE(mvmvif->queue_params); i++) {
|
||||
pos += scnprintf(buf+pos, bufsz-pos,
|
||||
"\t%d: txop:%d - cw_min:%d - cw_max = %d - aifs = %d upasd = %d\n",
|
||||
i, mvmvif->queue_params[i].txop,
|
||||
mvmvif->queue_params[i].cw_min,
|
||||
mvmvif->queue_params[i].cw_max,
|
||||
mvmvif->queue_params[i].aifs,
|
||||
mvmvif->queue_params[i].uapsd);
|
||||
}
|
||||
|
||||
if (vif->type == NL80211_IFTYPE_STATION &&
|
||||
ap_sta_id != IWL_MVM_STATION_COUNT) {
|
||||
struct ieee80211_sta *sta;
|
||||
struct iwl_mvm_sta *mvm_sta;
|
||||
|
||||
sta = rcu_dereference_protected(mvm->fw_id_to_mac_id[ap_sta_id],
|
||||
lockdep_is_held(&mvm->mutex));
|
||||
mvm_sta = (void *)sta->drv_priv;
|
||||
pos += scnprintf(buf+pos, bufsz-pos,
|
||||
"ap_sta_id %d - reduced Tx power %d\n",
|
||||
ap_sta_id, mvm_sta->bt_reduced_txpower);
|
||||
}
|
||||
|
||||
rcu_read_lock();
|
||||
chanctx_conf = rcu_dereference(vif->chanctx_conf);
|
||||
if (chanctx_conf) {
|
||||
pos += scnprintf(buf+pos, bufsz-pos,
|
||||
"idle rx chains %d, active rx chains: %d\n",
|
||||
chanctx_conf->rx_chains_static,
|
||||
chanctx_conf->rx_chains_dynamic);
|
||||
}
|
||||
rcu_read_unlock();
|
||||
|
||||
mutex_unlock(&mvm->mutex);
|
||||
|
||||
return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
|
||||
}
|
||||
|
||||
#define BT_MBOX_MSG(_notif, _num, _field) \
|
||||
((le32_to_cpu((_notif)->mbox_msg[(_num)]) & BT_MBOX##_num##_##_field)\
|
||||
>> BT_MBOX##_num##_##_field##_POS)
|
||||
|
@ -783,11 +539,9 @@ static ssize_t iwl_dbgfs_fw_rx_stats_read(struct file *file,
|
|||
}
|
||||
#undef PRINT_STAT_LE32
|
||||
|
||||
static ssize_t iwl_dbgfs_fw_restart_write(struct file *file,
|
||||
const char __user *user_buf,
|
||||
static ssize_t iwl_dbgfs_fw_restart_write(struct iwl_mvm *mvm, char *buf,
|
||||
size_t count, loff_t *ppos)
|
||||
{
|
||||
struct iwl_mvm *mvm = file->private_data;
|
||||
int ret;
|
||||
|
||||
mutex_lock(&mvm->mutex);
|
||||
|
@ -804,6 +558,14 @@ static ssize_t iwl_dbgfs_fw_restart_write(struct file *file,
|
|||
return count;
|
||||
}
|
||||
|
||||
static ssize_t iwl_dbgfs_fw_nmi_write(struct iwl_mvm *mvm, char *buf,
|
||||
size_t count, loff_t *ppos)
|
||||
{
|
||||
iwl_write_prph(mvm->trans, DEVICE_SET_NMI_REG, 1);
|
||||
|
||||
return count;
|
||||
}
|
||||
|
||||
static ssize_t
|
||||
iwl_dbgfs_scan_ant_rxchain_read(struct file *file,
|
||||
char __user *user_buf,
|
||||
|
@ -828,21 +590,11 @@ iwl_dbgfs_scan_ant_rxchain_read(struct file *file,
|
|||
}
|
||||
|
||||
static ssize_t
|
||||
iwl_dbgfs_scan_ant_rxchain_write(struct file *file,
|
||||
const char __user *user_buf,
|
||||
iwl_dbgfs_scan_ant_rxchain_write(struct iwl_mvm *mvm, char *buf,
|
||||
size_t count, loff_t *ppos)
|
||||
{
|
||||
struct iwl_mvm *mvm = file->private_data;
|
||||
char buf[8];
|
||||
int buf_size;
|
||||
u8 scan_rx_ant;
|
||||
|
||||
memset(buf, 0, sizeof(buf));
|
||||
buf_size = min(count, sizeof(buf) - 1);
|
||||
|
||||
/* get the argument from the user and check if it is valid */
|
||||
if (copy_from_user(buf, user_buf, buf_size))
|
||||
return -EFAULT;
|
||||
if (sscanf(buf, "%hhx", &scan_rx_ant) != 1)
|
||||
return -EINVAL;
|
||||
if (scan_rx_ant > ANT_ABC)
|
||||
|
@ -850,228 +602,17 @@ iwl_dbgfs_scan_ant_rxchain_write(struct file *file,
|
|||
if (scan_rx_ant & ~iwl_fw_valid_rx_ant(mvm->fw))
|
||||
return -EINVAL;
|
||||
|
||||
/* change the rx antennas for scan command */
|
||||
mvm->scan_rx_ant = scan_rx_ant;
|
||||
|
||||
return count;
|
||||
}
|
||||
|
||||
|
||||
static void iwl_dbgfs_update_bf(struct ieee80211_vif *vif,
|
||||
enum iwl_dbgfs_bf_mask param, int value)
|
||||
{
|
||||
struct iwl_mvm_vif *mvmvif = iwl_mvm_vif_from_mac80211(vif);
|
||||
struct iwl_dbgfs_bf *dbgfs_bf = &mvmvif->dbgfs_bf;
|
||||
|
||||
dbgfs_bf->mask |= param;
|
||||
|
||||
switch (param) {
|
||||
case MVM_DEBUGFS_BF_ENERGY_DELTA:
|
||||
dbgfs_bf->bf_energy_delta = value;
|
||||
break;
|
||||
case MVM_DEBUGFS_BF_ROAMING_ENERGY_DELTA:
|
||||
dbgfs_bf->bf_roaming_energy_delta = value;
|
||||
break;
|
||||
case MVM_DEBUGFS_BF_ROAMING_STATE:
|
||||
dbgfs_bf->bf_roaming_state = value;
|
||||
break;
|
||||
case MVM_DEBUGFS_BF_TEMP_THRESHOLD:
|
||||
dbgfs_bf->bf_temp_threshold = value;
|
||||
break;
|
||||
case MVM_DEBUGFS_BF_TEMP_FAST_FILTER:
|
||||
dbgfs_bf->bf_temp_fast_filter = value;
|
||||
break;
|
||||
case MVM_DEBUGFS_BF_TEMP_SLOW_FILTER:
|
||||
dbgfs_bf->bf_temp_slow_filter = value;
|
||||
break;
|
||||
case MVM_DEBUGFS_BF_ENABLE_BEACON_FILTER:
|
||||
dbgfs_bf->bf_enable_beacon_filter = value;
|
||||
break;
|
||||
case MVM_DEBUGFS_BF_DEBUG_FLAG:
|
||||
dbgfs_bf->bf_debug_flag = value;
|
||||
break;
|
||||
case MVM_DEBUGFS_BF_ESCAPE_TIMER:
|
||||
dbgfs_bf->bf_escape_timer = value;
|
||||
break;
|
||||
case MVM_DEBUGFS_BA_ENABLE_BEACON_ABORT:
|
||||
dbgfs_bf->ba_enable_beacon_abort = value;
|
||||
break;
|
||||
case MVM_DEBUGFS_BA_ESCAPE_TIMER:
|
||||
dbgfs_bf->ba_escape_timer = value;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
static ssize_t iwl_dbgfs_bf_params_write(struct file *file,
|
||||
const char __user *user_buf,
|
||||
size_t count, loff_t *ppos)
|
||||
{
|
||||
struct ieee80211_vif *vif = file->private_data;
|
||||
struct iwl_mvm_vif *mvmvif = iwl_mvm_vif_from_mac80211(vif);
|
||||
struct iwl_mvm *mvm = mvmvif->dbgfs_data;
|
||||
enum iwl_dbgfs_bf_mask param;
|
||||
char buf[256];
|
||||
int buf_size;
|
||||
int value;
|
||||
int ret = 0;
|
||||
|
||||
memset(buf, 0, sizeof(buf));
|
||||
buf_size = min(count, sizeof(buf) - 1);
|
||||
if (copy_from_user(buf, user_buf, buf_size))
|
||||
return -EFAULT;
|
||||
|
||||
if (!strncmp("bf_energy_delta=", buf, 16)) {
|
||||
if (sscanf(buf+16, "%d", &value) != 1)
|
||||
return -EINVAL;
|
||||
if (value < IWL_BF_ENERGY_DELTA_MIN ||
|
||||
value > IWL_BF_ENERGY_DELTA_MAX)
|
||||
return -EINVAL;
|
||||
param = MVM_DEBUGFS_BF_ENERGY_DELTA;
|
||||
} else if (!strncmp("bf_roaming_energy_delta=", buf, 24)) {
|
||||
if (sscanf(buf+24, "%d", &value) != 1)
|
||||
return -EINVAL;
|
||||
if (value < IWL_BF_ROAMING_ENERGY_DELTA_MIN ||
|
||||
value > IWL_BF_ROAMING_ENERGY_DELTA_MAX)
|
||||
return -EINVAL;
|
||||
param = MVM_DEBUGFS_BF_ROAMING_ENERGY_DELTA;
|
||||
} else if (!strncmp("bf_roaming_state=", buf, 17)) {
|
||||
if (sscanf(buf+17, "%d", &value) != 1)
|
||||
return -EINVAL;
|
||||
if (value < IWL_BF_ROAMING_STATE_MIN ||
|
||||
value > IWL_BF_ROAMING_STATE_MAX)
|
||||
return -EINVAL;
|
||||
param = MVM_DEBUGFS_BF_ROAMING_STATE;
|
||||
} else if (!strncmp("bf_temp_threshold=", buf, 18)) {
|
||||
if (sscanf(buf+18, "%d", &value) != 1)
|
||||
return -EINVAL;
|
||||
if (value < IWL_BF_TEMP_THRESHOLD_MIN ||
|
||||
value > IWL_BF_TEMP_THRESHOLD_MAX)
|
||||
return -EINVAL;
|
||||
param = MVM_DEBUGFS_BF_TEMP_THRESHOLD;
|
||||
} else if (!strncmp("bf_temp_fast_filter=", buf, 20)) {
|
||||
if (sscanf(buf+20, "%d", &value) != 1)
|
||||
return -EINVAL;
|
||||
if (value < IWL_BF_TEMP_FAST_FILTER_MIN ||
|
||||
value > IWL_BF_TEMP_FAST_FILTER_MAX)
|
||||
return -EINVAL;
|
||||
param = MVM_DEBUGFS_BF_TEMP_FAST_FILTER;
|
||||
} else if (!strncmp("bf_temp_slow_filter=", buf, 20)) {
|
||||
if (sscanf(buf+20, "%d", &value) != 1)
|
||||
return -EINVAL;
|
||||
if (value < IWL_BF_TEMP_SLOW_FILTER_MIN ||
|
||||
value > IWL_BF_TEMP_SLOW_FILTER_MAX)
|
||||
return -EINVAL;
|
||||
param = MVM_DEBUGFS_BF_TEMP_SLOW_FILTER;
|
||||
} else if (!strncmp("bf_enable_beacon_filter=", buf, 24)) {
|
||||
if (sscanf(buf+24, "%d", &value) != 1)
|
||||
return -EINVAL;
|
||||
if (value < 0 || value > 1)
|
||||
return -EINVAL;
|
||||
param = MVM_DEBUGFS_BF_ENABLE_BEACON_FILTER;
|
||||
} else if (!strncmp("bf_debug_flag=", buf, 14)) {
|
||||
if (sscanf(buf+14, "%d", &value) != 1)
|
||||
return -EINVAL;
|
||||
if (value < 0 || value > 1)
|
||||
return -EINVAL;
|
||||
param = MVM_DEBUGFS_BF_DEBUG_FLAG;
|
||||
} else if (!strncmp("bf_escape_timer=", buf, 16)) {
|
||||
if (sscanf(buf+16, "%d", &value) != 1)
|
||||
return -EINVAL;
|
||||
if (value < IWL_BF_ESCAPE_TIMER_MIN ||
|
||||
value > IWL_BF_ESCAPE_TIMER_MAX)
|
||||
return -EINVAL;
|
||||
param = MVM_DEBUGFS_BF_ESCAPE_TIMER;
|
||||
} else if (!strncmp("ba_escape_timer=", buf, 16)) {
|
||||
if (sscanf(buf+16, "%d", &value) != 1)
|
||||
return -EINVAL;
|
||||
if (value < IWL_BA_ESCAPE_TIMER_MIN ||
|
||||
value > IWL_BA_ESCAPE_TIMER_MAX)
|
||||
return -EINVAL;
|
||||
param = MVM_DEBUGFS_BA_ESCAPE_TIMER;
|
||||
} else if (!strncmp("ba_enable_beacon_abort=", buf, 23)) {
|
||||
if (sscanf(buf+23, "%d", &value) != 1)
|
||||
return -EINVAL;
|
||||
if (value < 0 || value > 1)
|
||||
return -EINVAL;
|
||||
param = MVM_DEBUGFS_BA_ENABLE_BEACON_ABORT;
|
||||
} else {
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
mutex_lock(&mvm->mutex);
|
||||
iwl_dbgfs_update_bf(vif, param, value);
|
||||
if (param == MVM_DEBUGFS_BF_ENABLE_BEACON_FILTER && !value) {
|
||||
ret = iwl_mvm_disable_beacon_filter(mvm, vif);
|
||||
} else {
|
||||
ret = iwl_mvm_enable_beacon_filter(mvm, vif);
|
||||
}
|
||||
mutex_unlock(&mvm->mutex);
|
||||
|
||||
return ret ?: count;
|
||||
}
|
||||
|
||||
static ssize_t iwl_dbgfs_bf_params_read(struct file *file,
|
||||
char __user *user_buf,
|
||||
size_t count, loff_t *ppos)
|
||||
{
|
||||
struct ieee80211_vif *vif = file->private_data;
|
||||
struct iwl_mvm_vif *mvmvif = iwl_mvm_vif_from_mac80211(vif);
|
||||
char buf[256];
|
||||
int pos = 0;
|
||||
const size_t bufsz = sizeof(buf);
|
||||
struct iwl_beacon_filter_cmd cmd = {
|
||||
IWL_BF_CMD_CONFIG_DEFAULTS,
|
||||
.bf_enable_beacon_filter =
|
||||
cpu_to_le32(IWL_BF_ENABLE_BEACON_FILTER_DEFAULT),
|
||||
.ba_enable_beacon_abort =
|
||||
cpu_to_le32(IWL_BA_ENABLE_BEACON_ABORT_DEFAULT),
|
||||
};
|
||||
|
||||
iwl_mvm_beacon_filter_debugfs_parameters(vif, &cmd);
|
||||
if (mvmvif->bf_data.bf_enabled)
|
||||
cmd.bf_enable_beacon_filter = cpu_to_le32(1);
|
||||
else
|
||||
cmd.bf_enable_beacon_filter = 0;
|
||||
|
||||
pos += scnprintf(buf+pos, bufsz-pos, "bf_energy_delta = %d\n",
|
||||
le32_to_cpu(cmd.bf_energy_delta));
|
||||
pos += scnprintf(buf+pos, bufsz-pos, "bf_roaming_energy_delta = %d\n",
|
||||
le32_to_cpu(cmd.bf_roaming_energy_delta));
|
||||
pos += scnprintf(buf+pos, bufsz-pos, "bf_roaming_state = %d\n",
|
||||
le32_to_cpu(cmd.bf_roaming_state));
|
||||
pos += scnprintf(buf+pos, bufsz-pos, "bf_temp_threshold = %d\n",
|
||||
le32_to_cpu(cmd.bf_temp_threshold));
|
||||
pos += scnprintf(buf+pos, bufsz-pos, "bf_temp_fast_filter = %d\n",
|
||||
le32_to_cpu(cmd.bf_temp_fast_filter));
|
||||
pos += scnprintf(buf+pos, bufsz-pos, "bf_temp_slow_filter = %d\n",
|
||||
le32_to_cpu(cmd.bf_temp_slow_filter));
|
||||
pos += scnprintf(buf+pos, bufsz-pos, "bf_enable_beacon_filter = %d\n",
|
||||
le32_to_cpu(cmd.bf_enable_beacon_filter));
|
||||
pos += scnprintf(buf+pos, bufsz-pos, "bf_debug_flag = %d\n",
|
||||
le32_to_cpu(cmd.bf_debug_flag));
|
||||
pos += scnprintf(buf+pos, bufsz-pos, "bf_escape_timer = %d\n",
|
||||
le32_to_cpu(cmd.bf_escape_timer));
|
||||
pos += scnprintf(buf+pos, bufsz-pos, "ba_escape_timer = %d\n",
|
||||
le32_to_cpu(cmd.ba_escape_timer));
|
||||
pos += scnprintf(buf+pos, bufsz-pos, "ba_enable_beacon_abort = %d\n",
|
||||
le32_to_cpu(cmd.ba_enable_beacon_abort));
|
||||
|
||||
return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
static ssize_t iwl_dbgfs_d3_sram_write(struct file *file,
|
||||
const char __user *user_buf,
|
||||
static ssize_t iwl_dbgfs_d3_sram_write(struct iwl_mvm *mvm, char *buf,
|
||||
size_t count, loff_t *ppos)
|
||||
{
|
||||
struct iwl_mvm *mvm = file->private_data;
|
||||
char buf[8] = {};
|
||||
int store;
|
||||
|
||||
count = min_t(size_t, count, sizeof(buf) - 1);
|
||||
if (copy_from_user(buf, user_buf, count))
|
||||
return -EFAULT;
|
||||
|
||||
if (sscanf(buf, "%d", &store) != 1)
|
||||
return -EINVAL;
|
||||
|
||||
|
@ -1124,61 +665,33 @@ static ssize_t iwl_dbgfs_d3_sram_read(struct file *file, char __user *user_buf,
|
|||
}
|
||||
#endif
|
||||
|
||||
#define MVM_DEBUGFS_READ_FILE_OPS(name) \
|
||||
static const struct file_operations iwl_dbgfs_##name##_ops = { \
|
||||
.read = iwl_dbgfs_##name##_read, \
|
||||
.open = simple_open, \
|
||||
.llseek = generic_file_llseek, \
|
||||
}
|
||||
|
||||
#define MVM_DEBUGFS_READ_WRITE_FILE_OPS(name) \
|
||||
static const struct file_operations iwl_dbgfs_##name##_ops = { \
|
||||
.write = iwl_dbgfs_##name##_write, \
|
||||
.read = iwl_dbgfs_##name##_read, \
|
||||
.open = simple_open, \
|
||||
.llseek = generic_file_llseek, \
|
||||
};
|
||||
|
||||
#define MVM_DEBUGFS_WRITE_FILE_OPS(name) \
|
||||
static const struct file_operations iwl_dbgfs_##name##_ops = { \
|
||||
.write = iwl_dbgfs_##name##_write, \
|
||||
.open = simple_open, \
|
||||
.llseek = generic_file_llseek, \
|
||||
};
|
||||
|
||||
#define MVM_DEBUGFS_WRITE_FILE_OPS(name, bufsz) \
|
||||
_MVM_DEBUGFS_WRITE_FILE_OPS(name, bufsz, struct iwl_mvm)
|
||||
#define MVM_DEBUGFS_READ_WRITE_FILE_OPS(name, bufsz) \
|
||||
_MVM_DEBUGFS_READ_WRITE_FILE_OPS(name, bufsz, struct iwl_mvm)
|
||||
#define MVM_DEBUGFS_ADD_FILE(name, parent, mode) do { \
|
||||
if (!debugfs_create_file(#name, mode, parent, mvm, \
|
||||
&iwl_dbgfs_##name##_ops)) \
|
||||
goto err; \
|
||||
} while (0)
|
||||
|
||||
#define MVM_DEBUGFS_ADD_FILE_VIF(name, parent, mode) do { \
|
||||
if (!debugfs_create_file(#name, mode, parent, vif, \
|
||||
&iwl_dbgfs_##name##_ops)) \
|
||||
goto err; \
|
||||
} while (0)
|
||||
|
||||
/* Device wide debugfs entries */
|
||||
MVM_DEBUGFS_WRITE_FILE_OPS(tx_flush);
|
||||
MVM_DEBUGFS_WRITE_FILE_OPS(sta_drain);
|
||||
MVM_DEBUGFS_READ_WRITE_FILE_OPS(sram);
|
||||
MVM_DEBUGFS_WRITE_FILE_OPS(tx_flush, 16);
|
||||
MVM_DEBUGFS_WRITE_FILE_OPS(sta_drain, 8);
|
||||
MVM_DEBUGFS_READ_WRITE_FILE_OPS(sram, 64);
|
||||
MVM_DEBUGFS_READ_FILE_OPS(stations);
|
||||
MVM_DEBUGFS_READ_FILE_OPS(bt_notif);
|
||||
MVM_DEBUGFS_READ_FILE_OPS(bt_cmd);
|
||||
MVM_DEBUGFS_READ_WRITE_FILE_OPS(disable_power_off);
|
||||
MVM_DEBUGFS_READ_WRITE_FILE_OPS(disable_power_off, 64);
|
||||
MVM_DEBUGFS_READ_FILE_OPS(fw_rx_stats);
|
||||
MVM_DEBUGFS_WRITE_FILE_OPS(fw_restart);
|
||||
MVM_DEBUGFS_READ_WRITE_FILE_OPS(scan_ant_rxchain);
|
||||
MVM_DEBUGFS_WRITE_FILE_OPS(fw_restart, 10);
|
||||
MVM_DEBUGFS_WRITE_FILE_OPS(fw_nmi, 10);
|
||||
MVM_DEBUGFS_READ_WRITE_FILE_OPS(scan_ant_rxchain, 8);
|
||||
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
MVM_DEBUGFS_READ_WRITE_FILE_OPS(d3_sram);
|
||||
MVM_DEBUGFS_READ_WRITE_FILE_OPS(d3_sram, 8);
|
||||
#endif
|
||||
|
||||
/* Interface specific debugfs entries */
|
||||
MVM_DEBUGFS_READ_FILE_OPS(mac_params);
|
||||
MVM_DEBUGFS_READ_WRITE_FILE_OPS(pm_params);
|
||||
MVM_DEBUGFS_READ_WRITE_FILE_OPS(bf_params);
|
||||
|
||||
int iwl_mvm_dbgfs_register(struct iwl_mvm *mvm, struct dentry *dbgfs_dir)
|
||||
{
|
||||
char buf[100];
|
||||
|
@ -1196,6 +709,7 @@ int iwl_mvm_dbgfs_register(struct iwl_mvm *mvm, struct dentry *dbgfs_dir)
|
|||
S_IRUSR | S_IWUSR);
|
||||
MVM_DEBUGFS_ADD_FILE(fw_rx_stats, mvm->debugfs_dir, S_IRUSR);
|
||||
MVM_DEBUGFS_ADD_FILE(fw_restart, mvm->debugfs_dir, S_IWUSR);
|
||||
MVM_DEBUGFS_ADD_FILE(fw_nmi, mvm->debugfs_dir, S_IWUSR);
|
||||
MVM_DEBUGFS_ADD_FILE(scan_ant_rxchain, mvm->debugfs_dir,
|
||||
S_IWUSR | S_IRUSR);
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
|
@ -1206,6 +720,19 @@ int iwl_mvm_dbgfs_register(struct iwl_mvm *mvm, struct dentry *dbgfs_dir)
|
|||
goto err;
|
||||
#endif
|
||||
|
||||
if (!debugfs_create_blob("nvm_hw", S_IRUSR,
|
||||
mvm->debugfs_dir, &mvm->nvm_hw_blob))
|
||||
goto err;
|
||||
if (!debugfs_create_blob("nvm_sw", S_IRUSR,
|
||||
mvm->debugfs_dir, &mvm->nvm_sw_blob))
|
||||
goto err;
|
||||
if (!debugfs_create_blob("nvm_calib", S_IRUSR,
|
||||
mvm->debugfs_dir, &mvm->nvm_calib_blob))
|
||||
goto err;
|
||||
if (!debugfs_create_blob("nvm_prod", S_IRUSR,
|
||||
mvm->debugfs_dir, &mvm->nvm_prod_blob))
|
||||
goto err;
|
||||
|
||||
/*
|
||||
* Create a symlink with mac80211. It will be removed when mac80211
|
||||
* exists (before the opmode exists which removes the target.)
|
||||
|
@ -1221,72 +748,3 @@ int iwl_mvm_dbgfs_register(struct iwl_mvm *mvm, struct dentry *dbgfs_dir)
|
|||
IWL_ERR(mvm, "Can't create the mvm debugfs directory\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
void iwl_mvm_vif_dbgfs_register(struct iwl_mvm *mvm, struct ieee80211_vif *vif)
|
||||
{
|
||||
struct dentry *dbgfs_dir = vif->debugfs_dir;
|
||||
struct iwl_mvm_vif *mvmvif = iwl_mvm_vif_from_mac80211(vif);
|
||||
char buf[100];
|
||||
|
||||
/*
|
||||
* Check if debugfs directory already exist before creating it.
|
||||
* This may happen when, for example, resetting hw or suspend-resume
|
||||
*/
|
||||
if (!dbgfs_dir || mvmvif->dbgfs_dir)
|
||||
return;
|
||||
|
||||
mvmvif->dbgfs_dir = debugfs_create_dir("iwlmvm", dbgfs_dir);
|
||||
mvmvif->dbgfs_data = mvm;
|
||||
|
||||
if (!mvmvif->dbgfs_dir) {
|
||||
IWL_ERR(mvm, "Failed to create debugfs directory under %s\n",
|
||||
dbgfs_dir->d_name.name);
|
||||
return;
|
||||
}
|
||||
|
||||
if (iwlmvm_mod_params.power_scheme != IWL_POWER_SCHEME_CAM &&
|
||||
vif->type == NL80211_IFTYPE_STATION && !vif->p2p)
|
||||
MVM_DEBUGFS_ADD_FILE_VIF(pm_params, mvmvif->dbgfs_dir, S_IWUSR |
|
||||
S_IRUSR);
|
||||
|
||||
MVM_DEBUGFS_ADD_FILE_VIF(mac_params, mvmvif->dbgfs_dir,
|
||||
S_IRUSR);
|
||||
|
||||
if (vif->type == NL80211_IFTYPE_STATION && !vif->p2p &&
|
||||
mvmvif == mvm->bf_allowed_vif)
|
||||
MVM_DEBUGFS_ADD_FILE_VIF(bf_params, mvmvif->dbgfs_dir,
|
||||
S_IRUSR | S_IWUSR);
|
||||
|
||||
/*
|
||||
* Create symlink for convenience pointing to interface specific
|
||||
* debugfs entries for the driver. For example, under
|
||||
* /sys/kernel/debug/iwlwifi/0000\:02\:00.0/iwlmvm/
|
||||
* find
|
||||
* netdev:wlan0 -> ../../../ieee80211/phy0/netdev:wlan0/iwlmvm/
|
||||
*/
|
||||
snprintf(buf, 100, "../../../%s/%s/%s/%s",
|
||||
dbgfs_dir->d_parent->d_parent->d_name.name,
|
||||
dbgfs_dir->d_parent->d_name.name,
|
||||
dbgfs_dir->d_name.name,
|
||||
mvmvif->dbgfs_dir->d_name.name);
|
||||
|
||||
mvmvif->dbgfs_slink = debugfs_create_symlink(dbgfs_dir->d_name.name,
|
||||
mvm->debugfs_dir, buf);
|
||||
if (!mvmvif->dbgfs_slink)
|
||||
IWL_ERR(mvm, "Can't create debugfs symbolic link under %s\n",
|
||||
dbgfs_dir->d_name.name);
|
||||
return;
|
||||
err:
|
||||
IWL_ERR(mvm, "Can't create debugfs entity\n");
|
||||
}
|
||||
|
||||
void iwl_mvm_vif_dbgfs_clean(struct iwl_mvm *mvm, struct ieee80211_vif *vif)
|
||||
{
|
||||
struct iwl_mvm_vif *mvmvif = iwl_mvm_vif_from_mac80211(vif);
|
||||
|
||||
debugfs_remove(mvmvif->dbgfs_slink);
|
||||
mvmvif->dbgfs_slink = NULL;
|
||||
|
||||
debugfs_remove_recursive(mvmvif->dbgfs_dir);
|
||||
mvmvif->dbgfs_dir = NULL;
|
||||
}
|
||||
|
|
101
drivers/net/wireless/iwlwifi/mvm/debugfs.h
Normal file
101
drivers/net/wireless/iwlwifi/mvm/debugfs.h
Normal file
|
@ -0,0 +1,101 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* This file is provided under a dual BSD/GPLv2 license. When using or
|
||||
* redistributing this file, you may do so under either license.
|
||||
*
|
||||
* GPL LICENSE SUMMARY
|
||||
*
|
||||
* Copyright(c) 2012 - 2013 Intel Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but
|
||||
* WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
* General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
|
||||
* USA
|
||||
*
|
||||
* The full GNU General Public License is included in this distribution
|
||||
* in the file called COPYING.
|
||||
*
|
||||
* Contact Information:
|
||||
* Intel Linux Wireless <ilw@linux.intel.com>
|
||||
* Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
|
||||
*
|
||||
* BSD LICENSE
|
||||
*
|
||||
* Copyright(c) 2012 - 2013 Intel Corporation. All rights reserved.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* * Neither the name Intel Corporation nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
#define MVM_DEBUGFS_READ_FILE_OPS(name) \
|
||||
static const struct file_operations iwl_dbgfs_##name##_ops = { \
|
||||
.read = iwl_dbgfs_##name##_read, \
|
||||
.open = simple_open, \
|
||||
.llseek = generic_file_llseek, \
|
||||
}
|
||||
|
||||
#define MVM_DEBUGFS_WRITE_WRAPPER(name, buflen, argtype) \
|
||||
static ssize_t _iwl_dbgfs_##name##_write(struct file *file, \
|
||||
const char __user *user_buf, \
|
||||
size_t count, loff_t *ppos) \
|
||||
{ \
|
||||
argtype *arg = file->private_data; \
|
||||
char buf[buflen] = {}; \
|
||||
size_t buf_size = min(count, sizeof(buf) - 1); \
|
||||
\
|
||||
if (copy_from_user(buf, user_buf, buf_size)) \
|
||||
return -EFAULT; \
|
||||
\
|
||||
return iwl_dbgfs_##name##_write(arg, buf, buf_size, ppos); \
|
||||
} \
|
||||
|
||||
#define _MVM_DEBUGFS_READ_WRITE_FILE_OPS(name, buflen, argtype) \
|
||||
MVM_DEBUGFS_WRITE_WRAPPER(name, buflen, argtype) \
|
||||
static const struct file_operations iwl_dbgfs_##name##_ops = { \
|
||||
.write = _iwl_dbgfs_##name##_write, \
|
||||
.read = iwl_dbgfs_##name##_read, \
|
||||
.open = simple_open, \
|
||||
.llseek = generic_file_llseek, \
|
||||
};
|
||||
|
||||
#define _MVM_DEBUGFS_WRITE_FILE_OPS(name, buflen, argtype) \
|
||||
MVM_DEBUGFS_WRITE_WRAPPER(name, buflen, argtype) \
|
||||
static const struct file_operations iwl_dbgfs_##name##_ops = { \
|
||||
.write = _iwl_dbgfs_##name##_write, \
|
||||
.open = simple_open, \
|
||||
.llseek = generic_file_llseek, \
|
||||
};
|
|
@ -127,6 +127,7 @@ enum iwl_bt_coex_valid_bit_msk {
|
|||
BT_VALID_ANT_ISOLATION_THRS = BIT(15),
|
||||
BT_VALID_TXTX_DELTA_FREQ_THRS = BIT(16),
|
||||
BT_VALID_TXRX_MAX_FREQ_0 = BIT(17),
|
||||
BT_VALID_SYNC_TO_SCO = BIT(18),
|
||||
};
|
||||
|
||||
/**
|
||||
|
|
|
@ -281,8 +281,31 @@ enum {
|
|||
/* # entries in rate scale table to support Tx retries */
|
||||
#define LQ_MAX_RETRY_NUM 16
|
||||
|
||||
/* Link quality command flags, only this one is available */
|
||||
#define LQ_FLAG_SET_STA_TLC_RTS_MSK BIT(0)
|
||||
/* Link quality command flags bit fields */
|
||||
|
||||
/* Bit 0: (0) Don't use RTS (1) Use RTS */
|
||||
#define LQ_FLAG_USE_RTS_POS 0
|
||||
#define LQ_FLAG_USE_RTS_MSK (1 << LQ_FLAG_USE_RTS_POS)
|
||||
|
||||
/* Bit 1-3: LQ command color. Used to match responses to LQ commands */
|
||||
#define LQ_FLAG_COLOR_POS 1
|
||||
#define LQ_FLAG_COLOR_MSK (7 << LQ_FLAG_COLOR_POS)
|
||||
|
||||
/* Bit 4-5: Tx RTS BW Signalling
|
||||
* (0) No RTS BW signalling
|
||||
* (1) Static BW signalling
|
||||
* (2) Dynamic BW signalling
|
||||
*/
|
||||
#define LQ_FLAG_RTS_BW_SIG_POS 4
|
||||
#define LQ_FLAG_RTS_BW_SIG_NONE (0 << LQ_FLAG_RTS_BW_SIG_POS)
|
||||
#define LQ_FLAG_RTS_BW_SIG_STATIC (1 << LQ_FLAG_RTS_BW_SIG_POS)
|
||||
#define LQ_FLAG_RTS_BW_SIG_DYNAMIC (2 << LQ_FLAG_RTS_BW_SIG_POS)
|
||||
|
||||
/* Bit 6: (0) No dynamic BW selection (1) Allow dynamic BW selection
|
||||
* Dyanmic BW selection allows Tx with narrower BW then requested in rates
|
||||
*/
|
||||
#define LQ_FLAG_DYNAMIC_BW_POS 6
|
||||
#define LQ_FLAG_DYNAMIC_BW_MSK (1 << LQ_FLAG_DYNAMIC_BW_POS)
|
||||
|
||||
/**
|
||||
* struct iwl_lq_cmd - link quality command
|
||||
|
|
|
@ -530,14 +530,13 @@ struct iwl_scan_offload_schedule {
|
|||
/*
|
||||
* iwl_scan_offload_flags
|
||||
*
|
||||
* IWL_SCAN_OFFLOAD_FLAG_FILTER_SSID: filter mode - upload every beacon or match
|
||||
* ssid list.
|
||||
* IWL_SCAN_OFFLOAD_FLAG_PASS_ALL: pass all results - no filtering.
|
||||
* IWL_SCAN_OFFLOAD_FLAG_CACHED_CHANNEL: add cached channels to partial scan.
|
||||
* IWL_SCAN_OFFLOAD_FLAG_ENERGY_SCAN: use energy based scan before partial scan
|
||||
* on A band.
|
||||
*/
|
||||
enum iwl_scan_offload_flags {
|
||||
IWL_SCAN_OFFLOAD_FLAG_FILTER_SSID = BIT(0),
|
||||
IWL_SCAN_OFFLOAD_FLAG_PASS_ALL = BIT(0),
|
||||
IWL_SCAN_OFFLOAD_FLAG_CACHED_CHANNEL = BIT(2),
|
||||
IWL_SCAN_OFFLOAD_FLAG_ENERGY_SCAN = BIT(3),
|
||||
};
|
||||
|
|
|
@ -488,6 +488,40 @@ static void iwl_mvm_ack_rates(struct iwl_mvm *mvm,
|
|||
*ofdm_rates = ofdm;
|
||||
}
|
||||
|
||||
static void iwl_mvm_mac_ctxt_set_ht_flags(struct iwl_mvm *mvm,
|
||||
struct ieee80211_vif *vif,
|
||||
struct iwl_mac_ctx_cmd *cmd)
|
||||
{
|
||||
/* for both sta and ap, ht_operation_mode hold the protection_mode */
|
||||
u8 protection_mode = vif->bss_conf.ht_operation_mode &
|
||||
IEEE80211_HT_OP_MODE_PROTECTION;
|
||||
/* The fw does not distinguish between ht and fat */
|
||||
u32 ht_flag = MAC_PROT_FLG_HT_PROT | MAC_PROT_FLG_FAT_PROT;
|
||||
|
||||
IWL_DEBUG_RATE(mvm, "protection mode set to %d\n", protection_mode);
|
||||
/*
|
||||
* See section 9.23.3.1 of IEEE 80211-2012.
|
||||
* Nongreenfield HT STAs Present is not supported.
|
||||
*/
|
||||
switch (protection_mode) {
|
||||
case IEEE80211_HT_OP_MODE_PROTECTION_NONE:
|
||||
break;
|
||||
case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER:
|
||||
case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
|
||||
cmd->protection_flags |= cpu_to_le32(ht_flag);
|
||||
break;
|
||||
case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
|
||||
/* Protect when channel wider than 20MHz */
|
||||
if (vif->bss_conf.chandef.width > NL80211_CHAN_WIDTH_20)
|
||||
cmd->protection_flags |= cpu_to_le32(ht_flag);
|
||||
break;
|
||||
default:
|
||||
IWL_ERR(mvm, "Illegal protection mode %d\n",
|
||||
protection_mode);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
static void iwl_mvm_mac_ctxt_cmd_common(struct iwl_mvm *mvm,
|
||||
struct ieee80211_vif *vif,
|
||||
struct iwl_mac_ctx_cmd *cmd,
|
||||
|
@ -495,6 +529,8 @@ static void iwl_mvm_mac_ctxt_cmd_common(struct iwl_mvm *mvm,
|
|||
{
|
||||
struct iwl_mvm_vif *mvmvif = iwl_mvm_vif_from_mac80211(vif);
|
||||
struct ieee80211_chanctx_conf *chanctx;
|
||||
bool ht_enabled = !!(vif->bss_conf.ht_operation_mode &
|
||||
IEEE80211_HT_OP_MODE_PROTECTION);
|
||||
u8 cck_ack_rates, ofdm_ack_rates;
|
||||
int i;
|
||||
|
||||
|
@ -573,16 +609,13 @@ static void iwl_mvm_mac_ctxt_cmd_common(struct iwl_mvm *mvm,
|
|||
cmd->protection_flags |=
|
||||
cpu_to_le32(MAC_PROT_FLG_SELF_CTS_EN);
|
||||
}
|
||||
|
||||
/*
|
||||
* I think that we should enable these 2 flags regardless the HT PROT
|
||||
* fields in the HT IE, but I am not sure. Someone knows whom to ask?...
|
||||
*/
|
||||
if (vif->bss_conf.chandef.width != NL80211_CHAN_WIDTH_20_NOHT) {
|
||||
IWL_DEBUG_RATE(mvm, "use_cts_prot %d, ht_operation_mode %d\n",
|
||||
vif->bss_conf.use_cts_prot,
|
||||
vif->bss_conf.ht_operation_mode);
|
||||
if (vif->bss_conf.chandef.width != NL80211_CHAN_WIDTH_20_NOHT)
|
||||
cmd->qos_flags |= cpu_to_le32(MAC_QOS_FLG_TGN);
|
||||
cmd->protection_flags |= cpu_to_le32(MAC_PROT_FLG_HT_PROT |
|
||||
MAC_PROT_FLG_FAT_PROT);
|
||||
}
|
||||
if (ht_enabled)
|
||||
iwl_mvm_mac_ctxt_set_ht_flags(mvm, vif, cmd);
|
||||
|
||||
cmd->filter_flags = cpu_to_le32(MAC_FILTER_ACCEPT_GRP);
|
||||
}
|
||||
|
|
|
@ -256,7 +256,8 @@ int iwl_mvm_mac_setup_register(struct iwl_mvm *mvm)
|
|||
}
|
||||
|
||||
hw->wiphy->features |= NL80211_FEATURE_P2P_GO_CTWIN |
|
||||
NL80211_FEATURE_P2P_GO_OPPPS;
|
||||
NL80211_FEATURE_P2P_GO_OPPPS |
|
||||
NL80211_FEATURE_LOW_PRIORITY_SCAN;
|
||||
|
||||
mvm->rts_threshold = IEEE80211_MAX_RTS_THRESHOLD;
|
||||
|
||||
|
@ -990,6 +991,17 @@ iwl_mvm_bss_info_changed_ap_ibss(struct iwl_mvm *mvm,
|
|||
struct ieee80211_bss_conf *bss_conf,
|
||||
u32 changes)
|
||||
{
|
||||
enum ieee80211_bss_change ht_change = BSS_CHANGED_ERP_CTS_PROT |
|
||||
BSS_CHANGED_HT |
|
||||
BSS_CHANGED_BANDWIDTH;
|
||||
int ret;
|
||||
|
||||
if (changes & ht_change) {
|
||||
ret = iwl_mvm_mac_ctxt_changed(mvm, vif);
|
||||
if (ret)
|
||||
IWL_ERR(mvm, "failed to update MAC %pM\n", vif->addr);
|
||||
}
|
||||
|
||||
/* Need to send a new beacon template to the FW */
|
||||
if (changes & BSS_CHANGED_BEACON) {
|
||||
if (iwl_mvm_mac_ctxt_beacon_changed(mvm, vif))
|
||||
|
@ -1080,7 +1092,7 @@ static void iwl_mvm_mac_sta_notify(struct ieee80211_hw *hw,
|
|||
struct ieee80211_sta *sta)
|
||||
{
|
||||
struct iwl_mvm *mvm = IWL_MAC80211_GET_MVM(hw);
|
||||
struct iwl_mvm_sta *mvmsta = (void *)sta->drv_priv;
|
||||
struct iwl_mvm_sta *mvmsta = iwl_mvm_sta_from_mac80211(sta);
|
||||
|
||||
switch (cmd) {
|
||||
case STA_NOTIFY_SLEEP:
|
||||
|
@ -1149,7 +1161,8 @@ static int iwl_mvm_mac_sta_state(struct ieee80211_hw *hw,
|
|||
ret = iwl_mvm_update_sta(mvm, vif, sta);
|
||||
if (ret == 0)
|
||||
iwl_mvm_rs_rate_init(mvm, sta,
|
||||
mvmvif->phy_ctxt->channel->band);
|
||||
mvmvif->phy_ctxt->channel->band,
|
||||
true);
|
||||
} else if (old_state == IEEE80211_STA_ASSOC &&
|
||||
new_state == IEEE80211_STA_AUTHORIZED) {
|
||||
/* enable beacon filtering */
|
||||
|
|
|
@ -323,9 +323,9 @@ struct iwl_mvm_vif {
|
|||
#endif
|
||||
|
||||
#ifdef CONFIG_IWLWIFI_DEBUGFS
|
||||
struct iwl_mvm *mvm;
|
||||
struct dentry *dbgfs_dir;
|
||||
struct dentry *dbgfs_slink;
|
||||
void *dbgfs_data;
|
||||
struct iwl_dbgfs_pm dbgfs_pm;
|
||||
struct iwl_dbgfs_bf dbgfs_bf;
|
||||
#endif
|
||||
|
@ -494,6 +494,11 @@ struct iwl_mvm {
|
|||
u32 dbgfs_sram_offset, dbgfs_sram_len;
|
||||
bool disable_power_off;
|
||||
bool disable_power_off_d3;
|
||||
|
||||
struct debugfs_blob_wrapper nvm_hw_blob;
|
||||
struct debugfs_blob_wrapper nvm_sw_blob;
|
||||
struct debugfs_blob_wrapper nvm_calib_blob;
|
||||
struct debugfs_blob_wrapper nvm_prod_blob;
|
||||
#endif
|
||||
|
||||
struct iwl_mvm_phy_ctxt phy_ctxts[NUM_PHY_CTX];
|
||||
|
@ -531,6 +536,7 @@ struct iwl_mvm {
|
|||
bool store_d3_resume_sram;
|
||||
void *d3_resume_sram;
|
||||
u32 d3_test_pme_ptr;
|
||||
struct ieee80211_vif *keep_vif;
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
@ -750,8 +756,7 @@ iwl_mvm_vif_dbgfs_clean(struct iwl_mvm *mvm, struct ieee80211_vif *vif)
|
|||
#endif /* CONFIG_IWLWIFI_DEBUGFS */
|
||||
|
||||
/* rate scaling */
|
||||
int iwl_mvm_send_lq_cmd(struct iwl_mvm *mvm, struct iwl_lq_cmd *lq,
|
||||
u8 flags, bool init);
|
||||
int iwl_mvm_send_lq_cmd(struct iwl_mvm *mvm, struct iwl_lq_cmd *lq, bool init);
|
||||
|
||||
/* power managment */
|
||||
static inline int iwl_mvm_power_update_mode(struct iwl_mvm *mvm,
|
||||
|
|
|
@ -443,6 +443,29 @@ int iwl_nvm_init(struct iwl_mvm *mvm)
|
|||
}
|
||||
mvm->nvm_sections[section].data = temp;
|
||||
mvm->nvm_sections[section].length = ret;
|
||||
|
||||
#ifdef CONFIG_IWLWIFI_DEBUGFS
|
||||
switch (section) {
|
||||
case NVM_SECTION_TYPE_HW:
|
||||
mvm->nvm_hw_blob.data = temp;
|
||||
mvm->nvm_hw_blob.size = ret;
|
||||
break;
|
||||
case NVM_SECTION_TYPE_SW:
|
||||
mvm->nvm_sw_blob.data = temp;
|
||||
mvm->nvm_sw_blob.size = ret;
|
||||
break;
|
||||
case NVM_SECTION_TYPE_CALIBRATION:
|
||||
mvm->nvm_calib_blob.data = temp;
|
||||
mvm->nvm_calib_blob.size = ret;
|
||||
break;
|
||||
case NVM_SECTION_TYPE_PRODUCTION:
|
||||
mvm->nvm_prod_blob.data = temp;
|
||||
mvm->nvm_prod_blob.size = ret;
|
||||
break;
|
||||
default:
|
||||
WARN(1, "section: %d", section);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
kfree(nvm_buffer);
|
||||
if (ret < 0)
|
||||
|
|
|
@ -217,8 +217,7 @@ int iwl_mvm_update_quotas(struct iwl_mvm *mvm, struct ieee80211_vif *newvif)
|
|||
} else {
|
||||
cmd.quotas[idx].quota =
|
||||
cpu_to_le32(quota * data.n_interfaces[i]);
|
||||
cmd.quotas[idx].max_duration =
|
||||
cpu_to_le32(IWL_MVM_MAX_QUOTA);
|
||||
cmd.quotas[idx].max_duration = cpu_to_le32(0);
|
||||
}
|
||||
idx++;
|
||||
}
|
||||
|
|
File diff suppressed because it is too large
Load diff
|
@ -155,38 +155,7 @@ enum {
|
|||
#define IWL_RATE_SCALE_SWITCH 10880 /* 85% */
|
||||
#define IWL_RATE_HIGH_TH 10880 /* 85% */
|
||||
#define IWL_RATE_INCREASE_TH 6400 /* 50% */
|
||||
#define IWL_RATE_DECREASE_TH 1920 /* 15% */
|
||||
|
||||
/* possible actions when in legacy mode */
|
||||
enum {
|
||||
IWL_LEGACY_SWITCH_ANTENNA,
|
||||
IWL_LEGACY_SWITCH_SISO,
|
||||
IWL_LEGACY_SWITCH_MIMO2,
|
||||
IWL_LEGACY_FIRST_ACTION = IWL_LEGACY_SWITCH_ANTENNA,
|
||||
IWL_LEGACY_LAST_ACTION = IWL_LEGACY_SWITCH_MIMO2,
|
||||
};
|
||||
|
||||
/* possible actions when in siso mode */
|
||||
enum {
|
||||
IWL_SISO_SWITCH_ANTENNA,
|
||||
IWL_SISO_SWITCH_MIMO2,
|
||||
IWL_SISO_SWITCH_GI,
|
||||
IWL_SISO_FIRST_ACTION = IWL_SISO_SWITCH_ANTENNA,
|
||||
IWL_SISO_LAST_ACTION = IWL_SISO_SWITCH_GI,
|
||||
};
|
||||
|
||||
/* possible actions when in mimo mode */
|
||||
enum {
|
||||
IWL_MIMO2_SWITCH_SISO_A,
|
||||
IWL_MIMO2_SWITCH_SISO_B,
|
||||
IWL_MIMO2_SWITCH_GI,
|
||||
IWL_MIMO2_FIRST_ACTION = IWL_MIMO2_SWITCH_SISO_A,
|
||||
IWL_MIMO2_LAST_ACTION = IWL_MIMO2_SWITCH_GI,
|
||||
};
|
||||
|
||||
#define IWL_MAX_SEARCH IWL_MIMO2_LAST_ACTION
|
||||
|
||||
#define IWL_ACTION_LIMIT 3 /* # possible actions */
|
||||
#define RS_SR_FORCE_DECREASE 1920 /* 15% */
|
||||
|
||||
#define LINK_QUAL_AGG_TIME_LIMIT_DEF (4000) /* 4 milliseconds */
|
||||
#define LINK_QUAL_AGG_TIME_LIMIT_MAX (8000)
|
||||
|
@ -224,22 +193,45 @@ enum iwl_table_type {
|
|||
LQ_MAX,
|
||||
};
|
||||
|
||||
#define is_legacy(tbl) (((tbl) == LQ_LEGACY_G) || ((tbl) == LQ_LEGACY_A))
|
||||
#define is_ht_siso(tbl) ((tbl) == LQ_HT_SISO)
|
||||
#define is_ht_mimo2(tbl) ((tbl) == LQ_HT_MIMO2)
|
||||
#define is_vht_siso(tbl) ((tbl) == LQ_VHT_SISO)
|
||||
#define is_vht_mimo2(tbl) ((tbl) == LQ_VHT_MIMO2)
|
||||
#define is_siso(tbl) (is_ht_siso(tbl) || is_vht_siso(tbl))
|
||||
#define is_mimo2(tbl) (is_ht_mimo2(tbl) || is_vht_mimo2(tbl))
|
||||
#define is_mimo(tbl) (is_mimo2(tbl))
|
||||
#define is_ht(tbl) (is_ht_siso(tbl) || is_ht_mimo2(tbl))
|
||||
#define is_vht(tbl) (is_vht_siso(tbl) || is_vht_mimo2(tbl))
|
||||
#define is_a_band(tbl) ((tbl) == LQ_LEGACY_A)
|
||||
#define is_g_band(tbl) ((tbl) == LQ_LEGACY_G)
|
||||
struct rs_rate {
|
||||
int index;
|
||||
enum iwl_table_type type;
|
||||
u8 ant;
|
||||
u32 bw;
|
||||
bool sgi;
|
||||
};
|
||||
|
||||
#define is_ht20(tbl) (tbl->bw == RATE_MCS_CHAN_WIDTH_20)
|
||||
#define is_ht40(tbl) (tbl->bw == RATE_MCS_CHAN_WIDTH_40)
|
||||
#define is_ht80(tbl) (tbl->bw == RATE_MCS_CHAN_WIDTH_80)
|
||||
|
||||
#define is_type_legacy(type) (((type) == LQ_LEGACY_G) || \
|
||||
((type) == LQ_LEGACY_A))
|
||||
#define is_type_ht_siso(type) ((type) == LQ_HT_SISO)
|
||||
#define is_type_ht_mimo2(type) ((type) == LQ_HT_MIMO2)
|
||||
#define is_type_vht_siso(type) ((type) == LQ_VHT_SISO)
|
||||
#define is_type_vht_mimo2(type) ((type) == LQ_VHT_MIMO2)
|
||||
#define is_type_siso(type) (is_type_ht_siso(type) || is_type_vht_siso(type))
|
||||
#define is_type_mimo2(type) (is_type_ht_mimo2(type) || is_type_vht_mimo2(type))
|
||||
#define is_type_mimo(type) (is_type_mimo2(type))
|
||||
#define is_type_ht(type) (is_type_ht_siso(type) || is_type_ht_mimo2(type))
|
||||
#define is_type_vht(type) (is_type_vht_siso(type) || is_type_vht_mimo2(type))
|
||||
#define is_type_a_band(type) ((type) == LQ_LEGACY_A)
|
||||
#define is_type_g_band(type) ((type) == LQ_LEGACY_G)
|
||||
|
||||
#define is_legacy(rate) is_type_legacy((rate)->type)
|
||||
#define is_ht_siso(rate) is_type_ht_siso((rate)->type)
|
||||
#define is_ht_mimo2(rate) is_type_ht_mimo2((rate)->type)
|
||||
#define is_vht_siso(rate) is_type_vht_siso((rate)->type)
|
||||
#define is_vht_mimo2(rate) is_type_vht_mimo2((rate)->type)
|
||||
#define is_siso(rate) is_type_siso((rate)->type)
|
||||
#define is_mimo2(rate) is_type_mimo2((rate)->type)
|
||||
#define is_mimo(rate) is_type_mimo((rate)->type)
|
||||
#define is_ht(rate) is_type_ht((rate)->type)
|
||||
#define is_vht(rate) is_type_vht((rate)->type)
|
||||
#define is_a_band(rate) is_type_a_band((rate)->type)
|
||||
#define is_g_band(rate) is_type_g_band((rate)->type)
|
||||
|
||||
#define is_ht20(rate) ((rate)->bw == RATE_MCS_CHAN_WIDTH_20)
|
||||
#define is_ht40(rate) ((rate)->bw == RATE_MCS_CHAN_WIDTH_40)
|
||||
#define is_ht80(rate) ((rate)->bw == RATE_MCS_CHAN_WIDTH_80)
|
||||
|
||||
#define IWL_MAX_MCS_DISPLAY_SIZE 12
|
||||
|
||||
|
@ -257,7 +249,23 @@ struct iwl_rate_scale_data {
|
|||
s32 success_ratio; /* per-cent * 128 */
|
||||
s32 counter; /* number of frames attempted */
|
||||
s32 average_tpt; /* success ratio * expected throughput */
|
||||
unsigned long stamp;
|
||||
};
|
||||
|
||||
/* Possible Tx columns
|
||||
* Tx Column = a combo of legacy/siso/mimo x antenna x SGI
|
||||
*/
|
||||
enum rs_column {
|
||||
RS_COLUMN_LEGACY_ANT_A = 0,
|
||||
RS_COLUMN_LEGACY_ANT_B,
|
||||
RS_COLUMN_SISO_ANT_A,
|
||||
RS_COLUMN_SISO_ANT_B,
|
||||
RS_COLUMN_SISO_ANT_A_SGI,
|
||||
RS_COLUMN_SISO_ANT_B_SGI,
|
||||
RS_COLUMN_MIMO2,
|
||||
RS_COLUMN_MIMO2_SGI,
|
||||
|
||||
RS_COLUMN_LAST = RS_COLUMN_MIMO2_SGI,
|
||||
RS_COLUMN_INVALID,
|
||||
};
|
||||
|
||||
/**
|
||||
|
@ -267,17 +275,19 @@ struct iwl_rate_scale_data {
|
|||
* one for "active", and one for "search".
|
||||
*/
|
||||
struct iwl_scale_tbl_info {
|
||||
enum iwl_table_type lq_type;
|
||||
u8 ant_type;
|
||||
u8 is_SGI; /* 1 = short guard interval */
|
||||
u32 bw; /* channel bandwidth; RATE_MCS_CHAN_WIDTH_XX */
|
||||
u8 action; /* change modulation; IWL_[LEGACY/SISO/MIMO]_SWITCH_* */
|
||||
u8 max_search; /* maximun number of tables we can search */
|
||||
struct rs_rate rate;
|
||||
enum rs_column column;
|
||||
s32 *expected_tpt; /* throughput metrics; expected_tpt_G, etc. */
|
||||
u32 current_rate; /* rate_n_flags, uCode API format */
|
||||
struct iwl_rate_scale_data win[IWL_RATE_COUNT]; /* rate histories */
|
||||
};
|
||||
|
||||
enum {
|
||||
RS_STATE_SEARCH_CYCLE_STARTED,
|
||||
RS_STATE_SEARCH_CYCLE_ENDED,
|
||||
RS_STATE_STAY_IN_COLUMN,
|
||||
};
|
||||
|
||||
/**
|
||||
* struct iwl_lq_sta -- driver's rate scaling private structure
|
||||
*
|
||||
|
@ -285,8 +295,7 @@ struct iwl_scale_tbl_info {
|
|||
*/
|
||||
struct iwl_lq_sta {
|
||||
u8 active_tbl; /* index of active table, range 0-1 */
|
||||
u8 enable_counter; /* indicates HT mode */
|
||||
u8 stay_in_tbl; /* 1: disallow, 0: allow search for new mode */
|
||||
u8 rs_state; /* RS_STATE_* */
|
||||
u8 search_better_tbl; /* 1: currently trying alternate mode */
|
||||
s32 last_tpt;
|
||||
|
||||
|
@ -299,7 +308,9 @@ struct iwl_lq_sta {
|
|||
u32 total_success; /* total successful frames, any/all rates */
|
||||
u64 flush_timer; /* time staying in mode before new search */
|
||||
|
||||
u8 action_counter; /* # mode-switch actions tried */
|
||||
u32 visited_columns; /* Bitmask marking which Tx columns were
|
||||
* explored during a search cycle
|
||||
*/
|
||||
bool is_vht;
|
||||
enum ieee80211_band band;
|
||||
|
||||
|
@ -328,32 +339,11 @@ struct iwl_lq_sta {
|
|||
u32 last_rate_n_flags;
|
||||
/* packets destined for this STA are aggregated */
|
||||
u8 is_agg;
|
||||
/* BT traffic this sta was last updated in */
|
||||
u8 last_bt_traffic;
|
||||
};
|
||||
|
||||
enum iwl_bt_coex_profile_traffic_load {
|
||||
IWL_BT_COEX_TRAFFIC_LOAD_NONE = 0,
|
||||
IWL_BT_COEX_TRAFFIC_LOAD_LOW = 1,
|
||||
IWL_BT_COEX_TRAFFIC_LOAD_HIGH = 2,
|
||||
IWL_BT_COEX_TRAFFIC_LOAD_CONTINUOUS = 3,
|
||||
/*
|
||||
* There are no more even though below is a u8, the
|
||||
* indication from the BT device only has two bits.
|
||||
*/
|
||||
};
|
||||
|
||||
|
||||
static inline u8 num_of_ant(u8 mask)
|
||||
{
|
||||
return !!((mask) & ANT_A) +
|
||||
!!((mask) & ANT_B) +
|
||||
!!((mask) & ANT_C);
|
||||
}
|
||||
|
||||
/* Initialize station's rate scaling information after adding station */
|
||||
void iwl_mvm_rs_rate_init(struct iwl_mvm *mvm, struct ieee80211_sta *sta,
|
||||
enum ieee80211_band band);
|
||||
enum ieee80211_band band, bool init);
|
||||
|
||||
/**
|
||||
* iwl_rate_control_register - Register the rate control algorithm callbacks
|
||||
|
|
|
@ -70,6 +70,9 @@
|
|||
|
||||
#define IWL_PLCP_QUIET_THRESH 1
|
||||
#define IWL_ACTIVE_QUIET_TIME 10
|
||||
#define LONG_OUT_TIME_PERIOD 600
|
||||
#define SHORT_OUT_TIME_PERIOD 200
|
||||
#define SUSPEND_TIME_PERIOD 100
|
||||
|
||||
static inline __le16 iwl_mvm_scan_rx_chain(struct iwl_mvm *mvm)
|
||||
{
|
||||
|
@ -87,20 +90,22 @@ static inline __le16 iwl_mvm_scan_rx_chain(struct iwl_mvm *mvm)
|
|||
return cpu_to_le16(rx_chain);
|
||||
}
|
||||
|
||||
static inline __le32 iwl_mvm_scan_max_out_time(struct ieee80211_vif *vif)
|
||||
static inline __le32 iwl_mvm_scan_max_out_time(struct ieee80211_vif *vif,
|
||||
u32 flags, bool is_assoc)
|
||||
{
|
||||
if (vif->bss_conf.assoc)
|
||||
return cpu_to_le32(200 * 1024);
|
||||
else
|
||||
if (!is_assoc)
|
||||
return 0;
|
||||
if (flags & NL80211_SCAN_FLAG_LOW_PRIORITY)
|
||||
return cpu_to_le32(ieee80211_tu_to_usec(SHORT_OUT_TIME_PERIOD));
|
||||
return cpu_to_le32(ieee80211_tu_to_usec(LONG_OUT_TIME_PERIOD));
|
||||
}
|
||||
|
||||
static inline __le32 iwl_mvm_scan_suspend_time(struct ieee80211_vif *vif)
|
||||
static inline __le32 iwl_mvm_scan_suspend_time(struct ieee80211_vif *vif,
|
||||
bool is_assoc)
|
||||
{
|
||||
if (!vif->bss_conf.assoc)
|
||||
if (!is_assoc)
|
||||
return 0;
|
||||
|
||||
return cpu_to_le32(ieee80211_tu_to_usec(vif->bss_conf.beacon_int));
|
||||
return cpu_to_le32(ieee80211_tu_to_usec(SUSPEND_TIME_PERIOD));
|
||||
}
|
||||
|
||||
static inline __le32
|
||||
|
@ -262,6 +267,15 @@ static u16 iwl_mvm_fill_probe_req(struct ieee80211_mgmt *frame, const u8 *ta,
|
|||
return (u16)len;
|
||||
}
|
||||
|
||||
static void iwl_mvm_vif_assoc_iterator(void *data, u8 *mac,
|
||||
struct ieee80211_vif *vif)
|
||||
{
|
||||
bool *is_assoc = data;
|
||||
|
||||
if (vif->bss_conf.assoc)
|
||||
*is_assoc = true;
|
||||
}
|
||||
|
||||
int iwl_mvm_scan_request(struct iwl_mvm *mvm,
|
||||
struct ieee80211_vif *vif,
|
||||
struct cfg80211_scan_request *req)
|
||||
|
@ -274,6 +288,7 @@ int iwl_mvm_scan_request(struct iwl_mvm *mvm,
|
|||
.dataflags = { IWL_HCMD_DFL_NOCOPY, },
|
||||
};
|
||||
struct iwl_scan_cmd *cmd = mvm->scan_cmd;
|
||||
bool is_assoc = false;
|
||||
int ret;
|
||||
u32 status;
|
||||
int ssid_len = 0;
|
||||
|
@ -289,13 +304,17 @@ int iwl_mvm_scan_request(struct iwl_mvm *mvm,
|
|||
memset(cmd, 0, sizeof(struct iwl_scan_cmd) +
|
||||
mvm->fw->ucode_capa.max_probe_length +
|
||||
(MAX_NUM_SCAN_CHANNELS * sizeof(struct iwl_scan_channel)));
|
||||
|
||||
ieee80211_iterate_active_interfaces_atomic(mvm->hw,
|
||||
IEEE80211_IFACE_ITER_NORMAL,
|
||||
iwl_mvm_vif_assoc_iterator,
|
||||
&is_assoc);
|
||||
cmd->channel_count = (u8)req->n_channels;
|
||||
cmd->quiet_time = cpu_to_le16(IWL_ACTIVE_QUIET_TIME);
|
||||
cmd->quiet_plcp_th = cpu_to_le16(IWL_PLCP_QUIET_THRESH);
|
||||
cmd->rxchain_sel_flags = iwl_mvm_scan_rx_chain(mvm);
|
||||
cmd->max_out_time = iwl_mvm_scan_max_out_time(vif);
|
||||
cmd->suspend_time = iwl_mvm_scan_suspend_time(vif);
|
||||
cmd->max_out_time = iwl_mvm_scan_max_out_time(vif, req->flags,
|
||||
is_assoc);
|
||||
cmd->suspend_time = iwl_mvm_scan_suspend_time(vif, is_assoc);
|
||||
cmd->rxon_flags = iwl_mvm_scan_rxon_flags(req);
|
||||
cmd->filter_flags = cpu_to_le32(MAC_FILTER_ACCEPT_GRP |
|
||||
MAC_FILTER_IN_BEACON);
|
||||
|
@ -522,6 +541,12 @@ static void iwl_build_scan_cmd(struct iwl_mvm *mvm,
|
|||
struct cfg80211_sched_scan_request *req,
|
||||
struct iwl_scan_offload_cmd *scan)
|
||||
{
|
||||
bool is_assoc = false;
|
||||
|
||||
ieee80211_iterate_active_interfaces_atomic(mvm->hw,
|
||||
IEEE80211_IFACE_ITER_NORMAL,
|
||||
iwl_mvm_vif_assoc_iterator,
|
||||
&is_assoc);
|
||||
scan->channel_count =
|
||||
mvm->nvm_data->bands[IEEE80211_BAND_2GHZ].n_channels +
|
||||
mvm->nvm_data->bands[IEEE80211_BAND_5GHZ].n_channels;
|
||||
|
@ -529,8 +554,9 @@ static void iwl_build_scan_cmd(struct iwl_mvm *mvm,
|
|||
scan->quiet_plcp_th = cpu_to_le16(IWL_PLCP_QUIET_THRESH);
|
||||
scan->good_CRC_th = IWL_GOOD_CRC_TH_DEFAULT;
|
||||
scan->rx_chain = iwl_mvm_scan_rx_chain(mvm);
|
||||
scan->max_out_time = cpu_to_le32(200 * 1024);
|
||||
scan->suspend_time = iwl_mvm_scan_suspend_time(vif);
|
||||
scan->max_out_time = iwl_mvm_scan_max_out_time(vif, req->flags,
|
||||
is_assoc);
|
||||
scan->suspend_time = iwl_mvm_scan_suspend_time(vif, is_assoc);
|
||||
scan->filter_flags |= cpu_to_le32(MAC_FILTER_ACCEPT_GRP |
|
||||
MAC_FILTER_IN_BEACON);
|
||||
scan->scan_type = cpu_to_le32(SCAN_TYPE_BACKGROUND);
|
||||
|
@ -817,11 +843,10 @@ int iwl_mvm_sched_scan_start(struct iwl_mvm *mvm,
|
|||
IWL_DEBUG_SCAN(mvm,
|
||||
"Sending scheduled scan with filtering, filter len %d\n",
|
||||
req->n_match_sets);
|
||||
scan_req.flags |=
|
||||
cpu_to_le16(IWL_SCAN_OFFLOAD_FLAG_FILTER_SSID);
|
||||
} else {
|
||||
IWL_DEBUG_SCAN(mvm,
|
||||
"Sending Scheduled scan without filtering\n");
|
||||
scan_req.flags |= cpu_to_le16(IWL_SCAN_OFFLOAD_FLAG_PASS_ALL);
|
||||
}
|
||||
|
||||
return iwl_mvm_send_cmd_pdu(mvm, SCAN_OFFLOAD_REQUEST_CMD, CMD_SYNC,
|
||||
|
|
|
@ -840,7 +840,7 @@ static const u8 tid_to_ac[] = {
|
|||
int iwl_mvm_sta_tx_agg_start(struct iwl_mvm *mvm, struct ieee80211_vif *vif,
|
||||
struct ieee80211_sta *sta, u16 tid, u16 *ssn)
|
||||
{
|
||||
struct iwl_mvm_sta *mvmsta = (void *)sta->drv_priv;
|
||||
struct iwl_mvm_sta *mvmsta = iwl_mvm_sta_from_mac80211(sta);
|
||||
struct iwl_mvm_tid_data *tid_data;
|
||||
int txq_id;
|
||||
|
||||
|
@ -895,7 +895,7 @@ int iwl_mvm_sta_tx_agg_start(struct iwl_mvm *mvm, struct ieee80211_vif *vif,
|
|||
int iwl_mvm_sta_tx_agg_oper(struct iwl_mvm *mvm, struct ieee80211_vif *vif,
|
||||
struct ieee80211_sta *sta, u16 tid, u8 buf_size)
|
||||
{
|
||||
struct iwl_mvm_sta *mvmsta = (void *)sta->drv_priv;
|
||||
struct iwl_mvm_sta *mvmsta = iwl_mvm_sta_from_mac80211(sta);
|
||||
struct iwl_mvm_tid_data *tid_data = &mvmsta->tid_data[tid];
|
||||
int queue, fifo, ret;
|
||||
u16 ssn;
|
||||
|
@ -945,13 +945,13 @@ int iwl_mvm_sta_tx_agg_oper(struct iwl_mvm *mvm, struct ieee80211_vif *vif,
|
|||
*/
|
||||
}
|
||||
|
||||
return iwl_mvm_send_lq_cmd(mvm, &mvmsta->lq_sta.lq, CMD_ASYNC, false);
|
||||
return iwl_mvm_send_lq_cmd(mvm, &mvmsta->lq_sta.lq, false);
|
||||
}
|
||||
|
||||
int iwl_mvm_sta_tx_agg_stop(struct iwl_mvm *mvm, struct ieee80211_vif *vif,
|
||||
struct ieee80211_sta *sta, u16 tid)
|
||||
{
|
||||
struct iwl_mvm_sta *mvmsta = (void *)sta->drv_priv;
|
||||
struct iwl_mvm_sta *mvmsta = iwl_mvm_sta_from_mac80211(sta);
|
||||
struct iwl_mvm_tid_data *tid_data = &mvmsta->tid_data[tid];
|
||||
u16 txq_id;
|
||||
int err;
|
||||
|
@ -1023,7 +1023,7 @@ int iwl_mvm_sta_tx_agg_stop(struct iwl_mvm *mvm, struct ieee80211_vif *vif,
|
|||
int iwl_mvm_sta_tx_agg_flush(struct iwl_mvm *mvm, struct ieee80211_vif *vif,
|
||||
struct ieee80211_sta *sta, u16 tid)
|
||||
{
|
||||
struct iwl_mvm_sta *mvmsta = (void *)sta->drv_priv;
|
||||
struct iwl_mvm_sta *mvmsta = iwl_mvm_sta_from_mac80211(sta);
|
||||
struct iwl_mvm_tid_data *tid_data = &mvmsta->tid_data[tid];
|
||||
u16 txq_id;
|
||||
enum iwl_mvm_agg_state old_state;
|
||||
|
@ -1416,7 +1416,7 @@ void iwl_mvm_update_tkip_key(struct iwl_mvm *mvm,
|
|||
void iwl_mvm_sta_modify_ps_wake(struct iwl_mvm *mvm,
|
||||
struct ieee80211_sta *sta)
|
||||
{
|
||||
struct iwl_mvm_sta *mvmsta = (void *)sta->drv_priv;
|
||||
struct iwl_mvm_sta *mvmsta = iwl_mvm_sta_from_mac80211(sta);
|
||||
struct iwl_mvm_add_sta_cmd_v6 cmd = {
|
||||
.add_modify = STA_MODE_MODIFY,
|
||||
.sta_id = mvmsta->sta_id,
|
||||
|
@ -1438,7 +1438,7 @@ void iwl_mvm_sta_modify_sleep_tx_count(struct iwl_mvm *mvm,
|
|||
u16 sleep_state_flags =
|
||||
(reason == IEEE80211_FRAME_RELEASE_UAPSD) ?
|
||||
STA_SLEEP_STATE_UAPSD : STA_SLEEP_STATE_PS_POLL;
|
||||
struct iwl_mvm_sta *mvmsta = (void *)sta->drv_priv;
|
||||
struct iwl_mvm_sta *mvmsta = iwl_mvm_sta_from_mac80211(sta);
|
||||
struct iwl_mvm_add_sta_cmd_v6 cmd = {
|
||||
.add_modify = STA_MODE_MODIFY,
|
||||
.sta_id = mvmsta->sta_id,
|
||||
|
|
|
@ -298,6 +298,12 @@ struct iwl_mvm_sta {
|
|||
bool tt_tx_protection;
|
||||
};
|
||||
|
||||
static inline struct iwl_mvm_sta *
|
||||
iwl_mvm_sta_from_mac80211(struct ieee80211_sta *sta)
|
||||
{
|
||||
return (void *)sta->drv_priv;
|
||||
}
|
||||
|
||||
/**
|
||||
* struct iwl_mvm_int_sta - representation of an internal station (auxiliary or
|
||||
* broadcast)
|
||||
|
|
|
@ -388,7 +388,7 @@ static void iwl_mvm_tt_tx_protection(struct iwl_mvm *mvm, bool enable)
|
|||
lockdep_is_held(&mvm->mutex));
|
||||
if (IS_ERR_OR_NULL(sta))
|
||||
continue;
|
||||
mvmsta = (void *)sta->drv_priv;
|
||||
mvmsta = iwl_mvm_sta_from_mac80211(sta);
|
||||
if (enable == mvmsta->tt_tx_protection)
|
||||
continue;
|
||||
err = iwl_mvm_tx_protection(mvm, mvmsta, enable);
|
||||
|
|
|
@ -276,6 +276,7 @@ iwl_mvm_set_tx_params(struct iwl_mvm *mvm, struct sk_buff *skb,
|
|||
return NULL;
|
||||
|
||||
memset(dev_cmd, 0, sizeof(*dev_cmd));
|
||||
dev_cmd->hdr.cmd = TX_CMD;
|
||||
tx_cmd = (struct iwl_tx_cmd *)dev_cmd->payload;
|
||||
|
||||
if (info->control.hw_key)
|
||||
|
@ -361,7 +362,7 @@ int iwl_mvm_tx_skb(struct iwl_mvm *mvm, struct sk_buff *skb,
|
|||
u8 txq_id = info->hw_queue;
|
||||
bool is_data_qos = false, is_ampdu = false;
|
||||
|
||||
mvmsta = (void *)sta->drv_priv;
|
||||
mvmsta = iwl_mvm_sta_from_mac80211(sta);
|
||||
fc = hdr->frame_control;
|
||||
|
||||
if (WARN_ON_ONCE(!mvmsta))
|
||||
|
@ -432,7 +433,7 @@ int iwl_mvm_tx_skb(struct iwl_mvm *mvm, struct sk_buff *skb,
|
|||
static void iwl_mvm_check_ratid_empty(struct iwl_mvm *mvm,
|
||||
struct ieee80211_sta *sta, u8 tid)
|
||||
{
|
||||
struct iwl_mvm_sta *mvmsta = (void *)sta->drv_priv;
|
||||
struct iwl_mvm_sta *mvmsta = iwl_mvm_sta_from_mac80211(sta);
|
||||
struct iwl_mvm_tid_data *tid_data = &mvmsta->tid_data[tid];
|
||||
struct ieee80211_vif *vif = mvmsta->vif;
|
||||
|
||||
|
@ -662,7 +663,7 @@ static void iwl_mvm_rx_tx_cmd_single(struct iwl_mvm *mvm,
|
|||
sta = rcu_dereference(mvm->fw_id_to_mac_id[sta_id]);
|
||||
|
||||
if (!IS_ERR_OR_NULL(sta)) {
|
||||
mvmsta = (void *)sta->drv_priv;
|
||||
mvmsta = iwl_mvm_sta_from_mac80211(sta);
|
||||
|
||||
if (tid != IWL_TID_NON_QOS) {
|
||||
struct iwl_mvm_tid_data *tid_data =
|
||||
|
@ -793,7 +794,7 @@ static void iwl_mvm_rx_tx_cmd_agg(struct iwl_mvm *mvm,
|
|||
sta = rcu_dereference(mvm->fw_id_to_mac_id[sta_id]);
|
||||
|
||||
if (!WARN_ON_ONCE(IS_ERR_OR_NULL(sta))) {
|
||||
struct iwl_mvm_sta *mvmsta = (void *)sta->drv_priv;
|
||||
struct iwl_mvm_sta *mvmsta = iwl_mvm_sta_from_mac80211(sta);
|
||||
mvmsta->tid_data[tid].rate_n_flags =
|
||||
le32_to_cpu(tx_resp->initial_rate);
|
||||
}
|
||||
|
@ -849,7 +850,7 @@ int iwl_mvm_rx_ba_notif(struct iwl_mvm *mvm, struct iwl_rx_cmd_buffer *rxb,
|
|||
return 0;
|
||||
}
|
||||
|
||||
mvmsta = (void *)sta->drv_priv;
|
||||
mvmsta = iwl_mvm_sta_from_mac80211(sta);
|
||||
tid_data = &mvmsta->tid_data[tid];
|
||||
|
||||
if (WARN_ONCE(tid_data->txq_id != scd_flow, "Q %d, tid %d, flow %d",
|
||||
|
|
|
@ -486,22 +486,18 @@ void iwl_mvm_dump_sram(struct iwl_mvm *mvm)
|
|||
* this case to clear the state indicating that station creation is in
|
||||
* progress.
|
||||
*/
|
||||
int iwl_mvm_send_lq_cmd(struct iwl_mvm *mvm, struct iwl_lq_cmd *lq,
|
||||
u8 flags, bool init)
|
||||
int iwl_mvm_send_lq_cmd(struct iwl_mvm *mvm, struct iwl_lq_cmd *lq, bool init)
|
||||
{
|
||||
struct iwl_host_cmd cmd = {
|
||||
.id = LQ_CMD,
|
||||
.len = { sizeof(struct iwl_lq_cmd), },
|
||||
.flags = flags,
|
||||
.flags = init ? CMD_SYNC : CMD_ASYNC,
|
||||
.data = { lq, },
|
||||
};
|
||||
|
||||
if (WARN_ON(lq->sta_id == IWL_MVM_STATION_COUNT))
|
||||
return -EINVAL;
|
||||
|
||||
if (WARN_ON(init && (cmd.flags & CMD_ASYNC)))
|
||||
return -EINVAL;
|
||||
|
||||
return iwl_mvm_send_cmd(mvm, &cmd);
|
||||
}
|
||||
|
||||
|
|
|
@ -297,6 +297,9 @@ static DEFINE_PCI_DEVICE_TABLE(iwl_hw_card_ids) = {
|
|||
{IWL_PCI_DEVICE(0x08B2, 0x4370, iwl7260_2ac_cfg)},
|
||||
{IWL_PCI_DEVICE(0x08B2, 0x4360, iwl7260_2n_cfg)},
|
||||
{IWL_PCI_DEVICE(0x08B1, 0x5070, iwl7260_2ac_cfg)},
|
||||
{IWL_PCI_DEVICE(0x08B1, 0x5072, iwl7260_2ac_cfg)},
|
||||
{IWL_PCI_DEVICE(0x08B1, 0x5170, iwl7260_2ac_cfg)},
|
||||
{IWL_PCI_DEVICE(0x08B1, 0x5770, iwl7260_2ac_cfg)},
|
||||
{IWL_PCI_DEVICE(0x08B1, 0x4020, iwl7260_2n_cfg)},
|
||||
{IWL_PCI_DEVICE(0x08B1, 0x402A, iwl7260_2n_cfg)},
|
||||
{IWL_PCI_DEVICE(0x08B2, 0x4220, iwl7260_2n_cfg)},
|
||||
|
@ -350,6 +353,8 @@ static DEFINE_PCI_DEVICE_TABLE(iwl_hw_card_ids) = {
|
|||
{IWL_PCI_DEVICE(0x08B4, 0x8270, iwl3160_2ac_cfg)},
|
||||
{IWL_PCI_DEVICE(0x08B3, 0x8470, iwl3160_2ac_cfg)},
|
||||
{IWL_PCI_DEVICE(0x08B3, 0x8570, iwl3160_2ac_cfg)},
|
||||
{IWL_PCI_DEVICE(0x08B3, 0x1070, iwl3160_2ac_cfg)},
|
||||
{IWL_PCI_DEVICE(0x08B3, 0x1170, iwl3160_2ac_cfg)},
|
||||
|
||||
/* 7265 Series */
|
||||
{IWL_PCI_DEVICE(0x095A, 0x5010, iwl7265_2ac_cfg)},
|
||||
|
|
|
@ -1126,7 +1126,6 @@ static irqreturn_t iwl_pcie_isr(int irq, void *data)
|
|||
struct iwl_trans *trans = data;
|
||||
struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
|
||||
u32 inta, inta_mask;
|
||||
irqreturn_t ret = IRQ_NONE;
|
||||
|
||||
lockdep_assert_held(&trans_pcie->irq_lock);
|
||||
|
||||
|
@ -1155,7 +1154,16 @@ static irqreturn_t iwl_pcie_isr(int irq, void *data)
|
|||
* or due to sporadic interrupts thrown from our NIC. */
|
||||
if (!inta) {
|
||||
IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n");
|
||||
goto none;
|
||||
/*
|
||||
* Re-enable interrupts here since we don't have anything to
|
||||
* service, but only in case the handler won't run. Note that
|
||||
* the handler can be scheduled because of a previous
|
||||
* interrupt.
|
||||
*/
|
||||
if (test_bit(STATUS_INT_ENABLED, &trans_pcie->status) &&
|
||||
!trans_pcie->inta)
|
||||
iwl_enable_interrupts(trans);
|
||||
return IRQ_NONE;
|
||||
}
|
||||
|
||||
if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
|
||||
|
@ -1173,19 +1181,7 @@ static irqreturn_t iwl_pcie_isr(int irq, void *data)
|
|||
|
||||
trans_pcie->inta |= inta;
|
||||
/* the thread will service interrupts and re-enable them */
|
||||
if (likely(inta))
|
||||
return IRQ_WAKE_THREAD;
|
||||
|
||||
ret = IRQ_HANDLED;
|
||||
|
||||
none:
|
||||
/* re-enable interrupts here since we don't have anything to service. */
|
||||
/* only Re-enable if disabled by irq and no schedules tasklet. */
|
||||
if (test_bit(STATUS_INT_ENABLED, &trans_pcie->status) &&
|
||||
!trans_pcie->inta)
|
||||
iwl_enable_interrupts(trans);
|
||||
|
||||
return ret;
|
||||
return IRQ_WAKE_THREAD;
|
||||
}
|
||||
|
||||
/* interrupt handler using ict table, with this interrupt driver will
|
||||
|
|
|
@ -1542,30 +1542,24 @@ static int iwl_pcie_send_hcmd_sync(struct iwl_trans *trans,
|
|||
}
|
||||
|
||||
if (!ret) {
|
||||
if (test_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status)) {
|
||||
struct iwl_txq *txq =
|
||||
&trans_pcie->txq[trans_pcie->cmd_queue];
|
||||
struct iwl_queue *q = &txq->q;
|
||||
struct iwl_txq *txq = &trans_pcie->txq[trans_pcie->cmd_queue];
|
||||
struct iwl_queue *q = &txq->q;
|
||||
|
||||
IWL_ERR(trans,
|
||||
"Error sending %s: time out after %dms.\n",
|
||||
get_cmd_string(trans_pcie, cmd->id),
|
||||
jiffies_to_msecs(HOST_COMPLETE_TIMEOUT));
|
||||
IWL_ERR(trans, "Error sending %s: time out after %dms.\n",
|
||||
get_cmd_string(trans_pcie, cmd->id),
|
||||
jiffies_to_msecs(HOST_COMPLETE_TIMEOUT));
|
||||
|
||||
IWL_ERR(trans,
|
||||
"Current CMD queue read_ptr %d write_ptr %d\n",
|
||||
q->read_ptr, q->write_ptr);
|
||||
IWL_ERR(trans, "Current CMD queue read_ptr %d write_ptr %d\n",
|
||||
q->read_ptr, q->write_ptr);
|
||||
|
||||
clear_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status);
|
||||
IWL_DEBUG_INFO(trans,
|
||||
"Clearing HCMD_ACTIVE for command %s\n",
|
||||
get_cmd_string(trans_pcie, cmd->id));
|
||||
ret = -ETIMEDOUT;
|
||||
clear_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status);
|
||||
IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n",
|
||||
get_cmd_string(trans_pcie, cmd->id));
|
||||
ret = -ETIMEDOUT;
|
||||
|
||||
iwl_nic_error(trans);
|
||||
iwl_nic_error(trans);
|
||||
|
||||
goto cancel;
|
||||
}
|
||||
goto cancel;
|
||||
}
|
||||
|
||||
if (test_bit(STATUS_FW_ERROR, &trans_pcie->status)) {
|
||||
|
@ -1674,7 +1668,6 @@ int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb,
|
|||
txq->entries[q->write_ptr].skb = skb;
|
||||
txq->entries[q->write_ptr].cmd = dev_cmd;
|
||||
|
||||
dev_cmd->hdr.cmd = REPLY_TX;
|
||||
dev_cmd->hdr.sequence =
|
||||
cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
|
||||
INDEX_TO_SEQ(q->write_ptr)));
|
||||
|
|
|
@ -8,9 +8,8 @@
|
|||
Ltd. under the terms of the GNU General Public License Version 2, June 1991
|
||||
(the "License"). You may use, redistribute and/or modify this File in
|
||||
accordance with the terms and conditions of the License, a copy of which
|
||||
is available along with the File in the license.txt file or by writing to
|
||||
the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
|
||||
02111-1307 or on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
|
||||
is available along with the File in the license.txt file or on the worldwide
|
||||
web at http://www.gnu.org/licenses/gpl.txt.
|
||||
|
||||
THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE
|
||||
|
|
|
@ -69,9 +69,9 @@ mwifiex_11n_form_amsdu_pkt(struct sk_buff *skb_aggr,
|
|||
memcpy(&tx_header->eth803_hdr, skb_src->data, dt_offset);
|
||||
|
||||
/* Copy SNAP header */
|
||||
snap.snap_type =
|
||||
le16_to_cpu(*(__le16 *) ((u8 *)skb_src->data + dt_offset));
|
||||
dt_offset += sizeof(u16);
|
||||
snap.snap_type = ((struct ethhdr *)skb_src->data)->h_proto;
|
||||
|
||||
dt_offset += sizeof(__be16);
|
||||
|
||||
memcpy(&tx_header->rfc1042_hdr, &snap, sizeof(struct rfc_1042_hdr));
|
||||
|
||||
|
|
|
@ -222,6 +222,7 @@ mwifiex_cfg80211_mgmt_tx(struct wiphy *wiphy, struct wireless_dev *wdev,
|
|||
tx_info = MWIFIEX_SKB_TXCB(skb);
|
||||
tx_info->bss_num = priv->bss_num;
|
||||
tx_info->bss_type = priv->bss_type;
|
||||
tx_info->pkt_len = pkt_len;
|
||||
|
||||
mwifiex_form_mgmt_frame(skb, buf, len);
|
||||
mwifiex_queue_tx_pkt(priv, skb);
|
||||
|
|
|
@ -312,14 +312,14 @@ static int mwifiex_dnld_sleep_confirm_cmd(struct mwifiex_adapter *adapter)
|
|||
}
|
||||
if (GET_BSS_ROLE(mwifiex_get_priv(adapter, MWIFIEX_BSS_ROLE_ANY))
|
||||
== MWIFIEX_BSS_ROLE_STA) {
|
||||
if (!sleep_cfm_buf->resp_ctrl)
|
||||
if (!le16_to_cpu(sleep_cfm_buf->resp_ctrl))
|
||||
/* Response is not needed for sleep
|
||||
confirm command */
|
||||
adapter->ps_state = PS_STATE_SLEEP;
|
||||
else
|
||||
adapter->ps_state = PS_STATE_SLEEP_CFM;
|
||||
|
||||
if (!sleep_cfm_buf->resp_ctrl &&
|
||||
if (!le16_to_cpu(sleep_cfm_buf->resp_ctrl) &&
|
||||
(adapter->is_hs_configured &&
|
||||
!adapter->sleep_period.period)) {
|
||||
adapter->pm_wakeup_card_req = true;
|
||||
|
|
|
@ -130,6 +130,7 @@ struct mwifiex_txinfo {
|
|||
u8 flags;
|
||||
u8 bss_num;
|
||||
u8 bss_type;
|
||||
u32 pkt_len;
|
||||
};
|
||||
|
||||
enum mwifiex_wmm_ac_e {
|
||||
|
|
|
@ -30,7 +30,7 @@ struct rfc_1042_hdr {
|
|||
u8 llc_ssap;
|
||||
u8 llc_ctrl;
|
||||
u8 snap_oui[3];
|
||||
u16 snap_type;
|
||||
__be16 snap_type;
|
||||
};
|
||||
|
||||
struct rx_packet_hdr {
|
||||
|
@ -610,12 +610,12 @@ struct mwifiex_ie_types_tsf_timestamp {
|
|||
struct mwifiex_cf_param_set {
|
||||
u8 cfp_cnt;
|
||||
u8 cfp_period;
|
||||
u16 cfp_max_duration;
|
||||
u16 cfp_duration_remaining;
|
||||
__le16 cfp_max_duration;
|
||||
__le16 cfp_duration_remaining;
|
||||
} __packed;
|
||||
|
||||
struct mwifiex_ibss_param_set {
|
||||
u16 atim_window;
|
||||
__le16 atim_window;
|
||||
} __packed;
|
||||
|
||||
struct mwifiex_ie_types_ss_param_set {
|
||||
|
@ -627,7 +627,7 @@ struct mwifiex_ie_types_ss_param_set {
|
|||
} __packed;
|
||||
|
||||
struct mwifiex_fh_param_set {
|
||||
u16 dwell_time;
|
||||
__le16 dwell_time;
|
||||
u8 hop_set;
|
||||
u8 hop_pattern;
|
||||
u8 hop_index;
|
||||
|
@ -684,10 +684,10 @@ struct host_cmd_ds_802_11_key_material {
|
|||
} __packed;
|
||||
|
||||
struct host_cmd_ds_gen {
|
||||
u16 command;
|
||||
u16 size;
|
||||
u16 seq_num;
|
||||
u16 result;
|
||||
__le16 command;
|
||||
__le16 size;
|
||||
__le16 seq_num;
|
||||
__le16 result;
|
||||
};
|
||||
|
||||
#define S_DS_GEN sizeof(struct host_cmd_ds_gen)
|
||||
|
@ -820,8 +820,8 @@ struct ieee_types_cf_param_set {
|
|||
u8 len;
|
||||
u8 cfp_cnt;
|
||||
u8 cfp_period;
|
||||
u16 cfp_max_duration;
|
||||
u16 cfp_duration_remaining;
|
||||
__le16 cfp_max_duration;
|
||||
__le16 cfp_duration_remaining;
|
||||
} __packed;
|
||||
|
||||
struct ieee_types_ibss_param_set {
|
||||
|
@ -957,7 +957,7 @@ struct mwifiex_hs_config_param {
|
|||
} __packed;
|
||||
|
||||
struct hs_activate_param {
|
||||
u16 resp_ctrl;
|
||||
__le16 resp_ctrl;
|
||||
} __packed;
|
||||
|
||||
struct host_cmd_ds_802_11_hs_cfg_enh {
|
||||
|
@ -1131,7 +1131,7 @@ struct host_cmd_ds_802_11_bg_scan_query {
|
|||
} __packed;
|
||||
|
||||
struct host_cmd_ds_802_11_bg_scan_query_rsp {
|
||||
u32 report_condition;
|
||||
__le32 report_condition;
|
||||
struct host_cmd_ds_802_11_scan_rsp scan_resp;
|
||||
} __packed;
|
||||
|
||||
|
@ -1230,7 +1230,7 @@ struct mwifiex_ie_types_wmm_queue_status {
|
|||
struct mwifiex_ie_types_header header;
|
||||
u8 queue_index;
|
||||
u8 disabled;
|
||||
u16 medium_time;
|
||||
__le16 medium_time;
|
||||
u8 flow_required;
|
||||
u8 flow_created;
|
||||
u32 reserved;
|
||||
|
@ -1310,7 +1310,7 @@ struct mwifiex_ie_types_vht_oper {
|
|||
u8 chan_center_freq_1;
|
||||
u8 chan_center_freq_2;
|
||||
/* Basic MCS set map, each 2 bits stands for a NSS */
|
||||
u16 basic_mcs_map;
|
||||
__le16 basic_mcs_map;
|
||||
} __packed;
|
||||
|
||||
struct mwifiex_ie_types_wmmcap {
|
||||
|
|
|
@ -643,7 +643,8 @@ mwifiex_shutdown_drv(struct mwifiex_adapter *adapter)
|
|||
if (priv)
|
||||
priv->stats.rx_dropped++;
|
||||
|
||||
adapter->if_ops.data_complete(adapter, skb);
|
||||
dev_kfree_skb_any(skb);
|
||||
adapter->if_ops.data_complete(adapter);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
@ -648,6 +648,7 @@ mwifiex_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
|
|||
tx_info = MWIFIEX_SKB_TXCB(skb);
|
||||
tx_info->bss_num = priv->bss_num;
|
||||
tx_info->bss_type = priv->bss_type;
|
||||
tx_info->pkt_len = skb->len;
|
||||
|
||||
/* Record the current time the packet was queued; used to
|
||||
* determine the amount of time the packet was queued in
|
||||
|
@ -991,12 +992,8 @@ int mwifiex_remove_card(struct mwifiex_adapter *adapter, struct semaphore *sem)
|
|||
rtnl_unlock();
|
||||
}
|
||||
|
||||
priv = adapter->priv[0];
|
||||
if (!priv || !priv->wdev)
|
||||
goto exit_remove;
|
||||
|
||||
wiphy_unregister(priv->wdev->wiphy);
|
||||
wiphy_free(priv->wdev->wiphy);
|
||||
wiphy_unregister(adapter->wiphy);
|
||||
wiphy_free(adapter->wiphy);
|
||||
|
||||
mwifiex_terminate_workqueue(adapter);
|
||||
|
||||
|
|
|
@ -615,7 +615,7 @@ struct mwifiex_if_ops {
|
|||
void (*cleanup_mpa_buf) (struct mwifiex_adapter *);
|
||||
int (*cmdrsp_complete) (struct mwifiex_adapter *, struct sk_buff *);
|
||||
int (*event_complete) (struct mwifiex_adapter *, struct sk_buff *);
|
||||
int (*data_complete) (struct mwifiex_adapter *, struct sk_buff *);
|
||||
int (*data_complete) (struct mwifiex_adapter *);
|
||||
int (*init_fw_port) (struct mwifiex_adapter *);
|
||||
int (*dnld_fw) (struct mwifiex_adapter *, struct mwifiex_fw_image *);
|
||||
void (*card_reset) (struct mwifiex_adapter *);
|
||||
|
|
|
@ -354,7 +354,7 @@ mwifiex_cmd_802_11_hs_cfg(struct mwifiex_private *priv,
|
|||
}
|
||||
if (hs_activate) {
|
||||
hs_cfg->action = cpu_to_le16(HS_ACTIVATE);
|
||||
hs_cfg->params.hs_activate.resp_ctrl = RESP_NEEDED;
|
||||
hs_cfg->params.hs_activate.resp_ctrl = cpu_to_le16(RESP_NEEDED);
|
||||
} else {
|
||||
hs_cfg->action = cpu_to_le16(HS_CONFIGURE);
|
||||
hs_cfg->params.hs_config.conditions = hscfg_param->conditions;
|
||||
|
|
|
@ -36,12 +36,12 @@ mwifiex_discard_gratuitous_arp(struct mwifiex_private *priv,
|
|||
struct sk_buff *skb)
|
||||
{
|
||||
const struct mwifiex_arp_eth_header *arp;
|
||||
struct ethhdr *eth_hdr;
|
||||
struct ethhdr *eth;
|
||||
struct ipv6hdr *ipv6;
|
||||
struct icmp6hdr *icmpv6;
|
||||
|
||||
eth_hdr = (struct ethhdr *)skb->data;
|
||||
switch (ntohs(eth_hdr->h_proto)) {
|
||||
eth = (struct ethhdr *)skb->data;
|
||||
switch (ntohs(eth->h_proto)) {
|
||||
case ETH_P_ARP:
|
||||
arp = (void *)(skb->data + sizeof(struct ethhdr));
|
||||
if (arp->hdr.ar_op == htons(ARPOP_REPLY) ||
|
||||
|
@ -87,16 +87,19 @@ int mwifiex_process_rx_packet(struct mwifiex_private *priv,
|
|||
struct rx_packet_hdr *rx_pkt_hdr;
|
||||
struct rxpd *local_rx_pd;
|
||||
int hdr_chop;
|
||||
struct ethhdr *eth_hdr;
|
||||
u8 rfc1042_eth_hdr[ETH_ALEN] = { 0xaa, 0xaa, 0x03, 0x00, 0x00, 0x00 };
|
||||
struct ethhdr *eth;
|
||||
|
||||
local_rx_pd = (struct rxpd *) (skb->data);
|
||||
|
||||
rx_pkt_hdr = (void *)local_rx_pd +
|
||||
le16_to_cpu(local_rx_pd->rx_pkt_offset);
|
||||
|
||||
if (!memcmp(&rx_pkt_hdr->rfc1042_hdr,
|
||||
rfc1042_eth_hdr, sizeof(rfc1042_eth_hdr))) {
|
||||
if ((!memcmp(&rx_pkt_hdr->rfc1042_hdr, bridge_tunnel_header,
|
||||
sizeof(bridge_tunnel_header))) ||
|
||||
(!memcmp(&rx_pkt_hdr->rfc1042_hdr, rfc1042_header,
|
||||
sizeof(rfc1042_header)) &&
|
||||
ntohs(rx_pkt_hdr->rfc1042_hdr.snap_type) != ETH_P_AARP &&
|
||||
ntohs(rx_pkt_hdr->rfc1042_hdr.snap_type) != ETH_P_IPX)) {
|
||||
/*
|
||||
* Replace the 803 header and rfc1042 header (llc/snap) with an
|
||||
* EthernetII header, keep the src/dst and snap_type
|
||||
|
@ -106,7 +109,7 @@ int mwifiex_process_rx_packet(struct mwifiex_private *priv,
|
|||
* To create the Ethernet II, just move the src, dst address
|
||||
* right before the snap_type.
|
||||
*/
|
||||
eth_hdr = (struct ethhdr *)
|
||||
eth = (struct ethhdr *)
|
||||
((u8 *) &rx_pkt_hdr->eth803_hdr
|
||||
+ sizeof(rx_pkt_hdr->eth803_hdr) +
|
||||
sizeof(rx_pkt_hdr->rfc1042_hdr)
|
||||
|
@ -114,14 +117,14 @@ int mwifiex_process_rx_packet(struct mwifiex_private *priv,
|
|||
- sizeof(rx_pkt_hdr->eth803_hdr.h_source)
|
||||
- sizeof(rx_pkt_hdr->rfc1042_hdr.snap_type));
|
||||
|
||||
memcpy(eth_hdr->h_source, rx_pkt_hdr->eth803_hdr.h_source,
|
||||
sizeof(eth_hdr->h_source));
|
||||
memcpy(eth_hdr->h_dest, rx_pkt_hdr->eth803_hdr.h_dest,
|
||||
sizeof(eth_hdr->h_dest));
|
||||
memcpy(eth->h_source, rx_pkt_hdr->eth803_hdr.h_source,
|
||||
sizeof(eth->h_source));
|
||||
memcpy(eth->h_dest, rx_pkt_hdr->eth803_hdr.h_dest,
|
||||
sizeof(eth->h_dest));
|
||||
|
||||
/* Chop off the rxpd + the excess memory from the 802.2/llc/snap
|
||||
header that was removed. */
|
||||
hdr_chop = (u8 *) eth_hdr - (u8 *) local_rx_pd;
|
||||
hdr_chop = (u8 *) eth - (u8 *) local_rx_pd;
|
||||
} else {
|
||||
/* Chop off the rxpd */
|
||||
hdr_chop = (u8 *) &rx_pkt_hdr->eth803_hdr -
|
||||
|
@ -185,12 +188,7 @@ int mwifiex_process_sta_rx_packet(struct mwifiex_private *priv,
|
|||
"wrong rx packet: len=%d, rx_pkt_offset=%d, rx_pkt_length=%d\n",
|
||||
skb->len, rx_pkt_offset, rx_pkt_length);
|
||||
priv->stats.rx_dropped++;
|
||||
|
||||
if (adapter->if_ops.data_complete)
|
||||
adapter->if_ops.data_complete(adapter, skb);
|
||||
else
|
||||
dev_kfree_skb_any(skb);
|
||||
|
||||
dev_kfree_skb_any(skb);
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
@ -244,12 +242,8 @@ int mwifiex_process_sta_rx_packet(struct mwifiex_private *priv,
|
|||
ret = mwifiex_11n_rx_reorder_pkt(priv, seq_num, local_rx_pd->priority,
|
||||
ta, (u8) rx_pkt_type, skb);
|
||||
|
||||
if (ret || (rx_pkt_type == PKT_TYPE_BAR)) {
|
||||
if (adapter->if_ops.data_complete)
|
||||
adapter->if_ops.data_complete(adapter, skb);
|
||||
else
|
||||
dev_kfree_skb_any(skb);
|
||||
}
|
||||
if (ret || (rx_pkt_type == PKT_TYPE_BAR))
|
||||
dev_kfree_skb_any(skb);
|
||||
|
||||
if (ret)
|
||||
priv->stats.rx_dropped++;
|
||||
|
|
|
@ -148,6 +148,7 @@ int mwifiex_send_null_packet(struct mwifiex_private *priv, u8 flags)
|
|||
tx_info = MWIFIEX_SKB_TXCB(skb);
|
||||
tx_info->bss_num = priv->bss_num;
|
||||
tx_info->bss_type = priv->bss_type;
|
||||
tx_info->pkt_len = data_len - (sizeof(struct txpd) + INTF_HEADER_LEN);
|
||||
skb_reserve(skb, sizeof(struct txpd) + INTF_HEADER_LEN);
|
||||
skb_push(skb, sizeof(struct txpd));
|
||||
|
||||
|
|
|
@ -40,6 +40,7 @@ int mwifiex_handle_rx_packet(struct mwifiex_adapter *adapter,
|
|||
mwifiex_get_priv(adapter, MWIFIEX_BSS_ROLE_ANY);
|
||||
struct rxpd *local_rx_pd;
|
||||
struct mwifiex_rxinfo *rx_info = MWIFIEX_SKB_RXCB(skb);
|
||||
int ret;
|
||||
|
||||
local_rx_pd = (struct rxpd *) (skb->data);
|
||||
/* Get the BSS number from rxpd, get corresponding priv */
|
||||
|
@ -58,9 +59,15 @@ int mwifiex_handle_rx_packet(struct mwifiex_adapter *adapter,
|
|||
rx_info->bss_type = priv->bss_type;
|
||||
|
||||
if (priv->bss_role == MWIFIEX_BSS_ROLE_UAP)
|
||||
return mwifiex_process_uap_rx_packet(priv, skb);
|
||||
ret = mwifiex_process_uap_rx_packet(priv, skb);
|
||||
else
|
||||
ret = mwifiex_process_sta_rx_packet(priv, skb);
|
||||
|
||||
return mwifiex_process_sta_rx_packet(priv, skb);
|
||||
/* Decrement RX pending counter for each packet */
|
||||
if (adapter->if_ops.data_complete)
|
||||
adapter->if_ops.data_complete(adapter);
|
||||
|
||||
return ret;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(mwifiex_handle_rx_packet);
|
||||
|
||||
|
@ -105,7 +112,7 @@ int mwifiex_process_tx(struct mwifiex_private *priv, struct sk_buff *skb,
|
|||
|
||||
switch (ret) {
|
||||
case -ENOSR:
|
||||
dev_err(adapter->dev, "data: -ENOSR is returned\n");
|
||||
dev_dbg(adapter->dev, "data: -ENOSR is returned\n");
|
||||
break;
|
||||
case -EBUSY:
|
||||
if ((GET_BSS_ROLE(priv) == MWIFIEX_BSS_ROLE_STA) &&
|
||||
|
@ -168,7 +175,7 @@ int mwifiex_write_data_complete(struct mwifiex_adapter *adapter,
|
|||
mwifiex_set_trans_start(priv->netdev);
|
||||
if (!status) {
|
||||
priv->stats.tx_packets++;
|
||||
priv->stats.tx_bytes += skb->len;
|
||||
priv->stats.tx_bytes += tx_info->pkt_len;
|
||||
if (priv->tx_timeout_cnt)
|
||||
priv->tx_timeout_cnt = 0;
|
||||
} else {
|
||||
|
|
|
@ -98,7 +98,6 @@ static void mwifiex_uap_queue_bridged_pkt(struct mwifiex_private *priv,
|
|||
int hdr_chop;
|
||||
struct timeval tv;
|
||||
struct ethhdr *p_ethhdr;
|
||||
u8 rfc1042_eth_hdr[ETH_ALEN] = { 0xaa, 0xaa, 0x03, 0x00, 0x00, 0x00 };
|
||||
|
||||
uap_rx_pd = (struct uap_rxpd *)(skb->data);
|
||||
rx_pkt_hdr = (void *)uap_rx_pd + le16_to_cpu(uap_rx_pd->rx_pkt_offset);
|
||||
|
@ -112,8 +111,12 @@ static void mwifiex_uap_queue_bridged_pkt(struct mwifiex_private *priv,
|
|||
return;
|
||||
}
|
||||
|
||||
if (!memcmp(&rx_pkt_hdr->rfc1042_hdr,
|
||||
rfc1042_eth_hdr, sizeof(rfc1042_eth_hdr))) {
|
||||
if ((!memcmp(&rx_pkt_hdr->rfc1042_hdr, bridge_tunnel_header,
|
||||
sizeof(bridge_tunnel_header))) ||
|
||||
(!memcmp(&rx_pkt_hdr->rfc1042_hdr, rfc1042_header,
|
||||
sizeof(rfc1042_header)) &&
|
||||
ntohs(rx_pkt_hdr->rfc1042_hdr.snap_type) != ETH_P_AARP &&
|
||||
ntohs(rx_pkt_hdr->rfc1042_hdr.snap_type) != ETH_P_IPX)) {
|
||||
/* Replace the 803 header and rfc1042 header (llc/snap) with
|
||||
* an Ethernet II header, keep the src/dst and snap_type
|
||||
* (ethertype).
|
||||
|
@ -144,7 +147,7 @@ static void mwifiex_uap_queue_bridged_pkt(struct mwifiex_private *priv,
|
|||
hdr_chop = (u8 *)&rx_pkt_hdr->eth803_hdr - (u8 *)uap_rx_pd;
|
||||
}
|
||||
|
||||
/* Chop off the leading header bytes so the it points
|
||||
/* Chop off the leading header bytes so that it points
|
||||
* to the start of either the reconstructed EthII frame
|
||||
* or the 802.2/llc/snap frame.
|
||||
*/
|
||||
|
@ -176,6 +179,19 @@ static void mwifiex_uap_queue_bridged_pkt(struct mwifiex_private *priv,
|
|||
tx_info->bss_type = priv->bss_type;
|
||||
tx_info->flags |= MWIFIEX_BUF_FLAG_BRIDGED_PKT;
|
||||
|
||||
if (is_unicast_ether_addr(rx_pkt_hdr->eth803_hdr.h_dest)) {
|
||||
/* Update bridge packet statistics as the
|
||||
* packet is not going to kernel/upper layer.
|
||||
*/
|
||||
priv->stats.rx_bytes += skb->len;
|
||||
priv->stats.rx_packets++;
|
||||
|
||||
/* Sending bridge packet to TX queue, so save the packet
|
||||
* length in TXCB to update statistics in TX complete.
|
||||
*/
|
||||
tx_info->pkt_len = skb->len;
|
||||
}
|
||||
|
||||
do_gettimeofday(&tv);
|
||||
skb->tstamp = timeval_to_ktime(tv);
|
||||
mwifiex_wmm_add_buf_txqueue(priv, skb);
|
||||
|
@ -264,12 +280,7 @@ int mwifiex_process_uap_rx_packet(struct mwifiex_private *priv,
|
|||
skb->len, le16_to_cpu(uap_rx_pd->rx_pkt_offset),
|
||||
le16_to_cpu(uap_rx_pd->rx_pkt_length));
|
||||
priv->stats.rx_dropped++;
|
||||
|
||||
if (adapter->if_ops.data_complete)
|
||||
adapter->if_ops.data_complete(adapter, skb);
|
||||
else
|
||||
dev_kfree_skb_any(skb);
|
||||
|
||||
dev_kfree_skb_any(skb);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
@ -323,12 +334,8 @@ int mwifiex_process_uap_rx_packet(struct mwifiex_private *priv,
|
|||
uap_rx_pd->priority, ta, pkt_type,
|
||||
skb);
|
||||
|
||||
if (ret || (rx_pkt_type == PKT_TYPE_BAR)) {
|
||||
if (adapter->if_ops.data_complete)
|
||||
adapter->if_ops.data_complete(adapter, skb);
|
||||
else
|
||||
dev_kfree_skb_any(skb);
|
||||
}
|
||||
if (ret || (rx_pkt_type == PKT_TYPE_BAR))
|
||||
dev_kfree_skb_any(skb);
|
||||
|
||||
if (ret)
|
||||
priv->stats.rx_dropped++;
|
||||
|
|
|
@ -938,11 +938,9 @@ static int mwifiex_usb_cmd_event_complete(struct mwifiex_adapter *adapter,
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int mwifiex_usb_data_complete(struct mwifiex_adapter *adapter,
|
||||
struct sk_buff *skb)
|
||||
static int mwifiex_usb_data_complete(struct mwifiex_adapter *adapter)
|
||||
{
|
||||
atomic_dec(&adapter->rx_pending);
|
||||
dev_kfree_skb_any(skb);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
@ -191,6 +191,9 @@ int mwifiex_recv_packet(struct mwifiex_private *priv, struct sk_buff *skb)
|
|||
if (!skb)
|
||||
return -1;
|
||||
|
||||
priv->stats.rx_bytes += skb->len;
|
||||
priv->stats.rx_packets++;
|
||||
|
||||
skb->dev = priv->netdev;
|
||||
skb->protocol = eth_type_trans(skb, priv->netdev);
|
||||
skb->ip_summed = CHECKSUM_NONE;
|
||||
|
@ -217,8 +220,6 @@ int mwifiex_recv_packet(struct mwifiex_private *priv, struct sk_buff *skb)
|
|||
(skb->truesize > MWIFIEX_RX_DATA_BUF_SIZE))
|
||||
skb->truesize += (skb->len - MWIFIEX_RX_DATA_BUF_SIZE);
|
||||
|
||||
priv->stats.rx_bytes += skb->len;
|
||||
priv->stats.rx_packets++;
|
||||
if (in_interrupt())
|
||||
netif_rx(skb);
|
||||
else
|
||||
|
|
|
@ -20,8 +20,7 @@
|
|||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
* along with this program; if not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
/*-------------------------------------------------------------------------*/
|
||||
|
|
|
@ -12,8 +12,7 @@
|
|||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
* along with this program; if not, see <http://www.gnu.org/licenses/>.
|
||||
*
|
||||
*/
|
||||
|
||||
|
|
Some files were not shown because too many files have changed in this diff Show more
Loading…
Reference in a new issue