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PCI: aerdrv: redefine PCI_ERR_ROOT_*_SRC

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The Error Source Identification Register (Offset 34h) is 4 byte
which contains a couple of 2 byte field, "[15:0] ERR_COR Source
Identification" and "[31:16] ERR_FATAL/NONFATAL Source Identification."

This patch defines PCI_ERR_ROOT_ERR_SRC to make dword access sensible.

Signed-off-by: Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com>
Reviewed-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
This commit is contained in:
Hidetoshi Seto 2010-04-15 13:17:33 +09:00 committed by Jesse Barnes
parent 17e21854bd
commit f647a44f57
3 changed files with 3 additions and 4 deletions
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2
drivers/pci/pcie/aer/aer_inject.c
View file

@ -168,7 +168,7 @@ static u32 *find_pci_config_dword(struct aer_error *err, int where,
target = &err->root_status; target = &err->root_status;
rw1cs = 1; rw1cs = 1;
break; break;
case PCI_ERR_ROOT_COR_SRC: case PCI_ERR_ROOT_ERR_SRC:
target = &err->source_id; target = &err->source_id;
break; break;
} }

2
drivers/pci/pcie/aer/aerdrv.c
View file

@ -210,7 +210,7 @@ irqreturn_t aer_irq(int irq, void *context)
} }
/* Read error source and clear error status */ /* Read error source and clear error status */
pci_read_config_dword(pdev->port, pos + PCI_ERR_ROOT_COR_SRC, &id); pci_read_config_dword(pdev->port, pos + PCI_ERR_ROOT_ERR_SRC, &id);
pci_write_config_dword(pdev->port, pos + PCI_ERR_ROOT_STATUS, status); pci_write_config_dword(pdev->port, pos + PCI_ERR_ROOT_STATUS, status);
/* Store error source for later DPC handler */ /* Store error source for later DPC handler */

3
include/linux/pci_regs.h
View file

@ -563,8 +563,7 @@
#define PCI_ERR_ROOT_FIRST_FATAL 0x00000010 /* First Fatal */ #define PCI_ERR_ROOT_FIRST_FATAL 0x00000010 /* First Fatal */
#define PCI_ERR_ROOT_NONFATAL_RCV 0x00000020 /* Non-Fatal Received */ #define PCI_ERR_ROOT_NONFATAL_RCV 0x00000020 /* Non-Fatal Received */
#define PCI_ERR_ROOT_FATAL_RCV 0x00000040 /* Fatal Received */ #define PCI_ERR_ROOT_FATAL_RCV 0x00000040 /* Fatal Received */
#define PCI_ERR_ROOT_COR_SRC 52 #define PCI_ERR_ROOT_ERR_SRC 52 /* Error Source Identification */
#define PCI_ERR_ROOT_SRC 54
/* Virtual Channel */ /* Virtual Channel */
#define PCI_VC_PORT_REG1 4 #define PCI_VC_PORT_REG1 4