spi: spi-imx: add DMA support
Enable DMA support on i.mx6. The read speed can increase from 600KB/s to 1.2MB/s on i.mx6q. You can disable or enable dma function in dts. If not set "dma-names" in dts, spi will use PIO mode. This patch only validate on i.mx6, not i.mx5, but encourage ones to apply this patch on i.mx5 since they share the same IP. Note: Sometime, there is a weid data in rxfifo after one full tx/rx transfer finish by DMA on i.mx6dl, so we disable dma functhion on i.mx6dl. Signed-off-by: Frank Li <Frank.Li@freescale.com> Signed-off-by: Robin Gong <b38343@freescale.com> Acked-by: Marek Vasut <marex@denx.de> Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Robin Gong
Mark Brown
parent
7d1311b93e
commit
f62caccd12
2 changed files with 284 additions and 5 deletions
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@ -7,6 +7,9 @@ Required properties:
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- interrupts : Should contain CSPI/eCSPI interrupt
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- fsl,spi-num-chipselects : Contains the number of the chipselect
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- cs-gpios : Specifies the gpio pins to be used for chipselects.
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- dmas: DMA specifiers for tx and rx dma. See the DMA client binding,
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Documentation/devicetree/bindings/dma/dma.txt
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- dma-names: DMA request names should include "tx" and "rx" if present.
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Example:
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@ -19,4 +22,6 @@ ecspi@70010000 {
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fsl,spi-num-chipselects = <2>;
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cs-gpios = <&gpio3 24 0>, /* GPIO3_24 */
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<&gpio3 25 0>; /* GPIO3_25 */
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dmas = <&sdma 3 7 1>, <&sdma 4 7 2>;
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dma-names = "rx", "tx";
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};
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@ -21,6 +21,8 @@
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#include <linux/clk.h>
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#include <linux/completion.h>
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#include <linux/delay.h>
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#include <linux/dmaengine.h>
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#include <linux/dma-mapping.h>
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#include <linux/err.h>
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#include <linux/gpio.h>
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#include <linux/interrupt.h>
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@ -37,6 +39,7 @@
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#include <linux/of_device.h>
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#include <linux/of_gpio.h>
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#include <linux/platform_data/dma-imx.h>
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#include <linux/platform_data/spi-imx.h>
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#define DRIVER_NAME "spi_imx"
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@ -51,6 +54,9 @@
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#define MXC_INT_RR (1 << 0) /* Receive data ready interrupt */
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#define MXC_INT_TE (1 << 1) /* Transmit FIFO empty interrupt */
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/* The maximum bytes that a sdma BD can transfer.*/
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#define MAX_SDMA_BD_BYTES (1 << 15)
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#define IMX_DMA_TIMEOUT (msecs_to_jiffies(3000))
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struct spi_imx_config {
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unsigned int speed_hz;
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unsigned int bpw;
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@ -95,6 +101,16 @@ struct spi_imx_data {
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const void *tx_buf;
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unsigned int txfifo; /* number of words pushed in tx FIFO */
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/* DMA */
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unsigned int dma_is_inited;
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unsigned int dma_finished;
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bool usedma;
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u32 rx_wml;
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u32 tx_wml;
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u32 rxt_wml;
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struct completion dma_rx_completion;
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struct completion dma_tx_completion;
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const struct spi_imx_devtype_data *devtype_data;
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int chipselect[0];
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};
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@ -181,9 +197,21 @@ static unsigned int spi_imx_clkdiv_2(unsigned int fin,
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return 7;
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}
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static bool spi_imx_can_dma(struct spi_master *master, struct spi_device *spi,
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struct spi_transfer *transfer)
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{
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struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
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if (spi_imx->dma_is_inited && (transfer->len > spi_imx->rx_wml)
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&& (transfer->len > spi_imx->tx_wml))
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return true;
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return false;
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}
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#define MX51_ECSPI_CTRL 0x08
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#define MX51_ECSPI_CTRL_ENABLE (1 << 0)
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#define MX51_ECSPI_CTRL_XCH (1 << 2)
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#define MX51_ECSPI_CTRL_SMC (1 << 3)
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#define MX51_ECSPI_CTRL_MODE_MASK (0xf << 4)
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#define MX51_ECSPI_CTRL_POSTDIV_OFFSET 8
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#define MX51_ECSPI_CTRL_PREDIV_OFFSET 12
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@ -201,6 +229,18 @@ static unsigned int spi_imx_clkdiv_2(unsigned int fin,
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#define MX51_ECSPI_INT_TEEN (1 << 0)
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#define MX51_ECSPI_INT_RREN (1 << 3)
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#define MX51_ECSPI_DMA 0x14
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#define MX51_ECSPI_DMA_TX_WML_OFFSET 0
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#define MX51_ECSPI_DMA_TX_WML_MASK 0x3F
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#define MX51_ECSPI_DMA_RX_WML_OFFSET 16
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#define MX51_ECSPI_DMA_RX_WML_MASK (0x3F << 16)
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#define MX51_ECSPI_DMA_RXT_WML_OFFSET 24
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#define MX51_ECSPI_DMA_RXT_WML_MASK (0x3F << 24)
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#define MX51_ECSPI_DMA_TEDEN_OFFSET 7
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#define MX51_ECSPI_DMA_RXDEN_OFFSET 23
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#define MX51_ECSPI_DMA_RXTDEN_OFFSET 31
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#define MX51_ECSPI_STAT 0x18
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#define MX51_ECSPI_STAT_RR (1 << 3)
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@ -257,17 +297,22 @@ static void __maybe_unused mx51_ecspi_intctrl(struct spi_imx_data *spi_imx, int
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static void __maybe_unused mx51_ecspi_trigger(struct spi_imx_data *spi_imx)
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{
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u32 reg;
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u32 reg = readl(spi_imx->base + MX51_ECSPI_CTRL);
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reg = readl(spi_imx->base + MX51_ECSPI_CTRL);
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reg |= MX51_ECSPI_CTRL_XCH;
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if (!spi_imx->usedma)
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reg |= MX51_ECSPI_CTRL_XCH;
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else if (!spi_imx->dma_finished)
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reg |= MX51_ECSPI_CTRL_SMC;
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else
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reg &= ~MX51_ECSPI_CTRL_SMC;
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writel(reg, spi_imx->base + MX51_ECSPI_CTRL);
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}
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static int __maybe_unused mx51_ecspi_config(struct spi_imx_data *spi_imx,
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struct spi_imx_config *config)
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{
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u32 ctrl = MX51_ECSPI_CTRL_ENABLE, cfg = 0;
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u32 ctrl = MX51_ECSPI_CTRL_ENABLE, cfg = 0, dma = 0;
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u32 tx_wml_cfg, rx_wml_cfg, rxt_wml_cfg;
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u32 clk = config->speed_hz, delay;
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/*
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@ -319,6 +364,30 @@ static int __maybe_unused mx51_ecspi_config(struct spi_imx_data *spi_imx,
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else /* SCLK is _very_ slow */
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usleep_range(delay, delay + 10);
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/*
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* Configure the DMA register: setup the watermark
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* and enable DMA request.
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*/
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if (spi_imx->dma_is_inited) {
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dma = readl(spi_imx->base + MX51_ECSPI_DMA);
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spi_imx->tx_wml = spi_imx_get_fifosize(spi_imx) / 2;
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spi_imx->rx_wml = spi_imx_get_fifosize(spi_imx) / 2;
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spi_imx->rxt_wml = spi_imx_get_fifosize(spi_imx) / 2;
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rx_wml_cfg = spi_imx->rx_wml << MX51_ECSPI_DMA_RX_WML_OFFSET;
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tx_wml_cfg = spi_imx->tx_wml << MX51_ECSPI_DMA_TX_WML_OFFSET;
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rxt_wml_cfg = spi_imx->rxt_wml << MX51_ECSPI_DMA_RXT_WML_OFFSET;
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dma = (dma & ~MX51_ECSPI_DMA_TX_WML_MASK
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& ~MX51_ECSPI_DMA_RX_WML_MASK
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& ~MX51_ECSPI_DMA_RXT_WML_MASK)
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| rx_wml_cfg | tx_wml_cfg | rxt_wml_cfg
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|(1 << MX51_ECSPI_DMA_TEDEN_OFFSET)
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|(1 << MX51_ECSPI_DMA_RXDEN_OFFSET)
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|(1 << MX51_ECSPI_DMA_RXTDEN_OFFSET);
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writel(dma, spi_imx->base + MX51_ECSPI_DMA);
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}
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return 0;
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}
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@ -730,7 +799,186 @@ static int spi_imx_setupxfer(struct spi_device *spi,
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return 0;
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}
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static int spi_imx_transfer(struct spi_device *spi,
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static void spi_imx_sdma_exit(struct spi_imx_data *spi_imx)
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{
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struct spi_master *master = spi_imx->bitbang.master;
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if (master->dma_rx) {
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dma_release_channel(master->dma_rx);
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master->dma_rx = NULL;
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}
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if (master->dma_tx) {
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dma_release_channel(master->dma_tx);
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master->dma_tx = NULL;
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}
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spi_imx->dma_is_inited = 0;
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}
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static int spi_imx_sdma_init(struct device *dev, struct spi_imx_data *spi_imx,
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struct spi_master *master,
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const struct resource *res)
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{
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struct dma_slave_config slave_config = {};
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int ret;
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/* Prepare for TX DMA: */
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master->dma_tx = dma_request_slave_channel(dev, "tx");
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if (!master->dma_tx) {
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dev_err(dev, "cannot get the TX DMA channel!\n");
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ret = -EINVAL;
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goto err;
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}
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slave_config.direction = DMA_MEM_TO_DEV;
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slave_config.dst_addr = res->start + MXC_CSPITXDATA;
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slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
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slave_config.dst_maxburst = spi_imx_get_fifosize(spi_imx) / 2;
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ret = dmaengine_slave_config(master->dma_tx, &slave_config);
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if (ret) {
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dev_err(dev, "error in TX dma configuration.\n");
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goto err;
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}
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/* Prepare for RX : */
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master->dma_rx = dma_request_slave_channel(dev, "rx");
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if (!master->dma_rx) {
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dev_dbg(dev, "cannot get the DMA channel.\n");
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ret = -EINVAL;
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goto err;
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}
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slave_config.direction = DMA_DEV_TO_MEM;
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slave_config.src_addr = res->start + MXC_CSPIRXDATA;
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slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
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slave_config.src_maxburst = spi_imx_get_fifosize(spi_imx) / 2;
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ret = dmaengine_slave_config(master->dma_rx, &slave_config);
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if (ret) {
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dev_err(dev, "error in RX dma configuration.\n");
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goto err;
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}
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init_completion(&spi_imx->dma_rx_completion);
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init_completion(&spi_imx->dma_tx_completion);
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master->can_dma = spi_imx_can_dma;
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master->max_dma_len = MAX_SDMA_BD_BYTES;
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spi_imx->bitbang.master->flags = SPI_MASTER_MUST_RX |
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SPI_MASTER_MUST_TX;
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spi_imx->dma_is_inited = 1;
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return 0;
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err:
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spi_imx_sdma_exit(spi_imx);
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return ret;
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}
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static void spi_imx_dma_rx_callback(void *cookie)
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{
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struct spi_imx_data *spi_imx = (struct spi_imx_data *)cookie;
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complete(&spi_imx->dma_rx_completion);
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}
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static void spi_imx_dma_tx_callback(void *cookie)
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{
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struct spi_imx_data *spi_imx = (struct spi_imx_data *)cookie;
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complete(&spi_imx->dma_tx_completion);
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}
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static int spi_imx_dma_transfer(struct spi_imx_data *spi_imx,
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struct spi_transfer *transfer)
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{
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struct dma_async_tx_descriptor *desc_tx = NULL, *desc_rx = NULL;
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int ret;
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u32 dma;
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int left;
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struct spi_master *master = spi_imx->bitbang.master;
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struct sg_table *tx = &transfer->tx_sg, *rx = &transfer->rx_sg;
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if (tx) {
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desc_tx = dmaengine_prep_slave_sg(master->dma_tx,
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tx->sgl, tx->nents, DMA_TO_DEVICE,
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DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
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if (!desc_tx)
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goto no_dma;
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desc_tx->callback = spi_imx_dma_tx_callback;
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desc_tx->callback_param = (void *)spi_imx;
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dmaengine_submit(desc_tx);
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}
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if (rx) {
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desc_rx = dmaengine_prep_slave_sg(master->dma_rx,
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rx->sgl, rx->nents, DMA_FROM_DEVICE,
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DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
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if (!desc_rx)
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goto no_dma;
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desc_rx->callback = spi_imx_dma_rx_callback;
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desc_rx->callback_param = (void *)spi_imx;
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dmaengine_submit(desc_rx);
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}
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reinit_completion(&spi_imx->dma_rx_completion);
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reinit_completion(&spi_imx->dma_tx_completion);
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/* Trigger the cspi module. */
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spi_imx->dma_finished = 0;
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dma = readl(spi_imx->base + MX51_ECSPI_DMA);
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dma = dma & (~MX51_ECSPI_DMA_RXT_WML_MASK);
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/* Change RX_DMA_LENGTH trigger dma fetch tail data */
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left = transfer->len % spi_imx->rxt_wml;
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if (left)
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writel(dma | (left << MX51_ECSPI_DMA_RXT_WML_OFFSET),
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spi_imx->base + MX51_ECSPI_DMA);
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spi_imx->devtype_data->trigger(spi_imx);
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dma_async_issue_pending(master->dma_tx);
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dma_async_issue_pending(master->dma_rx);
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/* Wait SDMA to finish the data transfer.*/
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ret = wait_for_completion_timeout(&spi_imx->dma_tx_completion,
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IMX_DMA_TIMEOUT);
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if (!ret) {
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pr_warn("%s %s: I/O Error in DMA TX\n",
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dev_driver_string(&master->dev),
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dev_name(&master->dev));
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dmaengine_terminate_all(master->dma_tx);
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} else {
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ret = wait_for_completion_timeout(&spi_imx->dma_rx_completion,
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IMX_DMA_TIMEOUT);
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if (!ret) {
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pr_warn("%s %s: I/O Error in DMA RX\n",
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dev_driver_string(&master->dev),
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dev_name(&master->dev));
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spi_imx->devtype_data->reset(spi_imx);
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dmaengine_terminate_all(master->dma_rx);
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}
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writel(dma |
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spi_imx->rxt_wml << MX51_ECSPI_DMA_RXT_WML_OFFSET,
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spi_imx->base + MX51_ECSPI_DMA);
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}
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spi_imx->dma_finished = 1;
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spi_imx->devtype_data->trigger(spi_imx);
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if (!ret)
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ret = -ETIMEDOUT;
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else if (ret > 0)
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ret = transfer->len;
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return ret;
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no_dma:
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pr_warn_once("%s %s: DMA not available, falling back to PIO\n",
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dev_driver_string(&master->dev),
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dev_name(&master->dev));
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return -EAGAIN;
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}
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static int spi_imx_pio_transfer(struct spi_device *spi,
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struct spi_transfer *transfer)
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{
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struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
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@ -751,6 +999,24 @@ static int spi_imx_transfer(struct spi_device *spi,
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return transfer->len;
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}
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static int spi_imx_transfer(struct spi_device *spi,
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struct spi_transfer *transfer)
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{
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int ret;
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struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
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if (spi_imx->bitbang.master->can_dma &&
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spi_imx_can_dma(spi_imx->bitbang.master, spi, transfer)) {
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spi_imx->usedma = true;
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ret = spi_imx_dma_transfer(spi_imx, transfer);
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if (ret != -EAGAIN)
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return ret;
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}
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spi_imx->usedma = false;
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return spi_imx_pio_transfer(spi, transfer);
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}
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static int spi_imx_setup(struct spi_device *spi)
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{
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struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
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@ -911,6 +1177,13 @@ static int spi_imx_probe(struct platform_device *pdev)
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goto out_put_per;
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spi_imx->spi_clk = clk_get_rate(spi_imx->clk_per);
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/*
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* Only validated on i.mx6 now, can remove the constrain if validated on
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* other chips.
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*/
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if (spi_imx->devtype_data == &imx51_ecspi_devtype_data
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&& spi_imx_sdma_init(&pdev->dev, spi_imx, master, res))
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dev_err(&pdev->dev, "dma setup error,use pio instead\n");
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spi_imx->devtype_data->reset(spi_imx);
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@ -949,6 +1222,7 @@ static int spi_imx_remove(struct platform_device *pdev)
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writel(0, spi_imx->base + MXC_CSPICTRL);
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clk_unprepare(spi_imx->clk_ipg);
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clk_unprepare(spi_imx->clk_per);
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spi_imx_sdma_exit(spi_imx);
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spi_master_put(master);
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return 0;
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