[TG3]: Handle Sun onboard tg3 chips more correctly.
Get rid of all the SUN_570X logic and instead: 1) Make sure MEMARB_ENABLE is set when we probe the SRAM for config information. If that is off we will get timeouts. 2) Always try to sync with the firmware, if there is no firmware running do not treat it as an error and instead just report it the first time we notice this condition. 3) If there is no valid SRAM signature, assume the device is onboard by setting TG3_FLAG_EEPROM_WRITE_PROT. Update driver version and release date. With help from Michael Chan and Fabio Massimo Di Nitto. Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller
parent
5224e6cc3a
commit
f49639e643
2 changed files with 50 additions and 97 deletions
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@ -69,8 +69,8 @@
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#define DRV_MODULE_NAME "tg3"
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#define PFX DRV_MODULE_NAME ": "
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#define DRV_MODULE_VERSION "3.58"
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#define DRV_MODULE_RELDATE "May 22, 2006"
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#define DRV_MODULE_VERSION "3.59"
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#define DRV_MODULE_RELDATE "June 8, 2006"
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#define TG3_DEF_MAC_MODE 0
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#define TG3_DEF_RX_MODE 0
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@ -4485,9 +4485,8 @@ static void tg3_disable_nvram_access(struct tg3 *tp)
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/* tp->lock is held. */
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static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
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{
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if (!(tp->tg3_flags2 & TG3_FLG2_SUN_570X))
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tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
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NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
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tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
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NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
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if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
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switch (kind) {
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@ -4568,13 +4567,12 @@ static int tg3_chip_reset(struct tg3 *tp)
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void (*write_op)(struct tg3 *, u32, u32);
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int i;
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if (!(tp->tg3_flags2 & TG3_FLG2_SUN_570X)) {
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tg3_nvram_lock(tp);
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/* No matching tg3_nvram_unlock() after this because
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* chip reset below will undo the nvram lock.
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*/
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tp->nvram_lock_cnt = 0;
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}
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tg3_nvram_lock(tp);
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/* No matching tg3_nvram_unlock() after this because
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* chip reset below will undo the nvram lock.
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*/
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tp->nvram_lock_cnt = 0;
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
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@ -4727,20 +4725,25 @@ static int tg3_chip_reset(struct tg3 *tp)
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tw32_f(MAC_MODE, 0);
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udelay(40);
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if (!(tp->tg3_flags2 & TG3_FLG2_SUN_570X)) {
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/* Wait for firmware initialization to complete. */
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for (i = 0; i < 100000; i++) {
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tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
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if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
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break;
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udelay(10);
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}
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if (i >= 100000) {
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printk(KERN_ERR PFX "tg3_reset_hw timed out for %s, "
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"firmware will not restart magic=%08x\n",
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tp->dev->name, val);
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return -ENODEV;
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}
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/* Wait for firmware initialization to complete. */
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for (i = 0; i < 100000; i++) {
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tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
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if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
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break;
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udelay(10);
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}
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/* Chip might not be fitted with firmare. Some Sun onboard
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* parts are configured like that. So don't signal the timeout
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* of the above loop as an error, but do report the lack of
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* running firmware once.
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*/
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if (i >= 100000 &&
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!(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
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tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
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printk(KERN_INFO PFX "%s: No firmware running.\n",
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tp->dev->name);
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}
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if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
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@ -9075,9 +9078,6 @@ static void __devinit tg3_nvram_init(struct tg3 *tp)
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{
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int j;
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if (tp->tg3_flags2 & TG3_FLG2_SUN_570X)
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return;
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tw32_f(GRC_EEPROM_ADDR,
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(EEPROM_ADDR_FSM_RESET |
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(EEPROM_DEFAULT_CLOCK_PERIOD <<
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@ -9210,11 +9210,6 @@ static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
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{
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int ret;
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if (tp->tg3_flags2 & TG3_FLG2_SUN_570X) {
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printk(KERN_ERR PFX "Attempt to do nvram_read on Sun 570X\n");
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return -EINVAL;
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}
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if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
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return tg3_nvram_read_using_eeprom(tp, offset, val);
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@ -9447,11 +9442,6 @@ static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
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{
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int ret;
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if (tp->tg3_flags2 & TG3_FLG2_SUN_570X) {
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printk(KERN_ERR PFX "Attempt to do nvram_write on Sun 570X\n");
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return -EINVAL;
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}
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if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
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tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
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~GRC_LCLCTRL_GPIO_OUTPUT1);
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@ -9578,15 +9568,19 @@ static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
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pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
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tp->misc_host_ctrl);
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/* The memory arbiter has to be enabled in order for SRAM accesses
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* to succeed. Normally on powerup the tg3 chip firmware will make
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* sure it is enabled, but other entities such as system netboot
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* code might disable it.
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*/
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val = tr32(MEMARB_MODE);
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tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
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tp->phy_id = PHY_ID_INVALID;
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tp->led_ctrl = LED_CTRL_MODE_PHY_1;
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/* Do not even try poking around in here on Sun parts. */
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if (tp->tg3_flags2 & TG3_FLG2_SUN_570X) {
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/* All SUN chips are built-in LOMs. */
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tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
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return;
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}
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/* Assume an onboard device by default. */
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tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
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tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
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if (val == NIC_SRAM_DATA_SIG_MAGIC) {
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@ -9686,6 +9680,8 @@ static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
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if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP)
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tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
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else
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tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
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if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
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tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
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@ -9834,16 +9830,8 @@ static void __devinit tg3_read_partno(struct tg3 *tp)
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int i;
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u32 magic;
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if (tp->tg3_flags2 & TG3_FLG2_SUN_570X) {
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/* Sun decided not to put the necessary bits in the
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* NVRAM of their onboard tg3 parts :(
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*/
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strcpy(tp->board_part_number, "Sun 570X");
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return;
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}
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if (tg3_nvram_read_swab(tp, 0x0, &magic))
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return;
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goto out_not_found;
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if (magic == TG3_EEPROM_MAGIC) {
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for (i = 0; i < 256; i += 4) {
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@ -9874,6 +9862,9 @@ static void __devinit tg3_read_partno(struct tg3 *tp)
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break;
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msleep(1);
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}
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if (!(tmp16 & 0x8000))
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goto out_not_found;
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pci_read_config_dword(tp->pdev, vpd_cap + PCI_VPD_DATA,
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&tmp);
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tmp = cpu_to_le32(tmp);
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@ -9965,37 +9956,6 @@ static void __devinit tg3_read_fw_ver(struct tg3 *tp)
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}
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}
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#ifdef CONFIG_SPARC64
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static int __devinit tg3_is_sun_570X(struct tg3 *tp)
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{
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struct pci_dev *pdev = tp->pdev;
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struct pcidev_cookie *pcp = pdev->sysdata;
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if (pcp != NULL) {
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int node = pcp->prom_node;
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u32 venid;
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int err;
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err = prom_getproperty(node, "subsystem-vendor-id",
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(char *) &venid, sizeof(venid));
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if (err == 0 || err == -1)
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return 0;
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if (venid == PCI_VENDOR_ID_SUN)
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return 1;
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/* TG3 chips onboard the SunBlade-2500 don't have the
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* subsystem-vendor-id set to PCI_VENDOR_ID_SUN but they
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* are distinguishable from non-Sun variants by being
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* named "network" by the firmware. Non-Sun cards will
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* show up as being named "ethernet".
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*/
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if (!strcmp(pcp->prom_name, "network"))
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return 1;
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}
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return 0;
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}
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#endif
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static int __devinit tg3_get_invariants(struct tg3 *tp)
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{
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static struct pci_device_id write_reorder_chipsets[] = {
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@ -10012,11 +9972,6 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
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u16 pci_cmd;
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int err;
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#ifdef CONFIG_SPARC64
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if (tg3_is_sun_570X(tp))
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tp->tg3_flags2 |= TG3_FLG2_SUN_570X;
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#endif
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/* Force memory write invalidate off. If we leave it on,
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* then on 5700_BX chips we have to enable a workaround.
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* The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
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@ -10312,8 +10267,7 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
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if (tp->write32 == tg3_write_indirect_reg32 ||
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((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
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(GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) ||
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(tp->tg3_flags2 & TG3_FLG2_SUN_570X))
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
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tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
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/* Get eeprom hw config before calling tg3_set_power_state().
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@ -10594,8 +10548,7 @@ static int __devinit tg3_get_device_address(struct tg3 *tp)
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#endif
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mac_offset = 0x7c;
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if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
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!(tp->tg3_flags & TG3_FLG2_SUN_570X)) ||
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if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
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(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
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if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
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mac_offset = 0xcc;
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@ -10622,8 +10575,7 @@ static int __devinit tg3_get_device_address(struct tg3 *tp)
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}
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if (!addr_ok) {
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/* Next, try NVRAM. */
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if (!(tp->tg3_flags & TG3_FLG2_SUN_570X) &&
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!tg3_nvram_read(tp, mac_offset + 0, &hi) &&
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if (!tg3_nvram_read(tp, mac_offset + 0, &hi) &&
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!tg3_nvram_read(tp, mac_offset + 4, &lo)) {
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dev->dev_addr[0] = ((hi >> 16) & 0xff);
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dev->dev_addr[1] = ((hi >> 24) & 0xff);
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@ -2184,7 +2184,7 @@ struct tg3 {
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#define TG3_FLAG_INIT_COMPLETE 0x80000000
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u32 tg3_flags2;
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#define TG3_FLG2_RESTART_TIMER 0x00000001
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#define TG3_FLG2_SUN_570X 0x00000002
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/* 0x00000002 available */
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#define TG3_FLG2_NO_ETH_WIRE_SPEED 0x00000004
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#define TG3_FLG2_IS_5788 0x00000008
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#define TG3_FLG2_MAX_RXPEND_64 0x00000010
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@ -2216,6 +2216,7 @@ struct tg3 {
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#define TG3_FLG2_HW_TSO (TG3_FLG2_HW_TSO_1 | TG3_FLG2_HW_TSO_2)
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#define TG3_FLG2_1SHOT_MSI 0x10000000
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#define TG3_FLG2_PHY_JITTER_BUG 0x20000000
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#define TG3_FLG2_NO_FWARE_REPORTED 0x40000000
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u32 split_mode_max_reqs;
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#define SPLIT_MODE_5704_MAX_REQ 3
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