amd-xgbe: Fix the ECC-related bit position definitions
The ECC bit positions that describe whether the ECC interrupt is for Tx, Rx or descriptor memory and whether the it is a single correctable or double detected error were defined in incorrectly (reversed order). Fix the bit position definitions for these settings so that the proper ECC handling is performed. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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1 changed files with 12 additions and 12 deletions
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@ -984,29 +984,29 @@
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#define XP_ECC_CNT1_DESC_DED_WIDTH 8
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#define XP_ECC_CNT1_DESC_SEC_INDEX 0
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#define XP_ECC_CNT1_DESC_SEC_WIDTH 8
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#define XP_ECC_IER_DESC_DED_INDEX 0
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#define XP_ECC_IER_DESC_DED_INDEX 5
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#define XP_ECC_IER_DESC_DED_WIDTH 1
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#define XP_ECC_IER_DESC_SEC_INDEX 1
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#define XP_ECC_IER_DESC_SEC_INDEX 4
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#define XP_ECC_IER_DESC_SEC_WIDTH 1
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#define XP_ECC_IER_RX_DED_INDEX 2
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#define XP_ECC_IER_RX_DED_INDEX 3
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#define XP_ECC_IER_RX_DED_WIDTH 1
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#define XP_ECC_IER_RX_SEC_INDEX 3
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#define XP_ECC_IER_RX_SEC_INDEX 2
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#define XP_ECC_IER_RX_SEC_WIDTH 1
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#define XP_ECC_IER_TX_DED_INDEX 4
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#define XP_ECC_IER_TX_DED_INDEX 1
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#define XP_ECC_IER_TX_DED_WIDTH 1
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#define XP_ECC_IER_TX_SEC_INDEX 5
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#define XP_ECC_IER_TX_SEC_INDEX 0
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#define XP_ECC_IER_TX_SEC_WIDTH 1
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#define XP_ECC_ISR_DESC_DED_INDEX 0
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#define XP_ECC_ISR_DESC_DED_INDEX 5
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#define XP_ECC_ISR_DESC_DED_WIDTH 1
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#define XP_ECC_ISR_DESC_SEC_INDEX 1
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#define XP_ECC_ISR_DESC_SEC_INDEX 4
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#define XP_ECC_ISR_DESC_SEC_WIDTH 1
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#define XP_ECC_ISR_RX_DED_INDEX 2
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#define XP_ECC_ISR_RX_DED_INDEX 3
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#define XP_ECC_ISR_RX_DED_WIDTH 1
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#define XP_ECC_ISR_RX_SEC_INDEX 3
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#define XP_ECC_ISR_RX_SEC_INDEX 2
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#define XP_ECC_ISR_RX_SEC_WIDTH 1
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#define XP_ECC_ISR_TX_DED_INDEX 4
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#define XP_ECC_ISR_TX_DED_INDEX 1
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#define XP_ECC_ISR_TX_DED_WIDTH 1
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#define XP_ECC_ISR_TX_SEC_INDEX 5
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#define XP_ECC_ISR_TX_SEC_INDEX 0
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#define XP_ECC_ISR_TX_SEC_WIDTH 1
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#define XP_I2C_MUTEX_BUSY_INDEX 31
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#define XP_I2C_MUTEX_BUSY_WIDTH 1
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