sh: remove old CMT driver
This patch removes the old CMT driver (CONFIG_SH_CMT/timer-cmt.c) As replacement, select the sh_cmt driver with CONFIG_SH_TIMER_CMT and configure timer channel using platform data. If multiple CMT channels are enabled using platform data, use the earlytimer parameter on the kernel command line to select channel. For instance, use "earlytimer=sh_cmt.0" to select the first channel. To verify which timer is being used, look at printouts or the timer irq count in /proc/interrupts. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Magnus Damm
Paul Mundt
parent
698aa99da5
commit
f425752fc6
5 changed files with 6 additions and 206 deletions
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@ -462,22 +462,14 @@ config SH_TMU
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help
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This enables the use of the TMU as the system timer.
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config SH_CMT
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bool "CMT timer support"
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depends on SYS_SUPPORTS_CMT && CPU_SH2
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default y
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help
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This enables the use of the CMT as the system timer.
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#
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# Support for the new-style CMT driver. This will replace SH_CMT
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# once its other dependencies are merged.
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#
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config SH_TIMER_CMT
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bool "CMT clockevents driver"
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depends on SYS_SUPPORTS_CMT && !SH_CMT
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bool "CMT timer driver"
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depends on SYS_SUPPORTS_CMT
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default y
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select GENERIC_CLOCKEVENTS
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select GENERIC_TIME
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help
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This enables build of the CMT timer driver.
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config SH_MTU2
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bool "MTU2 timer support"
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@ -23,7 +23,7 @@ struct sys_timer {
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#define TICK_SIZE (tick_nsec / 1000)
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extern struct sys_timer tmu_timer, cmt_timer, mtu2_timer;
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extern struct sys_timer tmu_timer, mtu2_timer;
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extern struct sys_timer *sys_timer;
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#ifndef CONFIG_GENERIC_TIME
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@ -6,6 +6,5 @@ obj-y := timer.o
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obj-$(CONFIG_SH_TMU) += timer-tmu.o
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obj-$(CONFIG_SH_MTU2) += timer-mtu2.o
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obj-$(CONFIG_SH_CMT) += timer-cmt.o
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obj-$(CONFIG_GENERIC_CLOCKEVENTS_BROADCAST) += timer-broadcast.o
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@ -1,188 +0,0 @@
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/*
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* arch/sh/kernel/timers/timer-cmt.c - CMT Timer Support
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*
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* Copyright (C) 2005 Yoshinori Sato
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/interrupt.h>
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#include <linux/seqlock.h>
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#include <asm/timer.h>
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#include <asm/rtc.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/clock.h>
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#if defined(CONFIG_CPU_SUBTYPE_SH7619)
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#define CMT_CMSTR 0xf84a0070
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#define CMT_CMCSR_0 0xf84a0072
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#define CMT_CMCNT_0 0xf84a0074
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#define CMT_CMCOR_0 0xf84a0076
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#define CMT_CMCSR_1 0xf84a0078
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#define CMT_CMCNT_1 0xf84a007a
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#define CMT_CMCOR_1 0xf84a007c
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#define STBCR3 0xf80a0000
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#define cmt_clock_enable() do { ctrl_outb(ctrl_inb(STBCR3) & ~0x10, STBCR3); } while(0)
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#define CMT_CMCSR_INIT 0x0040
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#define CMT_CMCSR_CALIB 0x0000
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#elif defined(CONFIG_CPU_SUBTYPE_SH7203) || \
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defined(CONFIG_CPU_SUBTYPE_SH7206) || \
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defined(CONFIG_CPU_SUBTYPE_SH7263)
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#define CMT_CMSTR 0xfffec000
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#define CMT_CMCSR_0 0xfffec002
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#define CMT_CMCNT_0 0xfffec004
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#define CMT_CMCOR_0 0xfffec006
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#define STBCR4 0xfffe040c
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#define cmt_clock_enable() do { ctrl_outb(ctrl_inb(STBCR4) & ~0x04, STBCR4); } while(0)
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#define CMT_CMCSR_INIT 0x0040
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#define CMT_CMCSR_CALIB 0x0000
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#else
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#error "Unknown CPU SUBTYPE"
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#endif
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static unsigned long cmt_timer_get_offset(void)
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{
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int count;
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static unsigned short count_p = 0xffff; /* for the first call after boot */
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static unsigned long jiffies_p = 0;
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/*
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* cache volatile jiffies temporarily; we have IRQs turned off.
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*/
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unsigned long jiffies_t;
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/* timer count may underflow right here */
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count = ctrl_inw(CMT_CMCOR_0);
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count -= ctrl_inw(CMT_CMCNT_0);
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jiffies_t = jiffies;
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/*
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* avoiding timer inconsistencies (they are rare, but they happen)...
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* there is one kind of problem that must be avoided here:
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* 1. the timer counter underflows
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*/
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if (jiffies_t == jiffies_p) {
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if (count > count_p) {
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/* the nutcase */
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if (ctrl_inw(CMT_CMCSR_0) & 0x80) { /* Check CMF bit */
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count -= LATCH;
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} else {
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printk("%s (): hardware timer problem?\n",
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__func__);
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}
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}
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} else
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jiffies_p = jiffies_t;
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count_p = count;
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count = ((LATCH-1) - count) * TICK_SIZE;
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count = (count + LATCH/2) / LATCH;
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return count;
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}
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static irqreturn_t cmt_timer_interrupt(int irq, void *dev_id)
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{
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unsigned long timer_status;
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/* Clear CMF bit */
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timer_status = ctrl_inw(CMT_CMCSR_0);
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timer_status &= ~0x80;
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ctrl_outw(timer_status, CMT_CMCSR_0);
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handle_timer_tick();
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return IRQ_HANDLED;
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}
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static struct irqaction cmt_irq = {
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.name = "timer",
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.handler = cmt_timer_interrupt,
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.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
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};
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static void cmt_clk_init(struct clk *clk)
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{
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u8 divisor = CMT_CMCSR_INIT & 0x3;
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ctrl_inw(CMT_CMCSR_0);
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ctrl_outw(CMT_CMCSR_INIT, CMT_CMCSR_0);
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clk->parent = clk_get(NULL, "module_clk");
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clk->rate = clk->parent->rate / (8 << (divisor << 1));
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}
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static void cmt_clk_recalc(struct clk *clk)
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{
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u8 divisor = ctrl_inw(CMT_CMCSR_0) & 0x3;
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clk->rate = clk->parent->rate / (8 << (divisor << 1));
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}
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static struct clk_ops cmt_clk_ops = {
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.init = cmt_clk_init,
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.recalc = cmt_clk_recalc,
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};
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static struct clk cmt0_clk = {
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.name = "cmt0_clk",
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.ops = &cmt_clk_ops,
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};
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static int cmt_timer_start(void)
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{
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ctrl_outw(ctrl_inw(CMT_CMSTR) | 0x01, CMT_CMSTR);
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return 0;
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}
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static int cmt_timer_stop(void)
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{
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ctrl_outw(ctrl_inw(CMT_CMSTR) & ~0x01, CMT_CMSTR);
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return 0;
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}
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static int cmt_timer_init(void)
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{
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unsigned long interval;
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cmt_clock_enable();
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setup_irq(CONFIG_SH_TIMER_IRQ, &cmt_irq);
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cmt0_clk.parent = clk_get(NULL, "module_clk");
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cmt_timer_stop();
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interval = cmt0_clk.parent->rate / 8 / HZ;
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printk(KERN_INFO "Interval = %ld\n", interval);
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ctrl_outw(interval, CMT_CMCOR_0);
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clk_register(&cmt0_clk);
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clk_enable(&cmt0_clk);
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cmt_timer_start();
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return 0;
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}
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static struct sys_timer_ops cmt_timer_ops = {
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.init = cmt_timer_init,
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.start = cmt_timer_start,
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.stop = cmt_timer_stop,
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#ifndef CONFIG_GENERIC_TIME
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.get_offset = cmt_timer_get_offset,
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#endif
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};
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struct sys_timer cmt_timer = {
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.name = "cmt",
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.ops = &cmt_timer_ops,
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};
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@ -19,9 +19,6 @@ static struct sys_timer *sys_timers[] = {
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#endif
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#ifdef CONFIG_SH_MTU2
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&mtu2_timer,
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#endif
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#ifdef CONFIG_SH_CMT
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&cmt_timer,
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#endif
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NULL,
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};
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