clk: Add support to vote to regulator framework from clk framework
Add vdd_class support which would help vote/unvote for any voltage rail for the clock frequency to the regulator framework. A clock client request for a clock frequency would look for the corresponding voltage vote and would be send the request to regulator framework. Change-Id: I5b1229091fcb7b3887b54735b9663fd31a35db21 Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Taniya Das <tdas@codeaurora.org> Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org> Signed-off-by: David Dai <daidavid1@codeaurora.org>
This commit is contained in:
Stephen Boyd
David Dai
parent
8ff1a590c2
commit
f349485712
10 changed files with 370 additions and 14 deletions
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@ -219,7 +219,7 @@ struct clk_hw *clk_hw_register_composite(struct device *dev, const char *name,
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unsigned long flags)
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{
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struct clk_hw *hw;
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struct clk_init_data init;
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struct clk_init_data init = {};
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struct clk_composite *composite;
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struct clk_ops *clk_composite_ops;
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int ret;
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@ -458,7 +458,7 @@ static struct clk_hw *_register_divider(struct device *dev, const char *name,
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{
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struct clk_divider *div;
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struct clk_hw *hw;
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struct clk_init_data init;
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struct clk_init_data init = {};
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int ret;
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if (clk_divider_flags & CLK_DIVIDER_HIWORD_MASK) {
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@ -74,7 +74,7 @@ struct clk_hw *clk_hw_register_fixed_factor(struct device *dev,
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unsigned int mult, unsigned int div)
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{
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struct clk_fixed_factor *fix;
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struct clk_init_data init;
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struct clk_init_data init = {};
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struct clk_hw *hw;
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int ret;
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@ -61,7 +61,7 @@ struct clk_hw *clk_hw_register_fixed_rate_with_accuracy(struct device *dev,
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{
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struct clk_fixed_rate *fixed;
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struct clk_hw *hw;
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struct clk_init_data init;
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struct clk_init_data init = {};
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int ret;
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/* allocate fixed-rate clock */
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@ -134,7 +134,7 @@ struct clk_hw *clk_hw_register_fractional_divider(struct device *dev,
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u8 clk_divider_flags, spinlock_t *lock)
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{
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struct clk_fractional_divider *fd;
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struct clk_init_data init;
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struct clk_init_data init = {};
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struct clk_hw *hw;
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int ret;
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@ -128,7 +128,7 @@ struct clk_hw *clk_hw_register_gate(struct device *dev, const char *name,
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{
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struct clk_gate *gate;
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struct clk_hw *hw;
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struct clk_init_data init;
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struct clk_init_data init = {};
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int ret;
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if (clk_gate_flags & CLK_GATE_HIWORD_MASK) {
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@ -140,7 +140,7 @@ struct clk_hw *clk_hw_register_mux_table(struct device *dev, const char *name,
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{
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struct clk_mux *mux;
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struct clk_hw *hw;
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struct clk_init_data init;
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struct clk_init_data init = {};
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u8 width = 0;
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int ret;
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@ -56,7 +56,7 @@ static const struct clk_ops clk_pwm_ops = {
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static int clk_pwm_probe(struct platform_device *pdev)
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{
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struct device_node *node = pdev->dev.of_node;
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struct clk_init_data init;
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struct clk_init_data init = {};
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struct clk_pwm *clk_pwm;
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struct pwm_device *pwm;
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struct pwm_args pargs;
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@ -1,6 +1,7 @@
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/*
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* Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>
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* Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
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* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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@ -24,6 +25,7 @@
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#include <linux/pm_runtime.h>
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#include <linux/sched.h>
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#include <linux/clkdev.h>
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#include <linux/regulator/consumer.h>
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#include "clk.h"
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@ -40,6 +42,13 @@ static HLIST_HEAD(clk_root_list);
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static HLIST_HEAD(clk_orphan_list);
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static LIST_HEAD(clk_notifier_list);
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struct clk_handoff_vdd {
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struct list_head list;
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struct clk_vdd_class *vdd_class;
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};
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static LIST_HEAD(clk_handoff_vdd_list);
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/*** private data structures ***/
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struct clk_core {
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@ -77,6 +86,9 @@ struct clk_core {
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struct hlist_node debug_node;
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#endif
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struct kref ref;
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struct clk_vdd_class *vdd_class;
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unsigned long *rate_max;
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int num_rate_max;
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};
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#define CREATE_TRACE_POINTS
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@ -560,6 +572,225 @@ int __clk_mux_determine_rate_closest(struct clk_hw *hw,
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}
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EXPORT_SYMBOL_GPL(__clk_mux_determine_rate_closest);
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/*
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* Find the voltage level required for a given clock rate.
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*/
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static int clk_find_vdd_level(struct clk_core *clk, unsigned long rate)
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{
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int level;
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/*
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* For certain PLLs, due to the limitation in the bits allocated for
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* programming the fractional divider, the actual rate of the PLL will
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* be slightly higher than the requested rate (in the order of several
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* Hz). To accommodate this difference, convert the FMAX rate and the
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* clock frequency to KHz and use that for deriving the voltage level.
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*/
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for (level = 0; level < clk->num_rate_max; level++)
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if (DIV_ROUND_CLOSEST(rate, 1000) <=
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DIV_ROUND_CLOSEST(clk->rate_max[level], 1000))
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break;
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if (level == clk->num_rate_max) {
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pr_err("Rate %lu for %s is greater than highest Fmax\n", rate,
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clk->name);
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return -EINVAL;
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}
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return level;
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}
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/*
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* Update voltage level given the current votes.
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*/
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static int clk_update_vdd(struct clk_vdd_class *vdd_class)
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{
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int level, rc = 0, i, ignore;
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struct regulator **r = vdd_class->regulator;
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int *uv = vdd_class->vdd_uv;
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int n_reg = vdd_class->num_regulators;
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int cur_lvl = vdd_class->cur_level;
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int max_lvl = vdd_class->num_levels - 1;
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int cur_base = cur_lvl * n_reg;
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int new_base;
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/* aggregate votes */
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for (level = max_lvl; level > 0; level--)
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if (vdd_class->level_votes[level])
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break;
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if (level == cur_lvl)
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return 0;
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max_lvl = max_lvl * n_reg;
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new_base = level * n_reg;
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for (i = 0; i < vdd_class->num_regulators; i++) {
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pr_debug("Set Voltage level Min %d, Max %d\n", uv[new_base + i],
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uv[max_lvl + i]);
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rc = regulator_set_voltage(r[i], uv[new_base + i],
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vdd_class->use_max_uV ? INT_MAX : uv[max_lvl + i]);
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if (rc)
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goto set_voltage_fail;
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if (cur_lvl == 0 || cur_lvl == vdd_class->num_levels)
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rc = regulator_enable(r[i]);
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else if (level == 0)
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rc = regulator_disable(r[i]);
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if (rc)
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goto enable_disable_fail;
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}
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if (vdd_class->set_vdd && !vdd_class->num_regulators)
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rc = vdd_class->set_vdd(vdd_class, level);
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if (!rc)
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vdd_class->cur_level = level;
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return rc;
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enable_disable_fail:
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regulator_set_voltage(r[i], uv[cur_base + i],
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vdd_class->use_max_uV ? INT_MAX : uv[max_lvl + i]);
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set_voltage_fail:
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for (i--; i >= 0; i--) {
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regulator_set_voltage(r[i], uv[cur_base + i],
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vdd_class->use_max_uV ? INT_MAX : uv[max_lvl + i]);
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if (cur_lvl == 0 || cur_lvl == vdd_class->num_levels)
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regulator_disable(r[i]);
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else if (level == 0)
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ignore = regulator_enable(r[i]);
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}
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return rc;
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}
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/*
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* Vote for a voltage level.
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*/
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static int clk_vote_vdd_level(struct clk_vdd_class *vdd_class, int level)
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{
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int rc = 0;
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if (level >= vdd_class->num_levels)
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return -EINVAL;
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mutex_lock(&vdd_class->lock);
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vdd_class->level_votes[level]++;
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rc = clk_update_vdd(vdd_class);
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if (rc)
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vdd_class->level_votes[level]--;
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mutex_unlock(&vdd_class->lock);
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return rc;
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}
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/*
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* Remove vote for a voltage level.
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*/
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static int clk_unvote_vdd_level(struct clk_vdd_class *vdd_class, int level)
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{
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int rc = 0;
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if (level >= vdd_class->num_levels)
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return -EINVAL;
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mutex_lock(&vdd_class->lock);
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if (WARN(!vdd_class->level_votes[level],
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"Reference counts are incorrect for %s level %d\n",
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vdd_class->class_name, level))
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goto out;
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vdd_class->level_votes[level]--;
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rc = clk_update_vdd(vdd_class);
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if (rc)
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vdd_class->level_votes[level]++;
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out:
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mutex_unlock(&vdd_class->lock);
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return rc;
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}
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/*
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* Vote for a voltage level corresponding to a clock's rate.
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*/
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static int clk_vote_rate_vdd(struct clk_core *core, unsigned long rate)
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{
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int level;
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if (!core->vdd_class)
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return 0;
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level = clk_find_vdd_level(core, rate);
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if (level < 0)
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return level;
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return clk_vote_vdd_level(core->vdd_class, level);
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}
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/*
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* Remove vote for a voltage level corresponding to a clock's rate.
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*/
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static void clk_unvote_rate_vdd(struct clk_core *core, unsigned long rate)
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{
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int level;
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if (!core->vdd_class)
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return;
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level = clk_find_vdd_level(core, rate);
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if (level < 0)
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return;
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clk_unvote_vdd_level(core->vdd_class, level);
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}
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static bool clk_is_rate_level_valid(struct clk_core *core, unsigned long rate)
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{
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int level;
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if (!core->vdd_class)
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return true;
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level = clk_find_vdd_level(core, rate);
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return level >= 0;
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}
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static int clk_vdd_class_init(struct clk_vdd_class *vdd)
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{
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struct clk_handoff_vdd *v;
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if (vdd->skip_handoff)
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return 0;
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list_for_each_entry(v, &clk_handoff_vdd_list, list) {
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if (v->vdd_class == vdd)
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return 0;
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}
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pr_debug("voting for vdd_class %s\n", vdd->class_name);
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if (clk_vote_vdd_level(vdd, vdd->num_levels - 1))
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pr_err("failed to vote for %s\n", vdd->class_name);
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v = kmalloc(sizeof(*v), GFP_KERNEL);
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if (!v)
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return -ENOMEM;
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v->vdd_class = vdd;
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list_add_tail(&v->list, &clk_handoff_vdd_list);
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return 0;
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}
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/*** clk api ***/
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static void clk_core_rate_unprotect(struct clk_core *core)
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@ -727,6 +958,9 @@ static void clk_core_unprepare(struct clk_core *core)
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clk_pm_runtime_put(core);
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trace_clk_unprepare_complete(core);
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clk_unvote_rate_vdd(core, core->rate);
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clk_core_unprepare(core->parent);
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}
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@ -777,13 +1011,21 @@ static int clk_core_prepare(struct clk_core *core)
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trace_clk_prepare(core);
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ret = clk_vote_rate_vdd(core, core->rate);
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if (ret) {
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clk_core_unprepare(core->parent);
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return ret;
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}
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if (core->ops->prepare)
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ret = core->ops->prepare(core->hw);
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trace_clk_prepare_complete(core);
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if (ret)
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if (ret) {
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clk_unvote_rate_vdd(core, core->rate);
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goto unprepare;
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}
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}
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core->prepare_count++;
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@ -1073,6 +1315,7 @@ __setup("clk_ignore_unused", clk_ignore_unused_setup);
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static int clk_disable_unused(void)
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{
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struct clk_core *core;
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struct clk_handoff_vdd *v, *v_temp;
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if (clk_ignore_unused) {
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pr_warn("clk: Not disabling unused clocks\n");
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@ -1093,6 +1336,13 @@ static int clk_disable_unused(void)
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hlist_for_each_entry(core, &clk_orphan_list, child_node)
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clk_unprepare_unused_subtree(core);
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list_for_each_entry_safe(v, v_temp, &clk_handoff_vdd_list, list) {
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clk_unvote_vdd_level(v->vdd_class,
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v->vdd_class->num_levels - 1);
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list_del(&v->list);
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kfree(v);
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}
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clk_prepare_unlock();
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return 0;
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@ -1724,11 +1974,20 @@ static struct clk_core *clk_calc_new_rates(struct clk_core *core,
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}
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}
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/*
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* Certain PLLs only have 16 bits to program the fractional divider.
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* Hence the programmed rate might be slightly different than the
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* requested one.
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*/
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if ((core->flags & CLK_SET_RATE_PARENT) && parent &&
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best_parent_rate != parent->rate)
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(DIV_ROUND_CLOSEST(best_parent_rate, 1000) !=
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DIV_ROUND_CLOSEST(parent->rate, 1000)))
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top = clk_calc_new_rates(parent, best_parent_rate);
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out:
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if (!clk_is_rate_level_valid(core, rate))
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return NULL;
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clk_calc_subtree(core, new_rate, parent, p_index);
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return top;
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@ -1811,6 +2070,15 @@ static int clk_change_rate(struct clk_core *core)
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clk_enable_unlock(flags);
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}
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trace_clk_set_rate(core, core->new_rate);
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/* Enforce vdd requirements for new frequency. */
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if (core->prepare_count) {
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rc = clk_vote_rate_vdd(core, core->new_rate);
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if (rc)
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goto out;
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}
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if (core->new_parent && core->new_parent != core->parent) {
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old_parent = __clk_set_parent_before(core, core->new_parent);
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trace_clk_set_parent(core, core->new_parent);
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@ -1831,19 +2099,21 @@ static int clk_change_rate(struct clk_core *core)
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if (core->flags & CLK_OPS_PARENT_ENABLE)
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clk_core_prepare_enable(parent);
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trace_clk_set_rate(core, core->new_rate);
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if (!skip_set_rate && core->ops->set_rate) {
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rc = core->ops->set_rate(core->hw, core->new_rate,
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best_parent_rate);
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if (rc) {
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trace_clk_set_rate_complete(core, core->new_rate);
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goto out;
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goto err_set_rate;
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}
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}
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trace_clk_set_rate_complete(core, core->new_rate);
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/* Release vdd requirements for old frequency. */
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if (core->prepare_count)
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clk_unvote_rate_vdd(core, old_rate);
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core->rate = clk_recalc(core, best_parent_rate);
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if (core->flags & CLK_SET_RATE_UNGATE) {
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@ -1874,13 +2144,19 @@ static int clk_change_rate(struct clk_core *core)
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continue;
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rc = clk_change_rate(child);
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if (rc)
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goto out;
|
||||
goto err_set_rate;
|
||||
}
|
||||
|
||||
/* handle the new child who might not be in core->children yet */
|
||||
if (core->new_child)
|
||||
rc = clk_change_rate(core->new_child);
|
||||
|
||||
clk_pm_runtime_put(core);
|
||||
return rc;
|
||||
|
||||
err_set_rate:
|
||||
if (core->prepare_count)
|
||||
clk_unvote_rate_vdd(core, core->new_rate);
|
||||
out:
|
||||
clk_pm_runtime_put(core);
|
||||
return rc;
|
||||
|
|
@ -3236,8 +3512,19 @@ struct clk *clk_register(struct device *dev, struct clk_hw *hw)
|
|||
core->num_parents = hw->init->num_parents;
|
||||
core->min_rate = 0;
|
||||
core->max_rate = ULONG_MAX;
|
||||
core->vdd_class = hw->init->vdd_class;
|
||||
core->rate_max = hw->init->rate_max;
|
||||
core->num_rate_max = hw->init->num_rate_max;
|
||||
hw->core = core;
|
||||
|
||||
if (core->vdd_class) {
|
||||
ret = clk_vdd_class_init(core->vdd_class);
|
||||
if (ret) {
|
||||
pr_err("Failed to initialize vdd class\n");
|
||||
goto fail_parent_names;
|
||||
}
|
||||
}
|
||||
|
||||
/* allocate local copy in case parent_names is __initdata */
|
||||
core->parent_names = kcalloc(core->num_parents, sizeof(char *),
|
||||
GFP_KERNEL);
|
||||
|
|
|
|||
|
|
@ -14,6 +14,7 @@
|
|||
#include <linux/io.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_clk.h>
|
||||
#include <linux/mutex.h>
|
||||
|
||||
#ifdef CONFIG_COMMON_CLK
|
||||
|
||||
|
|
@ -260,6 +261,9 @@ struct clk_ops {
|
|||
* @parent_names: array of string names for all possible parents
|
||||
* @num_parents: number of possible parents
|
||||
* @flags: framework-level hints and quirks
|
||||
* @vdd_class: voltage scaling requirement class
|
||||
* @rate_max: maximum clock rate in Hz supported at each voltage level
|
||||
* @num_rate_max: number of maximum voltage level supported
|
||||
*/
|
||||
struct clk_init_data {
|
||||
const char *name;
|
||||
|
|
@ -267,8 +271,73 @@ struct clk_init_data {
|
|||
const char * const *parent_names;
|
||||
u8 num_parents;
|
||||
unsigned long flags;
|
||||
struct clk_vdd_class *vdd_class;
|
||||
unsigned long *rate_max;
|
||||
int num_rate_max;
|
||||
};
|
||||
|
||||
struct regulator;
|
||||
|
||||
/**
|
||||
* struct clk_vdd_class - Voltage scaling class
|
||||
* @class_name: name of the class
|
||||
* @regulator: array of regulators
|
||||
* @num_regulators: size of regulator array. Standard regulator APIs will be
|
||||
used if this field > 0
|
||||
* @set_vdd: function to call when applying a new voltage setting
|
||||
* @vdd_uv: sorted 2D array of legal voltage settings. Indexed by level, then
|
||||
regulator
|
||||
* @level_votes: array of votes for each level
|
||||
* @num_levels: specifies the size of level_votes array
|
||||
* @skip_handoff: do not vote for the max possible voltage during init
|
||||
* @use_max_uV: use INT_MAX for max_uV when calling regulator_set_voltage
|
||||
* @cur_level: the currently set voltage level
|
||||
* @lock: lock to protect this struct
|
||||
*/
|
||||
struct clk_vdd_class {
|
||||
const char *class_name;
|
||||
struct regulator **regulator;
|
||||
int num_regulators;
|
||||
int (*set_vdd)(struct clk_vdd_class *v_class, int level);
|
||||
int *vdd_uv;
|
||||
int *level_votes;
|
||||
int num_levels;
|
||||
bool skip_handoff;
|
||||
bool use_max_uV;
|
||||
unsigned long cur_level;
|
||||
struct mutex lock;
|
||||
};
|
||||
|
||||
#define DEFINE_VDD_CLASS(_name, _set_vdd, _num_levels) \
|
||||
struct clk_vdd_class _name = { \
|
||||
.class_name = #_name, \
|
||||
.set_vdd = _set_vdd, \
|
||||
.level_votes = (int [_num_levels]) {}, \
|
||||
.num_levels = _num_levels, \
|
||||
.cur_level = _num_levels, \
|
||||
.lock = __MUTEX_INITIALIZER(_name.lock) \
|
||||
}
|
||||
|
||||
#define DEFINE_VDD_REGULATORS(_name, _num_levels, _num_regulators, _vdd_uv) \
|
||||
struct clk_vdd_class _name = { \
|
||||
.class_name = #_name, \
|
||||
.vdd_uv = _vdd_uv, \
|
||||
.regulator = (struct regulator * [_num_regulators]) {}, \
|
||||
.num_regulators = _num_regulators, \
|
||||
.level_votes = (int [_num_levels]) {}, \
|
||||
.num_levels = _num_levels, \
|
||||
.cur_level = _num_levels, \
|
||||
.lock = __MUTEX_INITIALIZER(_name.lock) \
|
||||
}
|
||||
|
||||
#define DEFINE_VDD_REGS_INIT(_name, _num_regulators) \
|
||||
struct clk_vdd_class _name = { \
|
||||
.class_name = #_name, \
|
||||
.regulator = (struct regulator * [_num_regulators]) {}, \
|
||||
.num_regulators = _num_regulators, \
|
||||
.lock = __MUTEX_INITIALIZER(_name.lock) \
|
||||
}
|
||||
|
||||
/**
|
||||
* struct clk_hw - handle for traversing from a struct clk to its corresponding
|
||||
* hardware-specific structure. struct clk_hw should be declared within struct
|
||||
|
|
|
|||
Loading…
Reference in a new issue