i2c: i2c-mpc: make I2C bus speed configurable
This patch makes the I2C bus speed configurable by using the I2C node
property "clock-frequency". If the property is not defined, the old
fixed clock settings will be used for backward comptibility.
The generic I2C clock properties, especially the CPU-specific source
clock pre-scaler are defined via the OF match table:
static const struct of_device_id mpc_i2c_of_match[] = {
...
{.compatible = "fsl,mpc8543-i2c",
.data = &(struct fsl_i2c_match_data) {
.setclock = mpc_i2c_setclock_8xxx,
.prescaler = 2,
},
},
The "data" field defines the relevant I2C setclock function and the
relevant pre-scaler for the I2C source clock frequency.
It uses arch-specific tables and functions to determine resonable
Freqency Divider Register (fdr) values for MPC83xx, MPC85xx, MPC86xx,
MPC5200 and MPC5200B.
The i2c->flags field and the corresponding FSL_I2C_DEV_* definitions
have been removed as they are obsolete.
Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
This commit is contained in:
Wolfgang Grandegger
Ben Dooks
parent
54377cd059
commit
f2bd5efe72
1 changed files with 242 additions and 20 deletions
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@ -26,6 +26,9 @@
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#include <linux/interrupt.h>
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#include <linux/delay.h>
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#include <asm/mpc52xx.h>
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#include <sysdev/fsl_soc.h>
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#define DRV_NAME "mpc-i2c"
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#define MPC_I2C_FDR 0x04
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@ -56,7 +59,18 @@ struct mpc_i2c {
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wait_queue_head_t queue;
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struct i2c_adapter adap;
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int irq;
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u32 flags;
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};
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struct mpc_i2c_divider {
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u16 divider;
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u16 fdr; /* including dfsrr */
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};
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struct mpc_i2c_match_data {
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void (*setclock)(struct device_node *node,
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struct mpc_i2c *i2c,
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u32 clock, u32 prescaler);
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u32 prescaler;
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};
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static inline void writeccr(struct mpc_i2c *i2c, u32 x)
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@ -150,18 +164,181 @@ static int i2c_wait(struct mpc_i2c *i2c, unsigned timeout, int writing)
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return 0;
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}
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static void mpc_i2c_setclock(struct mpc_i2c *i2c)
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#ifdef CONFIG_PPC_52xx
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static const struct mpc_i2c_divider mpc_i2c_dividers_52xx[] = {
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{20, 0x20}, {22, 0x21}, {24, 0x22}, {26, 0x23},
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{28, 0x24}, {30, 0x01}, {32, 0x25}, {34, 0x02},
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{36, 0x26}, {40, 0x27}, {44, 0x04}, {48, 0x28},
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{52, 0x63}, {56, 0x29}, {60, 0x41}, {64, 0x2a},
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{68, 0x07}, {72, 0x2b}, {80, 0x2c}, {88, 0x09},
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{96, 0x2d}, {104, 0x0a}, {112, 0x2e}, {120, 0x81},
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{128, 0x2f}, {136, 0x47}, {144, 0x0c}, {160, 0x30},
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{176, 0x49}, {192, 0x31}, {208, 0x4a}, {224, 0x32},
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{240, 0x0f}, {256, 0x33}, {272, 0x87}, {288, 0x10},
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{320, 0x34}, {352, 0x89}, {384, 0x35}, {416, 0x8a},
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{448, 0x36}, {480, 0x13}, {512, 0x37}, {576, 0x14},
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{640, 0x38}, {768, 0x39}, {896, 0x3a}, {960, 0x17},
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{1024, 0x3b}, {1152, 0x18}, {1280, 0x3c}, {1536, 0x3d},
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{1792, 0x3e}, {1920, 0x1b}, {2048, 0x3f}, {2304, 0x1c},
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{2560, 0x1d}, {3072, 0x1e}, {3584, 0x7e}, {3840, 0x1f},
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{4096, 0x7f}, {4608, 0x5c}, {5120, 0x5d}, {6144, 0x5e},
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{7168, 0xbe}, {7680, 0x5f}, {8192, 0xbf}, {9216, 0x9c},
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{10240, 0x9d}, {12288, 0x9e}, {15360, 0x9f}
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};
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int mpc_i2c_get_fdr_52xx(struct device_node *node, u32 clock, int prescaler)
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{
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/* Set clock and filters */
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if (i2c->flags & FSL_I2C_DEV_SEPARATE_DFSRR) {
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writeb(0x31, i2c->base + MPC_I2C_FDR);
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writeb(0x10, i2c->base + MPC_I2C_DFSRR);
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} else if (i2c->flags & FSL_I2C_DEV_CLOCK_5200)
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writeb(0x3f, i2c->base + MPC_I2C_FDR);
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else
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writel(0x1031, i2c->base + MPC_I2C_FDR);
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const struct mpc52xx_i2c_divider *div = NULL;
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unsigned int pvr = mfspr(SPRN_PVR);
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u32 divider;
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int i;
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if (!clock)
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return -EINVAL;
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/* Determine divider value */
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divider = mpc52xx_find_ipb_freq(node) / clock;
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/*
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* We want to choose an FDR/DFSR that generates an I2C bus speed that
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* is equal to or lower than the requested speed.
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*/
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for (i = 0; i < ARRAY_SIZE(mpc52xx_i2c_dividers); i++) {
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div = &mpc_i2c_dividers_52xx[i];
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/* Old MPC5200 rev A CPUs do not support the high bits */
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if (div->fdr & 0xc0 && pvr == 0x80822011)
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continue;
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if (div->divider >= divider)
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break;
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}
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return div ? (int)div->fdr : -EINVAL;
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}
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static void mpc_i2c_setclock_52xx(struct device_node *node,
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struct mpc_i2c *i2c,
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u32 clock, u32 prescaler)
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{
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int fdr = mpc52xx_i2c_get_fdr(node, clock, prescaler);
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if (fdr < 0)
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fdr = 0x3f; /* backward compatibility */
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writeb(fdr & 0xff, i2c->base + MPC_I2C_FDR);
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dev_info(i2c->dev, "clock %d Hz (fdr=%d)\n", clock, fdr);
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}
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#else /* !CONFIG_PPC_52xx */
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static void mpc_i2c_setclock_52xx(struct device_node *node,
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struct mpc_i2c *i2c,
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u32 clock, u32 prescaler)
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{
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}
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#endif /* CONFIG_PPC_52xx*/
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#ifdef CONFIG_FSL_SOC
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static const struct mpc_i2c_divider mpc_i2c_dividers_8xxx[] = {
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{160, 0x0120}, {192, 0x0121}, {224, 0x0122}, {256, 0x0123},
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{288, 0x0100}, {320, 0x0101}, {352, 0x0601}, {384, 0x0102},
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{416, 0x0602}, {448, 0x0126}, {480, 0x0103}, {512, 0x0127},
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{544, 0x0b03}, {576, 0x0104}, {608, 0x1603}, {640, 0x0105},
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{672, 0x2003}, {704, 0x0b05}, {736, 0x2b03}, {768, 0x0106},
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{800, 0x3603}, {832, 0x0b06}, {896, 0x012a}, {960, 0x0107},
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{1024, 0x012b}, {1088, 0x1607}, {1152, 0x0108}, {1216, 0x2b07},
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{1280, 0x0109}, {1408, 0x1609}, {1536, 0x010a}, {1664, 0x160a},
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{1792, 0x012e}, {1920, 0x010b}, {2048, 0x012f}, {2176, 0x2b0b},
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{2304, 0x010c}, {2560, 0x010d}, {2816, 0x2b0d}, {3072, 0x010e},
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{3328, 0x2b0e}, {3584, 0x0132}, {3840, 0x010f}, {4096, 0x0133},
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{4608, 0x0110}, {5120, 0x0111}, {6144, 0x0112}, {7168, 0x0136},
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{7680, 0x0113}, {8192, 0x0137}, {9216, 0x0114}, {10240, 0x0115},
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{12288, 0x0116}, {14336, 0x013a}, {15360, 0x0117}, {16384, 0x013b},
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{18432, 0x0118}, {20480, 0x0119}, {24576, 0x011a}, {28672, 0x013e},
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{30720, 0x011b}, {32768, 0x013f}, {36864, 0x011c}, {40960, 0x011d},
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{49152, 0x011e}, {61440, 0x011f}
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};
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u32 mpc_i2c_get_sec_cfg_8xxx(void)
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{
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struct device_node *node = NULL;
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u32 __iomem *reg;
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u32 val = 0;
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node = of_find_node_by_name(NULL, "global-utilities");
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if (node) {
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const u32 *prop = of_get_property(node, "reg", NULL);
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if (prop) {
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/*
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* Map and check POR Device Status Register 2
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* (PORDEVSR2) at 0xE0014
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*/
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reg = ioremap(get_immrbase() + *prop + 0x14, 0x4);
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if (!reg)
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printk(KERN_ERR
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"Error: couldn't map PORDEVSR2\n");
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else
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val = in_be32(reg) & 0x00000080; /* sec-cfg */
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iounmap(reg);
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}
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}
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if (node)
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of_node_put(node);
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return val;
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}
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int mpc_i2c_get_fdr_8xxx(struct device_node *node, u32 clock, u32 prescaler)
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{
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const struct mpc_i2c_divider *div = NULL;
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u32 divider;
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int i;
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if (!clock)
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return -EINVAL;
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/* Determine proper divider value */
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if (of_device_is_compatible(node, "fsl,mpc8544-i2c"))
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prescaler = mpc_i2c_get_sec_cfg_8xxx() ? 3 : 2;
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if (!prescaler)
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prescaler = 1;
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divider = fsl_get_sys_freq() / clock / prescaler;
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pr_debug("I2C: src_clock=%d clock=%d divider=%d\n",
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fsl_get_sys_freq(), clock, divider);
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/*
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* We want to choose an FDR/DFSR that generates an I2C bus speed that
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* is equal to or lower than the requested speed.
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*/
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for (i = 0; i < ARRAY_SIZE(mpc_i2c_dividers_8xxx); i++) {
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div = &mpc_i2c_dividers_8xxx[i];
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if (div->divider >= divider)
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break;
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}
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return div ? (int)div->fdr : -EINVAL;
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}
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static void mpc_i2c_setclock_8xxx(struct device_node *node,
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struct mpc_i2c *i2c,
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u32 clock, u32 prescaler)
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{
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int fdr = mpc_i2c_get_fdr_8xxx(node, clock, prescaler);
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if (fdr < 0)
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fdr = 0x1031; /* backward compatibility */
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writeb(fdr & 0xff, i2c->base + MPC_I2C_FDR);
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writeb((fdr >> 8) & 0xff, i2c->base + MPC_I2C_DFSRR);
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dev_info(i2c->dev, "clock %d Hz (dfsrr=%d fdr=%d)\n",
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clock, fdr >> 8, fdr & 0xff);
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}
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#else /* !CONFIG_FSL_SOC */
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static void mpc_i2c_setclock_8xxx(struct device_node *node,
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struct mpc_i2c *i2c,
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u32 clock, u32 prescaler)
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{
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}
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#endif /* CONFIG_FSL_SOC */
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static void mpc_i2c_start(struct mpc_i2c *i2c)
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{
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/* Clear arbitration */
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@ -315,8 +492,11 @@ static struct i2c_adapter mpc_ops = {
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static int __devinit fsl_i2c_probe(struct of_device *op,
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const struct of_device_id *match)
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{
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int result = 0;
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struct mpc_i2c *i2c;
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const u32 *prop;
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u32 clock = 0;
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int result = 0;
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int plen;
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i2c = kzalloc(sizeof(*i2c), GFP_KERNEL);
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if (!i2c)
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@ -324,13 +504,6 @@ static int __devinit fsl_i2c_probe(struct of_device *op,
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i2c->dev = &op->dev; /* for debug and error output */
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if (of_get_property(op->node, "dfsrr", NULL))
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i2c->flags |= FSL_I2C_DEV_SEPARATE_DFSRR;
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if (of_device_is_compatible(op->node, "fsl,mpc5200-i2c") ||
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of_device_is_compatible(op->node, "mpc5200-i2c"))
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i2c->flags |= FSL_I2C_DEV_CLOCK_5200;
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init_waitqueue_head(&i2c->queue);
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i2c->base = of_iomap(op->node, 0);
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@ -350,7 +523,22 @@ static int __devinit fsl_i2c_probe(struct of_device *op,
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}
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}
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mpc_i2c_setclock(i2c);
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if (!of_get_property(op->node, "fsl,preserve-clocking", NULL)) {
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prop = of_get_property(op->node, "clock-frequency", &plen);
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if (prop && plen == sizeof(u32))
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clock = *prop;
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if (match->data) {
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struct mpc_i2c_match_data *data =
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(struct mpc_i2c_match_data *)match->data;
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data->setclock(op->node, i2c, clock, data->prescaler);
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} else {
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/* Backwards compatibility */
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if (of_get_property(op->node, "dfsrr", NULL))
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mpc_i2c_setclock_8xxx(op->node, i2c,
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clock, 0);
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}
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}
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dev_set_drvdata(&op->dev, i2c);
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@ -395,9 +583,43 @@ static int __devexit fsl_i2c_remove(struct of_device *op)
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};
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static const struct of_device_id mpc_i2c_of_match[] = {
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{.compatible = "fsl-i2c",},
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{.compatible = "mpc5200-i2c",
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.data = &(struct mpc_i2c_match_data) {
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.setclock = mpc_i2c_setclock_52xx,
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},
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},
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{.compatible = "fsl,mpc5200b-i2c",
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.data = &(struct mpc_i2c_match_data) {
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.setclock = mpc_i2c_setclock_52xx,
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},
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},
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{.compatible = "fsl,mpc5200-i2c",
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.data = &(struct mpc_i2c_match_data) {
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.setclock = mpc_i2c_setclock_52xx,
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},
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},
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{.compatible = "fsl,mpc8313-i2c",
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.data = &(struct mpc_i2c_match_data) {
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.setclock = mpc_i2c_setclock_8xxx,
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},
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},
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{.compatible = "fsl,mpc8543-i2c",
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.data = &(struct mpc_i2c_match_data) {
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.setclock = mpc_i2c_setclock_8xxx,
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.prescaler = 2,
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},
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},
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{.compatible = "fsl,mpc8544-i2c",
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.data = &(struct mpc_i2c_match_data) {
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.setclock = mpc_i2c_setclock_8xxx,
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.prescaler = 3,
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},
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/* Backward compatibility */
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},
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{.compatible = "fsl-i2c", },
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{},
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};
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MODULE_DEVICE_TABLE(of, mpc_i2c_of_match);
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