phy: for 4.16
*) Fix in exynos5-usbdrd to enumerate SuperSpeed devices on Odroid XU3
*) Fix in Broadcom USB PHY to get Dell Low Speed keyboards working
*) Fix in Broadcom USB PHY to power down the PHY when XHCI disabled
to save power
*) Fix in Broadcom USB PHY to prevent abort in DRD mode
*) Fix in Broadcom USB PHY to use the correct dt properties
*) Fix in Mediatek PHY to detect device connection
*) Make getting resource optional for Mediatek V1 TPHY
*) Cleanup in Mediatek PHY
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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Merge tag 'phy-for-4.16' of git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy into usb-next
Kishon writes:
phy: for 4.16
*) Fix in exynos5-usbdrd to enumerate SuperSpeed devices on Odroid XU3
*) Fix in Broadcom USB PHY to get Dell Low Speed keyboards working
*) Fix in Broadcom USB PHY to power down the PHY when XHCI disabled
to save power
*) Fix in Broadcom USB PHY to prevent abort in DRD mode
*) Fix in Broadcom USB PHY to use the correct dt properties
*) Fix in Mediatek PHY to detect device connection
*) Make getting resource optional for Mediatek V1 TPHY
*) Cleanup in Mediatek PHY
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
This commit is contained in:
Greg Kroah-Hartman
commit
f1faf88c13
5 changed files with 212 additions and 34 deletions
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@ -50,6 +50,8 @@
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#define USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK 0x80000000 /* option */
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#define USB_CTRL_EBRIDGE 0x0c
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#define USB_CTRL_EBRIDGE_ESTOP_SCB_REQ_MASK 0x00020000 /* option */
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#define USB_CTRL_OBRIDGE 0x10
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#define USB_CTRL_OBRIDGE_LS_KEEP_ALIVE_MASK 0x08000000
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#define USB_CTRL_MDIO 0x14
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#define USB_CTRL_MDIO2 0x18
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#define USB_CTRL_UTMI_CTL_1 0x2c
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@ -71,6 +73,7 @@
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#define USB_CTRL_USB30_CTL1_USB3_IPP_MASK 0x20000000 /* option */
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#define USB_CTRL_USB30_PCTL 0x70
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#define USB_CTRL_USB30_PCTL_PHY3_SOFT_RESETB_MASK 0x00000002
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#define USB_CTRL_USB30_PCTL_PHY3_IDDQ_OVERRIDE_MASK 0x00008000
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#define USB_CTRL_USB30_PCTL_PHY3_SOFT_RESETB_P1_MASK 0x00020000
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#define USB_CTRL_USB_DEVICE_CTL1 0x90
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#define USB_CTRL_USB_DEVICE_CTL1_PORT_MODE_MASK 0x00000003 /* option */
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@ -116,7 +119,6 @@ enum {
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USB_CTRL_SETUP_STRAP_IPP_SEL_SELECTOR,
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USB_CTRL_SETUP_OC3_DISABLE_SELECTOR,
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USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_SELECTOR,
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USB_CTRL_EBRIDGE_ESTOP_SCB_REQ_SELECTOR,
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USB_CTRL_USB_PM_BDC_SOFT_RESETB_SELECTOR,
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USB_CTRL_USB_PM_XHC_SOFT_RESETB_SELECTOR,
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USB_CTRL_USB_PM_USB_PWRDN_SELECTOR,
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@ -203,7 +205,6 @@ usb_reg_bits_map_table[BRCM_FAMILY_COUNT][USB_CTRL_SELECTOR_COUNT] = {
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USB_CTRL_SETUP_STRAP_IPP_SEL_MASK,
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USB_CTRL_SETUP_OC3_DISABLE_MASK,
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0, /* USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK */
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USB_CTRL_EBRIDGE_ESTOP_SCB_REQ_MASK,
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0, /* USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK */
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USB_CTRL_USB_PM_XHC_SOFT_RESETB_MASK,
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USB_CTRL_USB_PM_USB_PWRDN_MASK,
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@ -225,7 +226,6 @@ usb_reg_bits_map_table[BRCM_FAMILY_COUNT][USB_CTRL_SELECTOR_COUNT] = {
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0, /* USB_CTRL_SETUP_STRAP_IPP_SEL_MASK */
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USB_CTRL_SETUP_OC3_DISABLE_MASK,
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USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK,
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USB_CTRL_EBRIDGE_ESTOP_SCB_REQ_MASK,
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0, /* USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK */
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USB_CTRL_USB_PM_XHC_SOFT_RESETB_VAR_MASK,
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0, /* USB_CTRL_USB_PM_USB_PWRDN_MASK */
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@ -247,7 +247,6 @@ usb_reg_bits_map_table[BRCM_FAMILY_COUNT][USB_CTRL_SELECTOR_COUNT] = {
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USB_CTRL_SETUP_STRAP_IPP_SEL_MASK,
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USB_CTRL_SETUP_OC3_DISABLE_MASK,
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0, /* USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK */
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USB_CTRL_EBRIDGE_ESTOP_SCB_REQ_MASK,
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USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK,
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USB_CTRL_USB_PM_XHC_SOFT_RESETB_MASK,
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USB_CTRL_USB_PM_USB_PWRDN_MASK,
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@ -269,7 +268,6 @@ usb_reg_bits_map_table[BRCM_FAMILY_COUNT][USB_CTRL_SELECTOR_COUNT] = {
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0, /* USB_CTRL_SETUP_STRAP_IPP_SEL_MASK */
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USB_CTRL_SETUP_OC3_DISABLE_MASK,
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USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK,
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USB_CTRL_EBRIDGE_ESTOP_SCB_REQ_MASK,
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0, /* USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK */
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USB_CTRL_USB_PM_XHC_SOFT_RESETB_VAR_MASK,
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0, /* USB_CTRL_USB_PM_USB_PWRDN_MASK */
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@ -291,7 +289,6 @@ usb_reg_bits_map_table[BRCM_FAMILY_COUNT][USB_CTRL_SELECTOR_COUNT] = {
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0, /* USB_CTRL_SETUP_STRAP_IPP_SEL_MASK */
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USB_CTRL_SETUP_OC3_DISABLE_MASK,
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0, /* USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK */
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USB_CTRL_EBRIDGE_ESTOP_SCB_REQ_MASK,
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0, /* USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK */
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USB_CTRL_USB_PM_XHC_SOFT_RESETB_VAR_MASK,
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USB_CTRL_USB_PM_USB_PWRDN_MASK,
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@ -313,7 +310,6 @@ usb_reg_bits_map_table[BRCM_FAMILY_COUNT][USB_CTRL_SELECTOR_COUNT] = {
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0, /* USB_CTRL_SETUP_STRAP_IPP_SEL_MASK */
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0, /* USB_CTRL_SETUP_OC3_DISABLE_MASK */
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USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK,
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0, /* USB_CTRL_EBRIDGE_ESTOP_SCB_REQ_MASK */
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0, /* USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK */
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0, /* USB_CTRL_USB_PM_XHC_SOFT_RESETB_MASK */
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0, /* USB_CTRL_USB_PM_USB_PWRDN_MASK */
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@ -335,7 +331,6 @@ usb_reg_bits_map_table[BRCM_FAMILY_COUNT][USB_CTRL_SELECTOR_COUNT] = {
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USB_CTRL_SETUP_STRAP_IPP_SEL_MASK,
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USB_CTRL_SETUP_OC3_DISABLE_MASK,
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0, /* USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK */
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0, /* USB_CTRL_EBRIDGE_ESTOP_SCB_REQ_MASK */
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USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK,
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USB_CTRL_USB_PM_XHC_SOFT_RESETB_MASK,
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USB_CTRL_USB_PM_USB_PWRDN_MASK,
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@ -357,7 +352,6 @@ usb_reg_bits_map_table[BRCM_FAMILY_COUNT][USB_CTRL_SELECTOR_COUNT] = {
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0, /* USB_CTRL_SETUP_STRAP_IPP_SEL_MASK */
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USB_CTRL_SETUP_OC3_DISABLE_MASK,
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USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK,
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0, /* USB_CTRL_EBRIDGE_ESTOP_SCB_REQ_MASK */
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0, /* USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK */
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0, /* USB_CTRL_USB_PM_XHC_SOFT_RESETB_MASK */
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0, /* USB_CTRL_USB_PM_USB_PWRDN_MASK */
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@ -379,7 +373,6 @@ usb_reg_bits_map_table[BRCM_FAMILY_COUNT][USB_CTRL_SELECTOR_COUNT] = {
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USB_CTRL_SETUP_STRAP_IPP_SEL_MASK,
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USB_CTRL_SETUP_OC3_DISABLE_MASK,
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0, /* USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK */
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USB_CTRL_EBRIDGE_ESTOP_SCB_REQ_MASK,
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USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK,
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USB_CTRL_USB_PM_XHC_SOFT_RESETB_MASK,
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USB_CTRL_USB_PM_USB_PWRDN_MASK,
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@ -401,7 +394,6 @@ usb_reg_bits_map_table[BRCM_FAMILY_COUNT][USB_CTRL_SELECTOR_COUNT] = {
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USB_CTRL_SETUP_STRAP_IPP_SEL_MASK,
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USB_CTRL_SETUP_OC3_DISABLE_MASK,
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0, /* USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK */
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USB_CTRL_EBRIDGE_ESTOP_SCB_REQ_MASK,
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USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK,
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USB_CTRL_USB_PM_XHC_SOFT_RESETB_MASK,
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USB_CTRL_USB_PM_USB_PWRDN_MASK,
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@ -926,6 +918,7 @@ void brcm_usb_init_common(struct brcm_usb_init_params *params)
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USB_CTRL_UNSET_FAMILY(params, USB_PM, BDC_SOFT_RESETB);
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break;
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default:
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USB_CTRL_UNSET_FAMILY(params, USB_PM, BDC_SOFT_RESETB);
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USB_CTRL_SET_FAMILY(params, USB_PM, BDC_SOFT_RESETB);
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break;
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}
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@ -952,13 +945,17 @@ void brcm_usb_init_eohci(struct brcm_usb_init_params *params)
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* Don't enable this so the memory controller doesn't read
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* into memory holes. NOTE: This bit is low true on 7366C0.
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*/
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USB_CTRL_SET_FAMILY(params, EBRIDGE, ESTOP_SCB_REQ);
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USB_CTRL_SET(ctrl, EBRIDGE, ESTOP_SCB_REQ);
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/* Setup the endian bits */
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reg = brcmusb_readl(USB_CTRL_REG(ctrl, SETUP));
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reg &= ~USB_CTRL_SETUP_ENDIAN_BITS;
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reg |= USB_CTRL_MASK_FAMILY(params, SETUP, ENDIAN);
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brcmusb_writel(reg, USB_CTRL_REG(ctrl, SETUP));
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if (params->selected_family == BRCM_FAMILY_7271A0)
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/* Enable LS keep alive fix for certain keyboards */
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USB_CTRL_SET(ctrl, OBRIDGE, LS_KEEP_ALIVE);
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}
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void brcm_usb_init_xhci(struct brcm_usb_init_params *params)
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@ -1003,6 +1000,7 @@ void brcm_usb_uninit_eohci(struct brcm_usb_init_params *params)
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void brcm_usb_uninit_xhci(struct brcm_usb_init_params *params)
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{
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brcmusb_xhci_soft_reset(params, 1);
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USB_CTRL_SET(params->ctrl_regs, USB30_PCTL, PHY3_IDDQ_OVERRIDE);
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}
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void brcm_usb_set_family_map(struct brcm_usb_init_params *params)
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@ -338,9 +338,9 @@ static int brcm_usb_phy_probe(struct platform_device *pdev)
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ARRAY_SIZE(brcm_dr_mode_to_name),
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mode, &priv->ini.mode);
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}
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if (of_property_read_bool(dn, "brcm,has_xhci"))
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if (of_property_read_bool(dn, "brcm,has-xhci"))
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priv->has_xhci = true;
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if (of_property_read_bool(dn, "brcm,has_eohci"))
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if (of_property_read_bool(dn, "brcm,has-eohci"))
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priv->has_eohci = true;
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err = brcm_usb_phy_dvr_init(dev, priv, dn);
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@ -20,6 +20,7 @@
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#include <linux/iopoll.h>
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#include <linux/module.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/phy/phy.h>
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#include <linux/platform_device.h>
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@ -440,9 +441,9 @@ static void u2_phy_instance_init(struct mtk_tphy *tphy,
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u32 index = instance->index;
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u32 tmp;
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/* switch to USB function. (system register, force ip into usb mode) */
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/* switch to USB function, and enable usb pll */
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tmp = readl(com + U3P_U2PHYDTM0);
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tmp &= ~P2C_FORCE_UART_EN;
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tmp &= ~(P2C_FORCE_UART_EN | P2C_FORCE_SUSPENDM);
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tmp |= P2C_RG_XCVRSEL_VAL(1) | P2C_RG_DATAIN_VAL(0);
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writel(tmp, com + U3P_U2PHYDTM0);
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@ -502,10 +503,8 @@ static void u2_phy_instance_power_on(struct mtk_tphy *tphy,
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u32 index = instance->index;
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u32 tmp;
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/* (force_suspendm=0) (let suspendm=1, enable usb 480MHz pll) */
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tmp = readl(com + U3P_U2PHYDTM0);
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tmp &= ~(P2C_FORCE_SUSPENDM | P2C_RG_XCVRSEL);
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tmp &= ~(P2C_RG_DATAIN | P2C_DTM0_PART_MASK);
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tmp &= ~(P2C_RG_XCVRSEL | P2C_RG_DATAIN | P2C_DTM0_PART_MASK);
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writel(tmp, com + U3P_U2PHYDTM0);
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/* OTG Enable */
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@ -540,7 +539,6 @@ static void u2_phy_instance_power_off(struct mtk_tphy *tphy,
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tmp = readl(com + U3P_U2PHYDTM0);
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tmp &= ~(P2C_RG_XCVRSEL | P2C_RG_DATAIN);
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tmp |= P2C_FORCE_SUSPENDM;
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writel(tmp, com + U3P_U2PHYDTM0);
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/* OTG Disable */
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@ -548,18 +546,16 @@ static void u2_phy_instance_power_off(struct mtk_tphy *tphy,
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tmp &= ~PA6_RG_U2_OTG_VBUSCMP_EN;
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writel(tmp, com + U3P_USBPHYACR6);
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/* let suspendm=0, set utmi into analog power down */
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tmp = readl(com + U3P_U2PHYDTM0);
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tmp &= ~P2C_RG_SUSPENDM;
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writel(tmp, com + U3P_U2PHYDTM0);
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udelay(1);
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tmp = readl(com + U3P_U2PHYDTM1);
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tmp &= ~(P2C_RG_VBUSVALID | P2C_RG_AVALID);
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tmp |= P2C_RG_SESSEND;
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writel(tmp, com + U3P_U2PHYDTM1);
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if (tphy->pdata->avoid_rx_sen_degradation && index) {
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tmp = readl(com + U3P_U2PHYDTM0);
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tmp &= ~(P2C_RG_SUSPENDM | P2C_FORCE_SUSPENDM);
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writel(tmp, com + U3P_U2PHYDTM0);
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tmp = readl(com + U3D_U2PHYDCR0);
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tmp &= ~P2C_RG_SIF_U2PLL_FORCE_ON;
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writel(tmp, com + U3D_U2PHYDCR0);
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@ -1000,7 +996,6 @@ MODULE_DEVICE_TABLE(of, mtk_tphy_id_table);
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static int mtk_tphy_probe(struct platform_device *pdev)
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{
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const struct of_device_id *match;
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struct device *dev = &pdev->dev;
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struct device_node *np = dev->of_node;
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struct device_node *child_np;
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@ -1010,15 +1005,14 @@ static int mtk_tphy_probe(struct platform_device *pdev)
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struct resource res;
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int port, retval;
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match = of_match_node(mtk_tphy_id_table, pdev->dev.of_node);
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if (!match)
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return -EINVAL;
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tphy = devm_kzalloc(dev, sizeof(*tphy), GFP_KERNEL);
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if (!tphy)
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return -ENOMEM;
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tphy->pdata = match->data;
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tphy->pdata = of_device_get_match_data(dev);
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if (!tphy->pdata)
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return -EINVAL;
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tphy->nphys = of_get_child_count(np);
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tphy->phys = devm_kcalloc(dev, tphy->nphys,
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sizeof(*tphy->phys), GFP_KERNEL);
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@ -1028,9 +1022,10 @@ static int mtk_tphy_probe(struct platform_device *pdev)
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tphy->dev = dev;
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platform_set_drvdata(pdev, tphy);
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if (tphy->pdata->version == MTK_PHY_V1) {
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sif_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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/* SATA phy of V1 needn't it if not shared with PCIe or USB */
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if (sif_res && tphy->pdata->version == MTK_PHY_V1) {
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/* get banks shared by multiple phys */
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sif_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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tphy->sif_base = devm_ioremap_resource(dev, sif_res);
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if (IS_ERR(tphy->sif_base)) {
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dev_err(dev, "failed to remap sif regs\n");
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|
|
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@ -90,7 +90,17 @@
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#define PHYCLKRST_COMMONONN BIT(0)
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#define EXYNOS5_DRD_PHYREG0 0x14
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#define PHYREG0_SSC_REF_CLK_SEL BIT(21)
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#define PHYREG0_SSC_RANGE BIT(20)
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#define PHYREG0_CR_WRITE BIT(19)
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#define PHYREG0_CR_READ BIT(18)
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#define PHYREG0_CR_DATA_IN(_x) ((_x) << 2)
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#define PHYREG0_CR_CAP_DATA BIT(1)
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#define PHYREG0_CR_CAP_ADDR BIT(0)
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#define EXYNOS5_DRD_PHYREG1 0x18
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#define PHYREG1_CR_DATA_OUT(_x) ((_x) << 1)
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#define PHYREG1_CR_ACK BIT(0)
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||||
#define EXYNOS5_DRD_PHYPARAM0 0x1c
|
||||
|
||||
|
|
@ -119,6 +129,25 @@
|
|||
#define EXYNOS5_DRD_PHYRESUME 0x34
|
||||
#define EXYNOS5_DRD_LINKPORT 0x44
|
||||
|
||||
/* USB 3.0 DRD PHY SS Function Control Reg; accessed by CR_PORT */
|
||||
#define EXYNOS5_DRD_PHYSS_LOSLEVEL_OVRD_IN (0x15)
|
||||
#define LOSLEVEL_OVRD_IN_LOS_BIAS_5420 (0x5 << 13)
|
||||
#define LOSLEVEL_OVRD_IN_LOS_BIAS_DEFAULT (0x0 << 13)
|
||||
#define LOSLEVEL_OVRD_IN_EN (0x1 << 10)
|
||||
#define LOSLEVEL_OVRD_IN_LOS_LEVEL_DEFAULT (0x9 << 0)
|
||||
|
||||
#define EXYNOS5_DRD_PHYSS_TX_VBOOSTLEVEL_OVRD_IN (0x12)
|
||||
#define TX_VBOOSTLEVEL_OVRD_IN_VBOOST_5420 (0x5 << 13)
|
||||
#define TX_VBOOSTLEVEL_OVRD_IN_VBOOST_DEFAULT (0x4 << 13)
|
||||
|
||||
#define EXYNOS5_DRD_PHYSS_LANE0_TX_DEBUG (0x1010)
|
||||
#define LANE0_TX_DEBUG_RXDET_MEAS_TIME_19M2_20M (0x4 << 4)
|
||||
#define LANE0_TX_DEBUG_RXDET_MEAS_TIME_24M (0x8 << 4)
|
||||
#define LANE0_TX_DEBUG_RXDET_MEAS_TIME_25M_26M (0x8 << 4)
|
||||
#define LANE0_TX_DEBUG_RXDET_MEAS_TIME_48M_50M_52M (0x20 << 4)
|
||||
#define LANE0_TX_DEBUG_RXDET_MEAS_TIME_62M5 (0x20 << 4)
|
||||
#define LANE0_TX_DEBUG_RXDET_MEAS_TIME_96M_100M (0x40 << 4)
|
||||
|
||||
#define KHZ 1000
|
||||
#define MHZ (KHZ * KHZ)
|
||||
|
||||
|
|
@ -527,6 +556,151 @@ static int exynos5_usbdrd_phy_power_off(struct phy *phy)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int crport_handshake(struct exynos5_usbdrd_phy *phy_drd,
|
||||
u32 val, u32 cmd)
|
||||
{
|
||||
u32 usec = 100;
|
||||
unsigned int result;
|
||||
|
||||
writel(val | cmd, phy_drd->reg_phy + EXYNOS5_DRD_PHYREG0);
|
||||
|
||||
do {
|
||||
result = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYREG1);
|
||||
if (result & PHYREG1_CR_ACK)
|
||||
break;
|
||||
|
||||
udelay(1);
|
||||
} while (usec-- > 0);
|
||||
|
||||
if (!usec) {
|
||||
dev_err(phy_drd->dev,
|
||||
"CRPORT handshake timeout1 (0x%08x)\n", val);
|
||||
return -ETIME;
|
||||
}
|
||||
|
||||
usec = 100;
|
||||
|
||||
writel(val, phy_drd->reg_phy + EXYNOS5_DRD_PHYREG0);
|
||||
|
||||
do {
|
||||
result = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYREG1);
|
||||
if (!(result & PHYREG1_CR_ACK))
|
||||
break;
|
||||
|
||||
udelay(1);
|
||||
} while (usec-- > 0);
|
||||
|
||||
if (!usec) {
|
||||
dev_err(phy_drd->dev,
|
||||
"CRPORT handshake timeout2 (0x%08x)\n", val);
|
||||
return -ETIME;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int crport_ctrl_write(struct exynos5_usbdrd_phy *phy_drd,
|
||||
u32 addr, u32 data)
|
||||
{
|
||||
int ret;
|
||||
|
||||
/* Write Address */
|
||||
writel(PHYREG0_CR_DATA_IN(addr),
|
||||
phy_drd->reg_phy + EXYNOS5_DRD_PHYREG0);
|
||||
ret = crport_handshake(phy_drd, PHYREG0_CR_DATA_IN(addr),
|
||||
PHYREG0_CR_CAP_ADDR);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* Write Data */
|
||||
writel(PHYREG0_CR_DATA_IN(data),
|
||||
phy_drd->reg_phy + EXYNOS5_DRD_PHYREG0);
|
||||
ret = crport_handshake(phy_drd, PHYREG0_CR_DATA_IN(data),
|
||||
PHYREG0_CR_CAP_DATA);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = crport_handshake(phy_drd, PHYREG0_CR_DATA_IN(data),
|
||||
PHYREG0_CR_WRITE);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*
|
||||
* Calibrate few PHY parameters using CR_PORT register to meet
|
||||
* SuperSpeed requirements on Exynos5420 and Exynos5800 systems,
|
||||
* which have 28nm USB 3.0 DRD PHY.
|
||||
*/
|
||||
static int exynos5420_usbdrd_phy_calibrate(struct exynos5_usbdrd_phy *phy_drd)
|
||||
{
|
||||
unsigned int temp;
|
||||
int ret = 0;
|
||||
|
||||
/*
|
||||
* Change los_bias to (0x5) for 28nm PHY from a
|
||||
* default value (0x0); los_level is set as default
|
||||
* (0x9) as also reflected in los_level[30:26] bits
|
||||
* of PHYPARAM0 register.
|
||||
*/
|
||||
temp = LOSLEVEL_OVRD_IN_LOS_BIAS_5420 |
|
||||
LOSLEVEL_OVRD_IN_EN |
|
||||
LOSLEVEL_OVRD_IN_LOS_LEVEL_DEFAULT;
|
||||
ret = crport_ctrl_write(phy_drd,
|
||||
EXYNOS5_DRD_PHYSS_LOSLEVEL_OVRD_IN,
|
||||
temp);
|
||||
if (ret) {
|
||||
dev_err(phy_drd->dev,
|
||||
"Failed setting Loss-of-Signal level for SuperSpeed\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*
|
||||
* Set tx_vboost_lvl to (0x5) for 28nm PHY Tuning,
|
||||
* to raise Tx signal level from its default value of (0x4)
|
||||
*/
|
||||
temp = TX_VBOOSTLEVEL_OVRD_IN_VBOOST_5420;
|
||||
ret = crport_ctrl_write(phy_drd,
|
||||
EXYNOS5_DRD_PHYSS_TX_VBOOSTLEVEL_OVRD_IN,
|
||||
temp);
|
||||
if (ret) {
|
||||
dev_err(phy_drd->dev,
|
||||
"Failed setting Tx-Vboost-Level for SuperSpeed\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*
|
||||
* Set proper time to wait for RxDetect measurement, for
|
||||
* desired reference clock of PHY, by tuning the CR_PORT
|
||||
* register LANE0.TX_DEBUG which is internal to PHY.
|
||||
* This fixes issue with few USB 3.0 devices, which are
|
||||
* not detected (not even generate interrupts on the bus
|
||||
* on insertion) without this change.
|
||||
* e.g. Samsung SUM-TSB16S 3.0 USB drive.
|
||||
*/
|
||||
switch (phy_drd->extrefclk) {
|
||||
case EXYNOS5_FSEL_50MHZ:
|
||||
temp = LANE0_TX_DEBUG_RXDET_MEAS_TIME_48M_50M_52M;
|
||||
break;
|
||||
case EXYNOS5_FSEL_20MHZ:
|
||||
case EXYNOS5_FSEL_19MHZ2:
|
||||
temp = LANE0_TX_DEBUG_RXDET_MEAS_TIME_19M2_20M;
|
||||
break;
|
||||
case EXYNOS5_FSEL_24MHZ:
|
||||
default:
|
||||
temp = LANE0_TX_DEBUG_RXDET_MEAS_TIME_24M;
|
||||
break;
|
||||
}
|
||||
|
||||
ret = crport_ctrl_write(phy_drd,
|
||||
EXYNOS5_DRD_PHYSS_LANE0_TX_DEBUG,
|
||||
temp);
|
||||
if (ret)
|
||||
dev_err(phy_drd->dev,
|
||||
"Fail to set RxDet measurement time for SuperSpeed\n");
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static struct phy *exynos5_usbdrd_phy_xlate(struct device *dev,
|
||||
struct of_phandle_args *args)
|
||||
{
|
||||
|
|
@ -538,11 +712,20 @@ static struct phy *exynos5_usbdrd_phy_xlate(struct device *dev,
|
|||
return phy_drd->phys[args->args[0]].phy;
|
||||
}
|
||||
|
||||
static int exynos5_usbdrd_phy_calibrate(struct phy *phy)
|
||||
{
|
||||
struct phy_usb_instance *inst = phy_get_drvdata(phy);
|
||||
struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);
|
||||
|
||||
return exynos5420_usbdrd_phy_calibrate(phy_drd);
|
||||
}
|
||||
|
||||
static const struct phy_ops exynos5_usbdrd_phy_ops = {
|
||||
.init = exynos5_usbdrd_phy_init,
|
||||
.exit = exynos5_usbdrd_phy_exit,
|
||||
.power_on = exynos5_usbdrd_phy_power_on,
|
||||
.power_off = exynos5_usbdrd_phy_power_off,
|
||||
.calibrate = exynos5_usbdrd_phy_calibrate,
|
||||
.owner = THIS_MODULE,
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -147,6 +147,7 @@ static void __dwc3_set_mode(struct work_struct *work)
|
|||
otg_set_vbus(dwc->usb2_phy->otg, true);
|
||||
phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
|
||||
phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
|
||||
phy_calibrate(dwc->usb2_generic_phy);
|
||||
}
|
||||
break;
|
||||
case DWC3_GCTL_PRTCAP_DEVICE:
|
||||
|
|
@ -945,6 +946,7 @@ static int dwc3_core_init_mode(struct dwc3 *dwc)
|
|||
dev_err(dev, "failed to initialize host\n");
|
||||
return ret;
|
||||
}
|
||||
phy_calibrate(dwc->usb2_generic_phy);
|
||||
break;
|
||||
case USB_DR_MODE_OTG:
|
||||
INIT_WORK(&dwc->drd_work, __dwc3_set_mode);
|
||||
|
|
|
|||
Loading…
Reference in a new issue