Merge branch 'x86-apic-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull x86/apic changes from Ingo Molnar: "Most of the changes are about helping virtualized guest kernels achieve better performance." Fix up trivial conflicts with the iommu updates to arch/x86/kernel/apic/io_apic.c * 'x86-apic-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: x86/apic: Implement EIO micro-optimization x86/apic: Add apic->eoi_write() callback x86/apic: Use symbolic APIC_EOI_ACK x86/apic: Fix typo EIO_ACK -> EOI_ACK and document it x86/xen/apic: Add missing #include <xen/xen.h> x86/apic: Only compile local function if used with !CONFIG_GENERIC_PENDING_IRQ x86/apic: Fix UP boot crash x86: Conditionally update time when ack-ing pending irqs xen/apic: implement io apic read with hypercall Revert "xen/x86: Workaround 'x86/ioapic: Add register level checks to detect bogus io-apic entries'" xen/x86: Implement x86_apic_ops x86/apic: Replace io_apic_ops with x86_io_apic_ops.
This commit is contained in:
Linus Torvalds
commit
f08b9c2f8a
25 changed files with 151 additions and 93 deletions
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@ -138,6 +138,11 @@ static inline void native_apic_msr_write(u32 reg, u32 v)
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wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0);
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}
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static inline void native_apic_msr_eoi_write(u32 reg, u32 v)
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{
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wrmsr(APIC_BASE_MSR + (APIC_EOI >> 4), APIC_EOI_ACK, 0);
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}
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static inline u32 native_apic_msr_read(u32 reg)
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{
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u64 msr;
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@ -351,6 +356,14 @@ struct apic {
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/* apic ops */
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u32 (*read)(u32 reg);
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void (*write)(u32 reg, u32 v);
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/*
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* ->eoi_write() has the same signature as ->write().
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*
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* Drivers can support both ->eoi_write() and ->write() by passing the same
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* callback value. Kernel can override ->eoi_write() and fall back
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* on write for EOI.
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*/
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void (*eoi_write)(u32 reg, u32 v);
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u64 (*icr_read)(void);
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void (*icr_write)(u32 low, u32 high);
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void (*wait_icr_idle)(void);
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@ -426,6 +439,11 @@ static inline void apic_write(u32 reg, u32 val)
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apic->write(reg, val);
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}
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static inline void apic_eoi(void)
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{
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apic->eoi_write(APIC_EOI, APIC_EOI_ACK);
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}
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static inline u64 apic_icr_read(void)
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{
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return apic->icr_read();
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@ -450,6 +468,7 @@ static inline u32 safe_apic_wait_icr_idle(void)
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static inline u32 apic_read(u32 reg) { return 0; }
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static inline void apic_write(u32 reg, u32 val) { }
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static inline void apic_eoi(void) { }
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static inline u64 apic_icr_read(void) { return 0; }
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static inline void apic_icr_write(u32 low, u32 high) { }
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static inline void apic_wait_icr_idle(void) { }
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@ -463,9 +482,7 @@ static inline void ack_APIC_irq(void)
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* ack_APIC_irq() actually gets compiled as a single instruction
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* ... yummie.
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*/
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/* Docs say use 0 for future compatibility */
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apic_write(APIC_EOI, 0);
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apic_eoi();
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}
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static inline unsigned default_get_apic_id(unsigned long x)
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@ -37,7 +37,7 @@
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#define APIC_ARBPRI_MASK 0xFFu
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#define APIC_PROCPRI 0xA0
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#define APIC_EOI 0xB0
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#define APIC_EIO_ACK 0x0
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#define APIC_EOI_ACK 0x0 /* Docs say 0 for future compat. */
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#define APIC_RRR 0xC0
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#define APIC_LDR 0xD0
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#define APIC_LDR_MASK (0xFFu << 24)
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@ -5,7 +5,7 @@
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#include <asm/mpspec.h>
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#include <asm/apicdef.h>
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#include <asm/irq_vectors.h>
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#include <asm/x86_init.h>
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/*
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* Intel IO-APIC support for SMP and UP systems.
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*
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@ -21,15 +21,6 @@
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#define IO_APIC_REDIR_LEVEL_TRIGGER (1 << 15)
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#define IO_APIC_REDIR_MASKED (1 << 16)
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struct io_apic_ops {
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void (*init) (void);
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unsigned int (*read) (unsigned int apic, unsigned int reg);
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void (*write) (unsigned int apic, unsigned int reg, unsigned int value);
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void (*modify)(unsigned int apic, unsigned int reg, unsigned int value);
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};
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void __init set_io_apic_ops(const struct io_apic_ops *);
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/*
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* The structure of the IO-APIC:
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*/
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@ -156,7 +147,6 @@ struct io_apic_irq_attr;
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extern int io_apic_set_pci_routing(struct device *dev, int irq,
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struct io_apic_irq_attr *irq_attr);
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void setup_IO_APIC_irq_extra(u32 gsi);
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extern void ioapic_and_gsi_init(void);
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extern void ioapic_insert_resources(void);
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int io_apic_setup_irq_pin_once(unsigned int irq, int node, struct io_apic_irq_attr *attr);
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@ -185,12 +175,29 @@ extern void mp_save_irq(struct mpc_intsrc *m);
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extern void disable_ioapic_support(void);
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extern void __init native_io_apic_init_mappings(void);
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extern unsigned int native_io_apic_read(unsigned int apic, unsigned int reg);
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extern void native_io_apic_write(unsigned int apic, unsigned int reg, unsigned int val);
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extern void native_io_apic_modify(unsigned int apic, unsigned int reg, unsigned int val);
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static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
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{
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return x86_io_apic_ops.read(apic, reg);
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}
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static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
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{
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x86_io_apic_ops.write(apic, reg, value);
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}
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static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
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{
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x86_io_apic_ops.modify(apic, reg, value);
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}
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#else /* !CONFIG_X86_IO_APIC */
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#define io_apic_assign_pci_irqs 0
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#define setup_ioapic_ids_from_mpc x86_init_noop
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static const int timer_through_8259 = 0;
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static inline void ioapic_and_gsi_init(void) { }
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static inline void ioapic_insert_resources(void) { }
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#define gsi_top (NR_IRQS_LEGACY)
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static inline int mp_find_ioapic(u32 gsi) { return 0; }
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@ -212,6 +219,10 @@ static inline int restore_ioapic_entries(void)
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static inline void mp_save_irq(struct mpc_intsrc *m) { };
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static inline void disable_ioapic_support(void) { }
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#define native_io_apic_init_mappings NULL
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#define native_io_apic_read NULL
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#define native_io_apic_write NULL
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#define native_io_apic_modify NULL
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#endif
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#endif /* _ASM_X86_IO_APIC_H */
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@ -188,11 +188,18 @@ struct x86_msi_ops {
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void (*restore_msi_irqs)(struct pci_dev *dev, int irq);
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};
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struct x86_io_apic_ops {
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void (*init) (void);
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unsigned int (*read) (unsigned int apic, unsigned int reg);
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void (*write) (unsigned int apic, unsigned int reg, unsigned int value);
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void (*modify)(unsigned int apic, unsigned int reg, unsigned int value);
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};
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extern struct x86_init_ops x86_init;
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extern struct x86_cpuinit_ops x86_cpuinit;
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extern struct x86_platform_ops x86_platform;
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extern struct x86_msi_ops x86_msi;
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extern struct x86_io_apic_ops x86_io_apic_ops;
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extern void x86_init_noop(void);
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extern void x86_init_uint_noop(unsigned int unused);
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@ -1326,11 +1326,13 @@ void __cpuinit setup_local_APIC(void)
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acked);
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break;
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}
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if (queued) {
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if (cpu_has_tsc) {
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rdtscll(ntsc);
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max_loops = (cpu_khz << 10) - (ntsc - tsc);
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} else
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max_loops--;
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}
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} while (queued && max_loops > 0);
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WARN_ON(max_loops <= 0);
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@ -227,6 +227,7 @@ static struct apic apic_flat = {
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.read = native_apic_mem_read,
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.write = native_apic_mem_write,
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.eoi_write = native_apic_mem_write,
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.icr_read = native_apic_icr_read,
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.icr_write = native_apic_icr_write,
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.wait_icr_idle = native_apic_wait_icr_idle,
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@ -386,6 +387,7 @@ static struct apic apic_physflat = {
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.read = native_apic_mem_read,
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.write = native_apic_mem_write,
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.eoi_write = native_apic_mem_write,
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.icr_read = native_apic_icr_read,
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.icr_write = native_apic_icr_write,
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.wait_icr_idle = native_apic_wait_icr_idle,
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@ -181,6 +181,7 @@ struct apic apic_noop = {
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.read = noop_apic_read,
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.write = noop_apic_write,
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.eoi_write = noop_apic_write,
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.icr_read = noop_apic_icr_read,
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.icr_write = noop_apic_icr_write,
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.wait_icr_idle = noop_apic_wait_icr_idle,
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@ -295,6 +295,7 @@ static struct apic apic_numachip __refconst = {
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.read = native_apic_mem_read,
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.write = native_apic_mem_write,
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.eoi_write = native_apic_mem_write,
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.icr_read = native_apic_icr_read,
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.icr_write = native_apic_icr_write,
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.wait_icr_idle = native_apic_wait_icr_idle,
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@ -248,6 +248,7 @@ static struct apic apic_bigsmp = {
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.read = native_apic_mem_read,
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.write = native_apic_mem_write,
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.eoi_write = native_apic_mem_write,
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.icr_read = native_apic_icr_read,
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.icr_write = native_apic_icr_write,
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.wait_icr_idle = native_apic_wait_icr_idle,
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@ -678,6 +678,7 @@ static struct apic __refdata apic_es7000_cluster = {
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.read = native_apic_mem_read,
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.write = native_apic_mem_write,
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.eoi_write = native_apic_mem_write,
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.icr_read = native_apic_icr_read,
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.icr_write = native_apic_icr_write,
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.wait_icr_idle = native_apic_wait_icr_idle,
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@ -742,6 +743,7 @@ static struct apic __refdata apic_es7000 = {
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.read = native_apic_mem_read,
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.write = native_apic_mem_write,
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.eoi_write = native_apic_mem_write,
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.icr_read = native_apic_icr_read,
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.icr_write = native_apic_icr_write,
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.wait_icr_idle = native_apic_wait_icr_idle,
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@ -68,24 +68,6 @@
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#define for_each_irq_pin(entry, head) \
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for (entry = head; entry; entry = entry->next)
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static void __init __ioapic_init_mappings(void);
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static unsigned int __io_apic_read (unsigned int apic, unsigned int reg);
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static void __io_apic_write (unsigned int apic, unsigned int reg, unsigned int val);
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static void __io_apic_modify(unsigned int apic, unsigned int reg, unsigned int val);
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static struct io_apic_ops io_apic_ops = {
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.init = __ioapic_init_mappings,
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.read = __io_apic_read,
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.write = __io_apic_write,
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.modify = __io_apic_modify,
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};
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void __init set_io_apic_ops(const struct io_apic_ops *ops)
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{
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io_apic_ops = *ops;
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}
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#ifdef CONFIG_IRQ_REMAP
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static void irq_remap_modify_chip_defaults(struct irq_chip *chip);
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static inline bool irq_remapped(struct irq_cfg *cfg)
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@ -329,21 +311,6 @@ static void free_irq_at(unsigned int at, struct irq_cfg *cfg)
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irq_free_desc(at);
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}
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static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
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{
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return io_apic_ops.read(apic, reg);
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}
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static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
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{
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io_apic_ops.write(apic, reg, value);
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}
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static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
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{
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io_apic_ops.modify(apic, reg, value);
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}
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struct io_apic {
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unsigned int index;
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@ -365,14 +332,14 @@ static inline void io_apic_eoi(unsigned int apic, unsigned int vector)
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writel(vector, &io_apic->eoi);
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}
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static unsigned int __io_apic_read(unsigned int apic, unsigned int reg)
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unsigned int native_io_apic_read(unsigned int apic, unsigned int reg)
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{
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struct io_apic __iomem *io_apic = io_apic_base(apic);
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writel(reg, &io_apic->index);
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return readl(&io_apic->data);
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}
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static void __io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
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void native_io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
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{
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struct io_apic __iomem *io_apic = io_apic_base(apic);
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@ -386,7 +353,7 @@ static void __io_apic_write(unsigned int apic, unsigned int reg, unsigned int va
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*
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* Older SiS APIC requires we rewrite the index register
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*/
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static void __io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
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void native_io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
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{
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struct io_apic __iomem *io_apic = io_apic_base(apic);
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@ -395,29 +362,6 @@ static void __io_apic_modify(unsigned int apic, unsigned int reg, unsigned int v
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writel(value, &io_apic->data);
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}
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static bool io_apic_level_ack_pending(struct irq_cfg *cfg)
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{
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struct irq_pin_list *entry;
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unsigned long flags;
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raw_spin_lock_irqsave(&ioapic_lock, flags);
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for_each_irq_pin(entry, cfg->irq_2_pin) {
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unsigned int reg;
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int pin;
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pin = entry->pin;
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reg = io_apic_read(entry->apic, 0x10 + pin*2);
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/* Is the remote IRR bit set? */
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if (reg & IO_APIC_REDIR_REMOTE_IRR) {
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raw_spin_unlock_irqrestore(&ioapic_lock, flags);
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return true;
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}
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}
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raw_spin_unlock_irqrestore(&ioapic_lock, flags);
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return false;
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}
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union entry_union {
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struct { u32 w1, w2; };
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struct IO_APIC_route_entry entry;
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@ -2439,6 +2383,29 @@ static void ack_apic_edge(struct irq_data *data)
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atomic_t irq_mis_count;
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#ifdef CONFIG_GENERIC_PENDING_IRQ
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static bool io_apic_level_ack_pending(struct irq_cfg *cfg)
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{
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struct irq_pin_list *entry;
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unsigned long flags;
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raw_spin_lock_irqsave(&ioapic_lock, flags);
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for_each_irq_pin(entry, cfg->irq_2_pin) {
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unsigned int reg;
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int pin;
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pin = entry->pin;
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reg = io_apic_read(entry->apic, 0x10 + pin*2);
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/* Is the remote IRR bit set? */
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if (reg & IO_APIC_REDIR_REMOTE_IRR) {
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raw_spin_unlock_irqrestore(&ioapic_lock, flags);
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return true;
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}
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}
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raw_spin_unlock_irqrestore(&ioapic_lock, flags);
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return false;
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}
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static inline bool ioapic_irqd_mask(struct irq_data *data, struct irq_cfg *cfg)
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{
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/* If we are moving the irq we need to mask it */
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@ -3756,12 +3723,7 @@ static struct resource * __init ioapic_setup_resources(int nr_ioapics)
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return res;
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}
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void __init ioapic_and_gsi_init(void)
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{
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io_apic_ops.init();
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}
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static void __init __ioapic_init_mappings(void)
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void __init native_io_apic_init_mappings(void)
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{
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unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
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struct resource *ioapic_res;
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@ -530,6 +530,7 @@ static struct apic __refdata apic_numaq = {
|
|||
|
||||
.read = native_apic_mem_read,
|
||||
.write = native_apic_mem_write,
|
||||
.eoi_write = native_apic_mem_write,
|
||||
.icr_read = native_apic_icr_read,
|
||||
.icr_write = native_apic_icr_write,
|
||||
.wait_icr_idle = native_apic_wait_icr_idle,
|
||||
|
|
|
|||
|
|
@ -142,6 +142,7 @@ static struct apic apic_default = {
|
|||
|
||||
.read = native_apic_mem_read,
|
||||
.write = native_apic_mem_write,
|
||||
.eoi_write = native_apic_mem_write,
|
||||
.icr_read = native_apic_icr_read,
|
||||
.icr_write = native_apic_icr_write,
|
||||
.wait_icr_idle = native_apic_wait_icr_idle,
|
||||
|
|
|
|||
|
|
@ -546,6 +546,7 @@ static struct apic apic_summit = {
|
|||
|
||||
.read = native_apic_mem_read,
|
||||
.write = native_apic_mem_write,
|
||||
.eoi_write = native_apic_mem_write,
|
||||
.icr_read = native_apic_icr_read,
|
||||
.icr_write = native_apic_icr_write,
|
||||
.wait_icr_idle = native_apic_wait_icr_idle,
|
||||
|
|
|
|||
|
|
@ -260,6 +260,7 @@ static struct apic apic_x2apic_cluster = {
|
|||
|
||||
.read = native_apic_msr_read,
|
||||
.write = native_apic_msr_write,
|
||||
.eoi_write = native_apic_msr_eoi_write,
|
||||
.icr_read = native_x2apic_icr_read,
|
||||
.icr_write = native_x2apic_icr_write,
|
||||
.wait_icr_idle = native_x2apic_wait_icr_idle,
|
||||
|
|
|
|||
|
|
@ -172,6 +172,7 @@ static struct apic apic_x2apic_phys = {
|
|||
|
||||
.read = native_apic_msr_read,
|
||||
.write = native_apic_msr_write,
|
||||
.eoi_write = native_apic_msr_eoi_write,
|
||||
.icr_read = native_x2apic_icr_read,
|
||||
.icr_write = native_x2apic_icr_write,
|
||||
.wait_icr_idle = native_x2apic_wait_icr_idle,
|
||||
|
|
|
|||
|
|
@ -404,6 +404,7 @@ static struct apic __refdata apic_x2apic_uv_x = {
|
|||
|
||||
.read = native_apic_msr_read,
|
||||
.write = native_apic_msr_write,
|
||||
.eoi_write = native_apic_msr_eoi_write,
|
||||
.icr_read = native_x2apic_icr_read,
|
||||
.icr_write = native_x2apic_icr_write,
|
||||
.wait_icr_idle = native_x2apic_wait_icr_idle,
|
||||
|
|
|
|||
|
|
@ -1012,7 +1012,8 @@ void __init setup_arch(char **cmdline_p)
|
|||
init_cpu_to_node();
|
||||
|
||||
init_apic_mappings();
|
||||
ioapic_and_gsi_init();
|
||||
if (x86_io_apic_ops.init)
|
||||
x86_io_apic_ops.init();
|
||||
|
||||
kvm_guest_init();
|
||||
|
||||
|
|
|
|||
|
|
@ -18,6 +18,7 @@
|
|||
#include <asm/e820.h>
|
||||
#include <asm/time.h>
|
||||
#include <asm/irq.h>
|
||||
#include <asm/io_apic.h>
|
||||
#include <asm/pat.h>
|
||||
#include <asm/tsc.h>
|
||||
#include <asm/iommu.h>
|
||||
|
|
@ -119,3 +120,10 @@ struct x86_msi_ops x86_msi = {
|
|||
.teardown_msi_irqs = default_teardown_msi_irqs,
|
||||
.restore_msi_irqs = default_restore_msi_irqs,
|
||||
};
|
||||
|
||||
struct x86_io_apic_ops x86_io_apic_ops = {
|
||||
.init = native_io_apic_init_mappings,
|
||||
.read = native_io_apic_read,
|
||||
.write = native_io_apic_write,
|
||||
.modify = native_io_apic_modify,
|
||||
};
|
||||
|
|
|
|||
|
|
@ -445,7 +445,7 @@ static void ack_cobalt_irq(struct irq_data *data)
|
|||
|
||||
spin_lock_irqsave(&cobalt_lock, flags);
|
||||
disable_cobalt_irq(data);
|
||||
apic_write(APIC_EOI, APIC_EIO_ACK);
|
||||
apic_write(APIC_EOI, APIC_EOI_ACK);
|
||||
spin_unlock_irqrestore(&cobalt_lock, flags);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -20,5 +20,5 @@ obj-$(CONFIG_EVENT_TRACING) += trace.o
|
|||
obj-$(CONFIG_SMP) += smp.o
|
||||
obj-$(CONFIG_PARAVIRT_SPINLOCKS)+= spinlock.o
|
||||
obj-$(CONFIG_XEN_DEBUG_FS) += debugfs.o
|
||||
obj-$(CONFIG_XEN_DOM0) += vga.o
|
||||
obj-$(CONFIG_XEN_DOM0) += apic.o vga.o
|
||||
obj-$(CONFIG_SWIOTLB_XEN) += pci-swiotlb-xen.o
|
||||
|
|
|
|||
33
arch/x86/xen/apic.c
Normal file
33
arch/x86/xen/apic.c
Normal file
|
|
@ -0,0 +1,33 @@
|
|||
#include <linux/init.h>
|
||||
|
||||
#include <asm/x86_init.h>
|
||||
#include <asm/apic.h>
|
||||
#include <asm/xen/hypercall.h>
|
||||
|
||||
#include <xen/xen.h>
|
||||
#include <xen/interface/physdev.h>
|
||||
|
||||
unsigned int xen_io_apic_read(unsigned apic, unsigned reg)
|
||||
{
|
||||
struct physdev_apic apic_op;
|
||||
int ret;
|
||||
|
||||
apic_op.apic_physbase = mpc_ioapic_addr(apic);
|
||||
apic_op.reg = reg;
|
||||
ret = HYPERVISOR_physdev_op(PHYSDEVOP_apic_read, &apic_op);
|
||||
if (!ret)
|
||||
return apic_op.value;
|
||||
|
||||
/* fallback to return an emulated IO_APIC values */
|
||||
if (reg == 0x1)
|
||||
return 0x00170020;
|
||||
else if (reg == 0x0)
|
||||
return apic << 24;
|
||||
|
||||
return 0xfd;
|
||||
}
|
||||
|
||||
void __init xen_init_apic(void)
|
||||
{
|
||||
x86_io_apic_ops.read = xen_io_apic_read;
|
||||
}
|
||||
|
|
@ -1396,6 +1396,8 @@ asmlinkage void __init xen_start_kernel(void)
|
|||
xen_start_info->console.domU.mfn = 0;
|
||||
xen_start_info->console.domU.evtchn = 0;
|
||||
|
||||
xen_init_apic();
|
||||
|
||||
/* Make sure ACS will be enabled */
|
||||
pci_request_acs();
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1864,7 +1864,6 @@ pgd_t * __init xen_setup_kernel_pagetable(pgd_t *pgd,
|
|||
#endif /* CONFIG_X86_64 */
|
||||
|
||||
static unsigned char dummy_mapping[PAGE_SIZE] __page_aligned_bss;
|
||||
static unsigned char fake_ioapic_mapping[PAGE_SIZE] __page_aligned_bss;
|
||||
|
||||
static void xen_set_fixmap(unsigned idx, phys_addr_t phys, pgprot_t prot)
|
||||
{
|
||||
|
|
@ -1905,7 +1904,7 @@ static void xen_set_fixmap(unsigned idx, phys_addr_t phys, pgprot_t prot)
|
|||
* We just don't map the IO APIC - all access is via
|
||||
* hypercalls. Keep the address in the pte for reference.
|
||||
*/
|
||||
pte = pfn_pte(PFN_DOWN(__pa(fake_ioapic_mapping)), PAGE_KERNEL);
|
||||
pte = pfn_pte(PFN_DOWN(__pa(dummy_mapping)), PAGE_KERNEL);
|
||||
break;
|
||||
#endif
|
||||
|
||||
|
|
@ -2070,7 +2069,6 @@ void __init xen_init_mmu_ops(void)
|
|||
pv_mmu_ops = xen_mmu_ops;
|
||||
|
||||
memset(dummy_mapping, 0xff, PAGE_SIZE);
|
||||
memset(fake_ioapic_mapping, 0xfd, PAGE_SIZE);
|
||||
}
|
||||
|
||||
/* Protected by xen_reservation_lock. */
|
||||
|
|
|
|||
|
|
@ -92,11 +92,15 @@ struct dom0_vga_console_info;
|
|||
|
||||
#ifdef CONFIG_XEN_DOM0
|
||||
void __init xen_init_vga(const struct dom0_vga_console_info *, size_t size);
|
||||
void __init xen_init_apic(void);
|
||||
#else
|
||||
static inline void __init xen_init_vga(const struct dom0_vga_console_info *info,
|
||||
size_t size)
|
||||
{
|
||||
}
|
||||
static inline void __init xen_init_apic(void)
|
||||
{
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Declare an asm function, along with symbols needed to make it
|
||||
|
|
|
|||
Loading…
Reference in a new issue