arm64: Fix misspellings in comments.
Signed-off-by: Adam Buchbinder <adam.buchbinder@gmail.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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cd1b76bb73
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9 changed files with 11 additions and 11 deletions
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@ -313,7 +313,7 @@
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/*
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* There are two serial driver i.e. 8250 based simple serial
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* driver and APB DMA based serial driver for higher baudrate
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* and performace. To enable the 8250 based driver, the compatible
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* and performance. To enable the 8250 based driver, the compatible
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* is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable
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* the APB DMA based serial driver, the comptible is
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* "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart".
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@ -345,7 +345,7 @@
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/*
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* There are two serial driver i.e. 8250 based simple serial
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* driver and APB DMA based serial driver for higher baudrate
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* and performace. To enable the 8250 based driver, the compatible
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* and performance. To enable the 8250 based driver, the compatible
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* is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable
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* the APB DMA based serial driver, the comptible is
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* "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart".
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@ -48,7 +48,7 @@ static inline unsigned long ftrace_call_adjust(unsigned long addr)
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* See kernel/trace/trace_syscalls.c
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*
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* x86 code says:
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* If the user realy wants these, then they should use the
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* If the user really wants these, then they should use the
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* raw syscall tracepoints with filtering.
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*/
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#define ARCH_TRACE_IGNORE_COMPAT_SYSCALLS
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@ -61,7 +61,7 @@
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/*
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* The bits we set in HCR:
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* RW: 64bit by default, can be overriden for 32bit VMs
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* RW: 64bit by default, can be overridden for 32bit VMs
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* TAC: Trap ACTLR
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* TSC: Trap SMC
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* TVM: Trap VM ops (until M+C set in SCTLR_EL1)
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@ -99,8 +99,8 @@ enum vcpu_sysreg {
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TTBR1_EL1, /* Translation Table Base Register 1 */
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TCR_EL1, /* Translation Control Register */
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ESR_EL1, /* Exception Syndrome Register */
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AFSR0_EL1, /* Auxilary Fault Status Register 0 */
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AFSR1_EL1, /* Auxilary Fault Status Register 1 */
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AFSR0_EL1, /* Auxiliary Fault Status Register 0 */
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AFSR1_EL1, /* Auxiliary Fault Status Register 1 */
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FAR_EL1, /* Fault Address Register */
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MAIR_EL1, /* Memory Attribute Indirection Register */
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VBAR_EL1, /* Vector Base Address Register */
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@ -45,7 +45,7 @@
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* been used to perform kernel mode NEON in the meantime.
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*
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* For (a), we add a 'cpu' field to struct fpsimd_state, which gets updated to
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* the id of the current CPU everytime the state is loaded onto a CPU. For (b),
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* the id of the current CPU every time the state is loaded onto a CPU. For (b),
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* we add the per-cpu variable 'fpsimd_last_state' (below), which contains the
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* address of the userland FPSIMD state of the task that was loaded onto the CPU
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* the most recently, or NULL if kernel mode NEON has been performed after that.
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@ -292,8 +292,8 @@ static struct notifier_block kgdb_notifier = {
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};
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/*
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* kgdb_arch_init - Perform any architecture specific initalization.
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* This function will handle the initalization of any architecture
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* kgdb_arch_init - Perform any architecture specific initialization.
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* This function will handle the initialization of any architecture
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* specific callbacks.
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*/
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int kgdb_arch_init(void)
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@ -166,7 +166,7 @@ int copy_siginfo_to_user32(compat_siginfo_t __user *to, const siginfo_t *from)
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#ifdef BUS_MCEERR_AO
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/*
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* Other callers might not initialize the si_lsb field,
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* so check explicitely for the right codes here.
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* so check explicitly for the right codes here.
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*/
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if (from->si_signo == SIGBUS &&
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(from->si_code == BUS_MCEERR_AR || from->si_code == BUS_MCEERR_AO))
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@ -211,7 +211,7 @@ CPU_LE( lsr tmp2, tmp2, tmp1 )
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.Lunequal_proc:
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cbz diff, .Lremain8
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/*There is differnence occured in the latest comparison.*/
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/* There is difference occurred in the latest comparison. */
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.Lnot_limit:
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/*
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* For little endian,reverse the low significant equal bits into MSB,then
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