Merge branch 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull irq updates from Thomas Gleixner: "This lot provides: * Bugfixes for armada irq controller * Updates to renesas irq chip * Support for the TI-NSPIRE irq controller Not strictly a bug fix only pull request, but important updates for some of the arm Socs which I completely forgot to send last week. Seems like my obliviousness is getting worse, I just can't remember when it started" * 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: irqchip: Add support for TI-NSPIRE irqchip irqchip: renesas-irqc: Enable mask on suspend irqchip: renesas-irqc: Use lazy disable irqchip: armada-370-xp: fix MSI race condition irqchip: armada-370-xp: fix IPI race condition
This commit is contained in:
Linus Torvalds
commit
ef42c58a5b
4 changed files with 148 additions and 2 deletions
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@ -0,0 +1,18 @@
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TI-NSPIRE interrupt controller
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Required properties:
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- compatible: Compatible property value should be "lsi,zevio-intc".
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- reg: Physical base address of the controller and length of memory mapped
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region.
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- interrupt-controller : Identifies the node as an interrupt controller
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Example:
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interrupt-controller {
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compatible = "lsi,zevio-intc";
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interrupt-controller;
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reg = <0xDC000000 0x1000>;
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#interrupt-cells = <1>;
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};
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@ -21,6 +21,7 @@ obj-$(CONFIG_SIRF_IRQ) += irq-sirfsoc.o
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obj-$(CONFIG_RENESAS_INTC_IRQPIN) += irq-renesas-intc-irqpin.o
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obj-$(CONFIG_RENESAS_IRQC) += irq-renesas-irqc.o
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obj-$(CONFIG_VERSATILE_FPGA_IRQ) += irq-versatile-fpga.o
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obj-$(CONFIG_ARCH_NSPIRE) += irq-zevio.o
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obj-$(CONFIG_ARCH_VT8500) += irq-vt8500.o
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obj-$(CONFIG_TB10X_IRQC) += irq-tb10x.o
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obj-$(CONFIG_XTENSA) += irq-xtensa-pic.o
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@ -381,7 +381,7 @@ armada_370_xp_handle_irq(struct pt_regs *regs)
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ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS)
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& PCI_MSI_DOORBELL_MASK;
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writel(~PCI_MSI_DOORBELL_MASK, per_cpu_int_base +
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writel(~msimask, per_cpu_int_base +
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ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
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for (msinr = PCI_MSI_DOORBELL_START;
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@ -407,7 +407,7 @@ armada_370_xp_handle_irq(struct pt_regs *regs)
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ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS)
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& IPI_DOORBELL_MASK;
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writel(~IPI_DOORBELL_MASK, per_cpu_int_base +
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writel(~ipimask, per_cpu_int_base +
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ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
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/* Handle all pending doorbells */
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127
drivers/irqchip/irq-zevio.c
Normal file
127
drivers/irqchip/irq-zevio.c
Normal file
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@ -0,0 +1,127 @@
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/*
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* linux/drivers/irqchip/irq-zevio.c
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*
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* Copyright (C) 2013 Daniel Tang <tangrs@tangrs.id.au>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2, as
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* published by the Free Software Foundation.
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*
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*/
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <asm/mach/irq.h>
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#include <asm/exception.h>
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#include "irqchip.h"
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#define IO_STATUS 0x000
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#define IO_RAW_STATUS 0x004
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#define IO_ENABLE 0x008
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#define IO_DISABLE 0x00C
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#define IO_CURRENT 0x020
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#define IO_RESET 0x028
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#define IO_MAX_PRIOTY 0x02C
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#define IO_IRQ_BASE 0x000
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#define IO_FIQ_BASE 0x100
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#define IO_INVERT_SEL 0x200
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#define IO_STICKY_SEL 0x204
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#define IO_PRIORITY_SEL 0x300
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#define MAX_INTRS 32
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#define FIQ_START MAX_INTRS
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static struct irq_domain *zevio_irq_domain;
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static void __iomem *zevio_irq_io;
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static void zevio_irq_ack(struct irq_data *irqd)
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{
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(irqd);
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struct irq_chip_regs *regs =
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&container_of(irqd->chip, struct irq_chip_type, chip)->regs;
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readl(gc->reg_base + regs->ack);
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}
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static asmlinkage void __exception_irq_entry zevio_handle_irq(struct pt_regs *regs)
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{
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int irqnr;
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while (readl(zevio_irq_io + IO_STATUS)) {
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irqnr = readl(zevio_irq_io + IO_CURRENT);
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irqnr = irq_find_mapping(zevio_irq_domain, irqnr);
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handle_IRQ(irqnr, regs);
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};
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}
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static void __init zevio_init_irq_base(void __iomem *base)
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{
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/* Disable all interrupts */
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writel(~0, base + IO_DISABLE);
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/* Accept interrupts of all priorities */
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writel(0xF, base + IO_MAX_PRIOTY);
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/* Reset existing interrupts */
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readl(base + IO_RESET);
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}
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static int __init zevio_of_init(struct device_node *node,
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struct device_node *parent)
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{
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unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
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struct irq_chip_generic *gc;
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int ret;
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if (WARN_ON(zevio_irq_io || zevio_irq_domain))
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return -EBUSY;
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zevio_irq_io = of_iomap(node, 0);
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BUG_ON(!zevio_irq_io);
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/* Do not invert interrupt status bits */
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writel(~0, zevio_irq_io + IO_INVERT_SEL);
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/* Disable sticky interrupts */
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writel(0, zevio_irq_io + IO_STICKY_SEL);
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/* We don't use IRQ priorities. Set each IRQ to highest priority. */
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memset_io(zevio_irq_io + IO_PRIORITY_SEL, 0, MAX_INTRS * sizeof(u32));
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/* Init IRQ and FIQ */
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zevio_init_irq_base(zevio_irq_io + IO_IRQ_BASE);
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zevio_init_irq_base(zevio_irq_io + IO_FIQ_BASE);
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zevio_irq_domain = irq_domain_add_linear(node, MAX_INTRS,
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&irq_generic_chip_ops, NULL);
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BUG_ON(!zevio_irq_domain);
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ret = irq_alloc_domain_generic_chips(zevio_irq_domain, MAX_INTRS, 1,
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"zevio_intc", handle_level_irq,
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clr, 0, IRQ_GC_INIT_MASK_CACHE);
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BUG_ON(ret);
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gc = irq_get_domain_generic_chip(zevio_irq_domain, 0);
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gc->reg_base = zevio_irq_io;
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gc->chip_types[0].chip.irq_ack = zevio_irq_ack;
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gc->chip_types[0].chip.irq_mask = irq_gc_mask_disable_reg;
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gc->chip_types[0].chip.irq_unmask = irq_gc_unmask_enable_reg;
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gc->chip_types[0].regs.mask = IO_IRQ_BASE + IO_ENABLE;
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gc->chip_types[0].regs.enable = IO_IRQ_BASE + IO_ENABLE;
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gc->chip_types[0].regs.disable = IO_IRQ_BASE + IO_DISABLE;
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gc->chip_types[0].regs.ack = IO_IRQ_BASE + IO_RESET;
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set_handle_irq(zevio_handle_irq);
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pr_info("TI-NSPIRE classic IRQ controller\n");
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return 0;
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}
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IRQCHIP_DECLARE(zevio_irq, "lsi,zevio-intc", zevio_of_init);
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