phy: qcom-qmp: Add support for IPQ8074
Add definitions required to enable QMP phy support for IPQ8074. Signed-off-by: smuthayy <smuthayy@codeaurora.org> Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
This commit is contained in:
Varadarajan Narayanan
Kishon Vijay Abraham I
parent
2a9316b046
commit
eef243d04b
1 changed files with 124 additions and 0 deletions
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@ -59,6 +59,7 @@
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#define QSERDES_COM_PLL_RCTRL_MODE1 0x088
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#define QSERDES_COM_PLL_CCTRL_MODE0 0x090
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#define QSERDES_COM_PLL_CCTRL_MODE1 0x094
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#define QSERDES_COM_BIAS_EN_CTRL_BY_PSM 0x0a8
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#define QSERDES_COM_SYSCLK_EN_SEL 0x0ac
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#define QSERDES_COM_RESETSM_CNTRL 0x0b4
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#define QSERDES_COM_RESTRIM_CTRL 0x0bc
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@ -143,6 +144,11 @@
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#define QPHY_LOCK_DETECT_CONFIG3 0x88
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#define QPHY_PWRUP_RESET_DLY_TIME_AUXCLK 0xa0
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#define QPHY_LP_WAKEUP_DLY_TIME_AUXCLK 0xa4
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#define QPHY_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB 0x1A8
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#define QPHY_OSC_DTCT_ACTIONS 0x1AC
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#define QPHY_RX_SIGDET_LVL 0x1D8
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#define QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB 0x1DC
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#define QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1E0
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/* QPHY_SW_RESET bit */
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#define SW_RESET BIT(0)
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@ -382,6 +388,85 @@ static const struct qmp_phy_init_tbl msm8996_usb3_pcs_tbl[] = {
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QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG2, 0x08),
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};
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static const struct qmp_phy_init_tbl ipq8074_pcie_serdes_tbl[] = {
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QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
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QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
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QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0xf),
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QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x1),
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QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x0),
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QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0x1f),
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QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
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QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x6),
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QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0xf),
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QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x0),
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QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x1),
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QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x20),
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QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0xa),
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QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
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QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0xa),
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QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xa),
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QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
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QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x3),
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QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
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QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
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QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x0),
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QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0xD),
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QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xD04),
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QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
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QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x2),
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QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
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QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0xb),
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QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
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QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
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QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x0),
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QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
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QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x1),
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QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0xa),
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QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x1),
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QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
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QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x1),
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QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x2),
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QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x0),
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QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
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QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
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QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
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QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x7),
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};
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static const struct qmp_phy_init_tbl ipq8074_pcie_tx_tbl[] = {
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QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
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QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x6),
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QMP_PHY_INIT_CFG(QSERDES_TX_RES_CODE_LANE_OFFSET, 0x2),
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QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
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};
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static const struct qmp_phy_init_tbl ipq8074_pcie_rx_tbl[] = {
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QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
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QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
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QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x1),
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QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x0),
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QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
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QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
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QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x4),
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QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN_HALF, 0x4),
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};
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static const struct qmp_phy_init_tbl ipq8074_pcie_pcs_tbl[] = {
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QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x4),
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QMP_PHY_INIT_CFG(QPHY_OSC_DTCT_ACTIONS, 0x0),
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QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x40),
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QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x0),
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QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x40),
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QMP_PHY_INIT_CFG(QPHY_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB, 0x0),
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QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x40),
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QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x73),
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QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_LVL, 0x99),
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QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M6DB_V0, 0x15),
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QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0xe),
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QMP_PHY_INIT_CFG_L(QPHY_SW_RESET, 0x0),
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QMP_PHY_INIT_CFG_L(QPHY_START_CTRL, 0x3),
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};
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/* struct qmp_phy_cfg - per-PHY initialization config */
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struct qmp_phy_cfg {
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/* phy-type - PCIE/UFS/USB */
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@ -580,6 +665,42 @@ static const struct qmp_phy_cfg msm8996_usb3phy_cfg = {
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.mask_pcs_ready = PHYSTATUS,
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};
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/* list of resets */
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static const char * const ipq8074_pciephy_reset_l[] = {
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"phy", "common",
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};
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static const struct qmp_phy_cfg ipq8074_pciephy_cfg = {
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.type = PHY_TYPE_PCIE,
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.nlanes = 1,
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.serdes_tbl = ipq8074_pcie_serdes_tbl,
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.serdes_tbl_num = ARRAY_SIZE(ipq8074_pcie_serdes_tbl),
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.tx_tbl = ipq8074_pcie_tx_tbl,
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.tx_tbl_num = ARRAY_SIZE(ipq8074_pcie_tx_tbl),
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.rx_tbl = ipq8074_pcie_rx_tbl,
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.rx_tbl_num = ARRAY_SIZE(ipq8074_pcie_rx_tbl),
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.pcs_tbl = ipq8074_pcie_pcs_tbl,
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.pcs_tbl_num = ARRAY_SIZE(ipq8074_pcie_pcs_tbl),
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.clk_list = NULL,
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.num_clks = 0,
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.reset_list = ipq8074_pciephy_reset_l,
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.num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
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.vreg_list = NULL,
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.num_vregs = 0,
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.regs = pciephy_regs_layout,
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.start_ctrl = SERDES_START | PCS_START,
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.pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
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.mask_pcs_ready = PHYSTATUS,
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.has_phy_com_ctrl = false,
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.has_lane_rst = false,
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.has_pwrdn_delay = true,
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.pwrdn_delay_min = 995, /* us */
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.pwrdn_delay_max = 1005, /* us */
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};
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static void qcom_qmp_phy_configure(void __iomem *base,
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const unsigned int *regs,
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const struct qmp_phy_init_tbl tbl[],
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@ -1048,6 +1169,9 @@ static const struct of_device_id qcom_qmp_phy_of_match_table[] = {
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}, {
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.compatible = "qcom,msm8996-qmp-usb3-phy",
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.data = &msm8996_usb3phy_cfg,
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}, {
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.compatible = "qcom,ipq8074-qmp-pcie-phy",
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.data = &ipq8074_pciephy_cfg,
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},
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{ },
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};
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